platforms/85xx/mpc85xx_cds.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPC85xx setup and early boot code plus other random bits.
0004  *
0005  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
0006  *
0007  * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
0008  */
0009
0010 #include <linux/stddef.h>
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/errno.h>
0014 #include <linux/reboot.h>
0015 #include <linux/pci.h>
0016 #include <linux/kdev_t.h>
0017 #include <linux/major.h>
0018 #include <linux/console.h>
0019 #include <linux/delay.h>
0020 #include <linux/seq_file.h>
0021 #include <linux/initrd.h>
0022 #include <linux/interrupt.h>
0023 #include <linux/fsl_devices.h>
0024 #include <linux/of_address.h>
0025 #include <linux/of_irq.h>
0026 #include <linux/of_platform.h>
0027 #include <linux/pgtable.h>
0028
0029 #include <asm/page.h>
0030 #include <linux/atomic.h>
0031 #include <asm/time.h>
0032 #include <asm/io.h>
0033 #include <asm/machdep.h>
0034 #include <asm/ipic.h>
0035 #include <asm/pci-bridge.h>
0036 #include <asm/irq.h>
0037 #include <mm/mmu_decl.h>
0038 #include <asm/udbg.h>
0039 #include <asm/mpic.h>
0040 #include <asm/i8259.h>
0041
0042 #include <sysdev/fsl_soc.h>
0043 #include <sysdev/fsl_pci.h>
0044
0045 #include "mpc85xx.h"
0046
0047 /*
0048  * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
0049  * various logic and performs system control functions.
0050  * Here is the FPGA/CPLD register map.
0051  */
0052 struct cadmus_reg {
0053     u8 cm_ver;      /* Board version */
0054     u8 cm_csr;      /* General control/status */
0055     u8 cm_rst;      /* Reset control */
0056     u8 cm_hsclk;    /* High speed clock */
0057     u8 cm_hsxclk;   /* High speed clock extended */
0058     u8 cm_led;      /* LED data */
0059     u8 cm_pci;      /* PCI control/status */
0060     u8 cm_dma;      /* DMA control */
0061     u8 res[248];    /* Total 256 bytes */
0062 };
0063
0064 static struct cadmus_reg *cadmus;
0065
0066 #ifdef CONFIG_PCI
0067
0068 #define ARCADIA_HOST_BRIDGE_IDSEL   17
0069 #define ARCADIA_2ND_BRIDGE_IDSEL    3
0070
0071 static int mpc85xx_exclude_device(struct pci_controller *hose,
0072                   u_char bus, u_char devfn)
0073 {
0074     /* We explicitly do not go past the Tundra 320 Bridge */
0075     if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
0076         return PCIBIOS_DEVICE_NOT_FOUND;
0077     if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
0078         return PCIBIOS_DEVICE_NOT_FOUND;
0079     else
0080         return PCIBIOS_SUCCESSFUL;
0081 }
0082
0083 static int mpc85xx_cds_restart(struct notifier_block *this,
0084                    unsigned long mode, void *cmd)
0085 {
0086     struct pci_dev *dev;
0087     u_char tmp;
0088
0089     if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
0090                     NULL))) {
0091
0092         /* Use the VIA Super Southbridge to force a PCI reset */
0093         pci_read_config_byte(dev, 0x47, &tmp);
0094         pci_write_config_byte(dev, 0x47, tmp | 1);
0095
0096         /* Flush the outbound PCI write queues */
0097         pci_read_config_byte(dev, 0x47, &tmp);
0098
0099         /*
0100          *  At this point, the hardware reset should have triggered.
0101          *  However, if it doesn't work for some mysterious reason,
0102          *  just fall through to the default reset below.
0103          */
0104
0105         pci_dev_put(dev);
0106     }
0107
0108     /*
0109      *  If we can't find the VIA chip (maybe the P2P bridge is
0110      *  disabled) or the VIA chip reset didn't work, just return
0111      *  and let default reset sequence happen.
0112      */
0113     return NOTIFY_DONE;
0114 }
0115
0116 static int mpc85xx_cds_restart_register(void)
0117 {
0118     static struct notifier_block restart_handler;
0119
0120     restart_handler.notifier_call = mpc85xx_cds_restart;
0121     restart_handler.priority = 192;
0122
0123     return register_restart_handler(&restart_handler);
0124 }
0125 machine_arch_initcall(mpc85xx_cds, mpc85xx_cds_restart_register);
0126
0127
0128 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
0129 {
0130     u_char c;
0131     if (dev->vendor == PCI_VENDOR_ID_VIA) {
0132         switch (dev->device) {
0133         case PCI_DEVICE_ID_VIA_82C586_1:
0134             /*
0135              * U-Boot does not set the enable bits
0136              * for the IDE device. Force them on here.
0137              */
0138             pci_read_config_byte(dev, 0x40, &c);
0139             c |= 0x03; /* IDE: Chip Enable Bits */
0140             pci_write_config_byte(dev, 0x40, c);
0141
0142             /*
0143              * Since only primary interface works, force the
0144              * IDE function to standard primary IDE interrupt
0145              * w/ 8259 offset
0146              */
0147             dev->irq = 14;
0148             pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
0149             break;
0150         /*
0151          * Force legacy USB interrupt routing
0152          */
0153         case PCI_DEVICE_ID_VIA_82C586_2:
0154         /* There are two USB controllers.
0155          * Identify them by function number
0156          */
0157             if (PCI_FUNC(dev->devfn) == 3)
0158                 dev->irq = 11;
0159             else
0160                 dev->irq = 10;
0161             pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
0162         default:
0163             break;
0164         }
0165     }
0166 }
0167
0168 static void skip_fake_bridge(struct pci_dev *dev)
0169 {
0170     /* Make it an error to skip the fake bridge
0171      * in pci_setup_device() in probe.c */
0172     dev->hdr_type = 0x7f;
0173 }
0174 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
0175 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
0176 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
0177
0178 #define PCI_DEVICE_ID_IDT_TSI310    0x01a7
0179
0180 /*
0181  * Fix Tsi310 PCI-X bridge resource.
0182  * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
0183  * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
0184  */
0185 void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
0186 {
0187     struct pci_dev *dev = bus->self;
0188     struct resource *res = bus->resource[0];
0189
0190     if (dev != NULL &&
0191         dev->vendor == PCI_VENDOR_ID_IBM &&
0192         dev->device == PCI_DEVICE_ID_IDT_TSI310) {
0193         if (res) {
0194             res->start = 0;
0195             res->end   = 0x1fff;
0196             res->flags = IORESOURCE_IO;
0197             pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
0198             pr_info("mpc85xx_cds: %pR\n", res);
0199         }
0200     }
0201
0202     fsl_pcibios_fixup_bus(bus);
0203 }
0204
0205 #ifdef CONFIG_PPC_I8259
0206 static void mpc85xx_8259_cascade_handler(struct irq_desc *desc)
0207 {
0208     unsigned int cascade_irq = i8259_irq();
0209
0210     if (cascade_irq)
0211         /* handle an interrupt from the 8259 */
0212         generic_handle_irq(cascade_irq);
0213
0214     /* check for any interrupts from the shared IRQ line */
0215     handle_fasteoi_irq(desc);
0216 }
0217
0218 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
0219 {
0220     return IRQ_HANDLED;
0221 }
0222 #endif /* PPC_I8259 */
0223 #endif /* CONFIG_PCI */
0224
0225 static void __init mpc85xx_cds_pic_init(void)
0226 {
0227     struct mpic *mpic;
0228     mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
0229             0, 256, " OpenPIC  ");
0230     BUG_ON(mpic == NULL);
0231     mpic_init(mpic);
0232 }
0233
0234 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
0235 static int mpc85xx_cds_8259_attach(void)
0236 {
0237     int ret;
0238     struct device_node *np = NULL;
0239     struct device_node *cascade_node = NULL;
0240     int cascade_irq;
0241
0242     /* Initialize the i8259 controller */
0243     for_each_node_by_type(np, "interrupt-controller")
0244         if (of_device_is_compatible(np, "chrp,iic")) {
0245             cascade_node = np;
0246             break;
0247         }
0248
0249     if (cascade_node == NULL) {
0250         printk(KERN_DEBUG "Could not find i8259 PIC\n");
0251         return -ENODEV;
0252     }
0253
0254     cascade_irq = irq_of_parse_and_map(cascade_node, 0);
0255     if (!cascade_irq) {
0256         printk(KERN_ERR "Failed to map cascade interrupt\n");
0257         return -ENXIO;
0258     }
0259
0260     i8259_init(cascade_node, 0);
0261     of_node_put(cascade_node);
0262
0263     /*
0264      *  Hook the interrupt to make sure desc->action is never NULL.
0265      *  This is required to ensure that the interrupt does not get
0266      *  disabled when the last user of the shared IRQ line frees their
0267      *  interrupt.
0268      */
0269     ret = request_irq(cascade_irq, mpc85xx_8259_cascade_action,
0270               IRQF_SHARED | IRQF_NO_THREAD, "8259 cascade",
0271               cascade_node);
0272     if (ret) {
0273         printk(KERN_ERR "Failed to setup cascade interrupt\n");
0274         return ret;
0275     }
0276
0277     /* Success. Connect our low-level cascade handler. */
0278     irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
0279
0280     return 0;
0281 }
0282 machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
0283
0284 #endif /* CONFIG_PPC_I8259 */
0285
0286 static void __init mpc85xx_cds_pci_assign_primary(void)
0287 {
0288 #ifdef CONFIG_PCI
0289     struct device_node *np;
0290
0291     if (fsl_pci_primary)
0292         return;
0293
0294     /*
0295      * MPC85xx_CDS has ISA bridge but unfortunately there is no
0296      * isa node in device tree. We now looking for i8259 node as
0297      * a workaround for such a broken device tree. This routine
0298      * is for complying to all device trees.
0299      */
0300     np = of_find_node_by_name(NULL, "i8259");
0301     while ((fsl_pci_primary = of_get_parent(np))) {
0302         of_node_put(np);
0303         np = fsl_pci_primary;
0304
0305         if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
0306             of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
0307             of_device_is_available(np))
0308             return;
0309     }
0310 #endif
0311 }
0312
0313 /*
0314  * Setup the architecture
0315  */
0316 static void __init mpc85xx_cds_setup_arch(void)
0317 {
0318     struct device_node *np;
0319     int cds_pci_slot;
0320
0321     if (ppc_md.progress)
0322         ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
0323
0324     np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
0325     if (!np) {
0326         pr_err("Could not find FPGA node.\n");
0327         return;
0328     }
0329
0330     cadmus = of_iomap(np, 0);
0331     of_node_put(np);
0332     if (!cadmus) {
0333         pr_err("Fail to map FPGA area.\n");
0334         return;
0335     }
0336
0337     if (ppc_md.progress) {
0338         char buf[40];
0339         cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
0340         snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
0341                 in_8(&cadmus->cm_ver), cds_pci_slot);
0342         ppc_md.progress(buf, 0);
0343     }
0344
0345 #ifdef CONFIG_PCI
0346     ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
0347     ppc_md.pci_exclude_device = mpc85xx_exclude_device;
0348 #endif
0349
0350     mpc85xx_cds_pci_assign_primary();
0351     fsl_pci_assign_primary();
0352 }
0353
0354 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
0355 {
0356     uint pvid, svid, phid1;
0357
0358     pvid = mfspr(SPRN_PVR);
0359     svid = mfspr(SPRN_SVR);
0360
0361     seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
0362     seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
0363             in_8(&cadmus->cm_ver));
0364     seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
0365     seq_printf(m, "SVR\t\t: 0x%x\n", svid);
0366
0367     /* Display cpu Pll setting */
0368     phid1 = mfspr(SPRN_HID1);
0369     seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
0370 }
0371
0372
0373 /*
0374  * Called very early, device-tree isn't unflattened
0375  */
0376 static int __init mpc85xx_cds_probe(void)
0377 {
0378     return of_machine_is_compatible("MPC85xxCDS");
0379 }
0380
0381 machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
0382
0383 define_machine(mpc85xx_cds) {
0384     .name       = "MPC85xx CDS",
0385     .probe      = mpc85xx_cds_probe,
0386     .setup_arch = mpc85xx_cds_setup_arch,
0387     .init_IRQ   = mpc85xx_cds_pic_init,
0388     .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
0389     .get_irq    = mpic_get_irq,
0390 #ifdef CONFIG_PCI
0391     .pcibios_fixup_bus  = mpc85xx_cds_fixup_bus,
0392     .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
0393 #endif
0394     .calibrate_decr = generic_calibrate_decr,
0395     .progress   = udbg_progress,
0396 };