platforms/85xx/mpc85xx_ads.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPC85xx setup and early boot code plus other random bits.
0004  *
0005  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
0006  *
0007  * Copyright 2005 Freescale Semiconductor Inc.
0008  */
0009
0010 #include <linux/stddef.h>
0011 #include <linux/kernel.h>
0012 #include <linux/pci.h>
0013 #include <linux/kdev_t.h>
0014 #include <linux/delay.h>
0015 #include <linux/seq_file.h>
0016 #include <linux/of_platform.h>
0017
0018 #include <asm/time.h>
0019 #include <asm/machdep.h>
0020 #include <asm/pci-bridge.h>
0021 #include <asm/mpic.h>
0022 #include <mm/mmu_decl.h>
0023 #include <asm/udbg.h>
0024
0025 #include <sysdev/fsl_soc.h>
0026 #include <sysdev/fsl_pci.h>
0027
0028 #ifdef CONFIG_CPM2
0029 #include <asm/cpm2.h>
0030 #include <sysdev/cpm2_pic.h>
0031 #endif
0032
0033 #include "mpc85xx.h"
0034
0035 static void __init mpc85xx_ads_pic_init(void)
0036 {
0037     struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
0038             0, 256, " OpenPIC  ");
0039     BUG_ON(mpic == NULL);
0040     mpic_init(mpic);
0041
0042     mpc85xx_cpm2_pic_init();
0043 }
0044
0045 /*
0046  * Setup the architecture
0047  */
0048 #ifdef CONFIG_CPM2
0049 struct cpm_pin {
0050     int port, pin, flags;
0051 };
0052
0053 static const struct cpm_pin mpc8560_ads_pins[] = {
0054     /* SCC1 */
0055     {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0056     {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0057     {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0058
0059     /* SCC2 */
0060     {2, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0061     {2, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0062     {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0063     {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0064     {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0065
0066     /* FCC2 */
0067     {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0068     {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0069     {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0070     {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0071     {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0072     {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0073     {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0074     {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0075     {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0076     {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0077     {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0078     {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0079     {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0080     {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0081     {2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK14 */
0082     {2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK13 */
0083
0084     /* FCC3 */
0085     {1, 4, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0086     {1, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0087     {1, 6, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0088     {1, 8, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0089     {1, 9, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0090     {1, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0091     {1, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0092     {1, 12, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0093     {1, 13, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0094     {1, 14, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0095     {1, 15, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0096     {1, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0097     {1, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0098     {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK16 */
0099     {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK15 */
0100     {2, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0101 };
0102
0103 static void __init init_ioports(void)
0104 {
0105     int i;
0106
0107     for (i = 0; i < ARRAY_SIZE(mpc8560_ads_pins); i++) {
0108         const struct cpm_pin *pin = &mpc8560_ads_pins[i];
0109         cpm2_set_pin(pin->port, pin->pin, pin->flags);
0110     }
0111
0112     cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
0113     cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
0114     cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
0115     cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
0116     cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
0117     cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
0118     cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK15, CPM_CLK_RX);
0119     cpm2_clk_setup(CPM_CLK_FCC3, CPM_CLK16, CPM_CLK_TX);
0120 }
0121 #endif
0122
0123 static void __init mpc85xx_ads_setup_arch(void)
0124 {
0125     if (ppc_md.progress)
0126         ppc_md.progress("mpc85xx_ads_setup_arch()", 0);
0127
0128 #ifdef CONFIG_CPM2
0129     cpm2_reset();
0130     init_ioports();
0131 #endif
0132
0133     fsl_pci_assign_primary();
0134 }
0135
0136 static void mpc85xx_ads_show_cpuinfo(struct seq_file *m)
0137 {
0138     uint pvid, svid, phid1;
0139
0140     pvid = mfspr(SPRN_PVR);
0141     svid = mfspr(SPRN_SVR);
0142
0143     seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
0144     seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
0145     seq_printf(m, "SVR\t\t: 0x%x\n", svid);
0146
0147     /* Display cpu Pll setting */
0148     phid1 = mfspr(SPRN_HID1);
0149     seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
0150 }
0151
0152 machine_arch_initcall(mpc85xx_ads, mpc85xx_common_publish_devices);
0153
0154 /*
0155  * Called very early, device-tree isn't unflattened
0156  */
0157 static int __init mpc85xx_ads_probe(void)
0158 {
0159     return of_machine_is_compatible("MPC85xxADS");
0160 }
0161
0162 define_machine(mpc85xx_ads) {
0163     .name           = "MPC85xx ADS",
0164     .probe          = mpc85xx_ads_probe,
0165     .setup_arch     = mpc85xx_ads_setup_arch,
0166     .init_IRQ       = mpc85xx_ads_pic_init,
0167     .show_cpuinfo       = mpc85xx_ads_show_cpuinfo,
0168     .get_irq        = mpic_get_irq,
0169     .calibrate_decr     = generic_calibrate_decr,
0170     .progress       = udbg_progress,
0171 };