platforms/85xx/ksi8560.c

0001 /*
0002  * Board setup routines for the Emerson KSI8560
0003  *
0004  * Author: Alexandr Smirnov <asmirnov@ru.mvista.com>
0005  *
0006  * Based on mpc85xx_ads.c maintained by Kumar Gala
0007  *
0008  * 2008 (c) MontaVista, Software, Inc.  This file is licensed under
0009  * the terms of the GNU General Public License version 2.  This program
0010  * is licensed "as is" without any warranty of any kind, whether express
0011  * or implied.
0012  *
0013  */
0014
0015 #include <linux/stddef.h>
0016 #include <linux/kernel.h>
0017 #include <linux/pci.h>
0018 #include <linux/kdev_t.h>
0019 #include <linux/delay.h>
0020 #include <linux/seq_file.h>
0021 #include <linux/of_platform.h>
0022
0023 #include <asm/time.h>
0024 #include <asm/machdep.h>
0025 #include <asm/pci-bridge.h>
0026 #include <asm/mpic.h>
0027 #include <mm/mmu_decl.h>
0028 #include <asm/udbg.h>
0029
0030 #include <sysdev/fsl_soc.h>
0031 #include <sysdev/fsl_pci.h>
0032
0033 #include <asm/cpm2.h>
0034 #include <sysdev/cpm2_pic.h>
0035
0036 #include "mpc85xx.h"
0037
0038 #define KSI8560_CPLD_HVR        0x04 /* Hardware Version Register */
0039 #define KSI8560_CPLD_PVR        0x08 /* PLD Version Register */
0040 #define KSI8560_CPLD_RCR1       0x30 /* Reset Command Register 1 */
0041
0042 #define KSI8560_CPLD_RCR1_CPUHR     0x80 /* CPU Hard Reset */
0043
0044 static void __iomem *cpld_base = NULL;
0045
0046 static void __noreturn machine_restart(char *cmd)
0047 {
0048     if (cpld_base)
0049         out_8(cpld_base + KSI8560_CPLD_RCR1, KSI8560_CPLD_RCR1_CPUHR);
0050     else
0051         printk(KERN_ERR "Can't find CPLD base, hang forever\n");
0052
0053     for (;;);
0054 }
0055
0056 static void __init ksi8560_pic_init(void)
0057 {
0058     struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
0059             0, 256, " OpenPIC  ");
0060     BUG_ON(mpic == NULL);
0061     mpic_init(mpic);
0062
0063     mpc85xx_cpm2_pic_init();
0064 }
0065
0066 #ifdef CONFIG_CPM2
0067 /*
0068  * Setup I/O ports
0069  */
0070 struct cpm_pin {
0071     int port, pin, flags;
0072 };
0073
0074 static struct cpm_pin __initdata ksi8560_pins[] = {
0075     /* SCC1 */
0076     {3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0077     {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0078     {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0079
0080     /* SCC2 */
0081     {3, 26, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0082     {3, 27, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0083     {3, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0084
0085     /* FCC1 */
0086     {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0087     {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0088     {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0089     {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0090     {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0091     {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0092     {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0093     {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0094     {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0095     {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0096     {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0097     {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0098     {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0099     {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0100     {2, 23, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK9 */
0101     {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY}, /* CLK10 */
0102
0103 };
0104
0105 static void __init init_ioports(void)
0106 {
0107     int i;
0108
0109     for (i = 0; i < ARRAY_SIZE(ksi8560_pins); i++) {
0110         struct cpm_pin *pin = &ksi8560_pins[i];
0111         cpm2_set_pin(pin->port, pin->pin, pin->flags);
0112     }
0113
0114     cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
0115     cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
0116     cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_RX);
0117     cpm2_clk_setup(CPM_CLK_SCC2, CPM_BRG2, CPM_CLK_TX);
0118     cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK9, CPM_CLK_RX);
0119     cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
0120 }
0121 #endif
0122
0123 /*
0124  * Setup the architecture
0125  */
0126 static void __init ksi8560_setup_arch(void)
0127 {
0128     struct device_node *cpld;
0129
0130     cpld = of_find_compatible_node(NULL, NULL, "emerson,KSI8560-cpld");
0131     if (cpld)
0132         cpld_base = of_iomap(cpld, 0);
0133     else
0134         printk(KERN_ERR "Can't find CPLD in device tree\n");
0135
0136     if (ppc_md.progress)
0137         ppc_md.progress("ksi8560_setup_arch()", 0);
0138
0139 #ifdef CONFIG_CPM2
0140     cpm2_reset();
0141     init_ioports();
0142 #endif
0143 }
0144
0145 static void ksi8560_show_cpuinfo(struct seq_file *m)
0146 {
0147     uint pvid, svid, phid1;
0148
0149     pvid = mfspr(SPRN_PVR);
0150     svid = mfspr(SPRN_SVR);
0151
0152     seq_printf(m, "Vendor\t\t: Emerson Network Power\n");
0153     seq_printf(m, "Board\t\t: KSI8560\n");
0154
0155     if (cpld_base) {
0156         seq_printf(m, "Hardware rev\t: %d\n",
0157                     in_8(cpld_base + KSI8560_CPLD_HVR));
0158         seq_printf(m, "CPLD rev\t: %d\n",
0159                     in_8(cpld_base + KSI8560_CPLD_PVR));
0160     } else
0161         seq_printf(m, "Unknown Hardware and CPLD revs\n");
0162
0163     seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
0164     seq_printf(m, "SVR\t\t: 0x%x\n", svid);
0165
0166     /* Display cpu Pll setting */
0167     phid1 = mfspr(SPRN_HID1);
0168     seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
0169 }
0170
0171 machine_device_initcall(ksi8560, mpc85xx_common_publish_devices);
0172
0173 /*
0174  * Called very early, device-tree isn't unflattened
0175  */
0176 static int __init ksi8560_probe(void)
0177 {
0178     return of_machine_is_compatible("emerson,KSI8560");
0179 }
0180
0181 define_machine(ksi8560) {
0182     .name           = "KSI8560",
0183     .probe          = ksi8560_probe,
0184     .setup_arch     = ksi8560_setup_arch,
0185     .init_IRQ       = ksi8560_pic_init,
0186     .show_cpuinfo       = ksi8560_show_cpuinfo,
0187     .get_irq        = mpic_get_irq,
0188     .restart        = machine_restart,
0189     .calibrate_decr     = generic_calibrate_decr,
0190 };