platforms/85xx/ge_imp3a.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * GE IMP3A Board Setup
0004  *
0005  * Author Martyn Welch <martyn.welch@ge.com>
0006  *
0007  * Copyright 2010 GE Intelligent Platforms Embedded Systems, Inc.
0008  *
0009  * Based on: mpc85xx_ds.c (MPC85xx DS Board Setup)
0010  * Copyright 2007 Freescale Semiconductor Inc.
0011  */
0012
0013 #include <linux/stddef.h>
0014 #include <linux/kernel.h>
0015 #include <linux/pci.h>
0016 #include <linux/kdev_t.h>
0017 #include <linux/delay.h>
0018 #include <linux/seq_file.h>
0019 #include <linux/interrupt.h>
0020 #include <linux/of_address.h>
0021 #include <linux/of_platform.h>
0022
0023 #include <asm/time.h>
0024 #include <asm/machdep.h>
0025 #include <asm/pci-bridge.h>
0026 #include <mm/mmu_decl.h>
0027 #include <asm/udbg.h>
0028 #include <asm/mpic.h>
0029 #include <asm/swiotlb.h>
0030 #include <asm/nvram.h>
0031
0032 #include <sysdev/fsl_soc.h>
0033 #include <sysdev/fsl_pci.h>
0034 #include "smp.h"
0035
0036 #include "mpc85xx.h"
0037 #include <sysdev/ge/ge_pic.h>
0038
0039 void __iomem *imp3a_regs;
0040
0041 void __init ge_imp3a_pic_init(void)
0042 {
0043     struct mpic *mpic;
0044     struct device_node *np;
0045     struct device_node *cascade_node = NULL;
0046
0047     if (of_machine_is_compatible("fsl,MPC8572DS-CAMP")) {
0048         mpic = mpic_alloc(NULL, 0,
0049             MPIC_NO_RESET |
0050             MPIC_BIG_ENDIAN |
0051             MPIC_SINGLE_DEST_CPU,
0052             0, 256, " OpenPIC  ");
0053     } else {
0054         mpic = mpic_alloc(NULL, 0,
0055               MPIC_BIG_ENDIAN |
0056               MPIC_SINGLE_DEST_CPU,
0057             0, 256, " OpenPIC  ");
0058     }
0059
0060     BUG_ON(mpic == NULL);
0061     mpic_init(mpic);
0062     /*
0063      * There is a simple interrupt handler in the main FPGA, this needs
0064      * to be cascaded into the MPIC
0065      */
0066     for_each_node_by_type(np, "interrupt-controller")
0067         if (of_device_is_compatible(np, "gef,fpga-pic-1.00")) {
0068             cascade_node = np;
0069             break;
0070         }
0071
0072     if (cascade_node == NULL) {
0073         printk(KERN_WARNING "IMP3A: No FPGA PIC\n");
0074         return;
0075     }
0076
0077     gef_pic_init(cascade_node);
0078     of_node_put(cascade_node);
0079 }
0080
0081 static void __init ge_imp3a_pci_assign_primary(void)
0082 {
0083 #ifdef CONFIG_PCI
0084     struct device_node *np;
0085     struct resource rsrc;
0086
0087     for_each_node_by_type(np, "pci") {
0088         if (of_device_is_compatible(np, "fsl,mpc8540-pci") ||
0089             of_device_is_compatible(np, "fsl,mpc8548-pcie") ||
0090             of_device_is_compatible(np, "fsl,p2020-pcie")) {
0091             of_address_to_resource(np, 0, &rsrc);
0092             if ((rsrc.start & 0xfffff) == 0x9000)
0093                 fsl_pci_primary = np;
0094         }
0095     }
0096 #endif
0097 }
0098
0099 /*
0100  * Setup the architecture
0101  */
0102 static void __init ge_imp3a_setup_arch(void)
0103 {
0104     struct device_node *regs;
0105
0106     if (ppc_md.progress)
0107         ppc_md.progress("ge_imp3a_setup_arch()", 0);
0108
0109     mpc85xx_smp_init();
0110
0111     ge_imp3a_pci_assign_primary();
0112
0113     swiotlb_detect_4g();
0114
0115     /* Remap basic board registers */
0116     regs = of_find_compatible_node(NULL, NULL, "ge,imp3a-fpga-regs");
0117     if (regs) {
0118         imp3a_regs = of_iomap(regs, 0);
0119         if (imp3a_regs == NULL)
0120             printk(KERN_WARNING "Unable to map board registers\n");
0121         of_node_put(regs);
0122     }
0123
0124 #if defined(CONFIG_MMIO_NVRAM)
0125     mmio_nvram_init();
0126 #endif
0127
0128     printk(KERN_INFO "GE Intelligent Platforms IMP3A 3U cPCI SBC\n");
0129 }
0130
0131 /* Return the PCB revision */
0132 static unsigned int ge_imp3a_get_pcb_rev(void)
0133 {
0134     unsigned int reg;
0135
0136     reg = ioread16(imp3a_regs);
0137     return (reg >> 8) & 0xff;
0138 }
0139
0140 /* Return the board (software) revision */
0141 static unsigned int ge_imp3a_get_board_rev(void)
0142 {
0143     unsigned int reg;
0144
0145     reg = ioread16(imp3a_regs + 0x2);
0146     return reg & 0xff;
0147 }
0148
0149 /* Return the FPGA revision */
0150 static unsigned int ge_imp3a_get_fpga_rev(void)
0151 {
0152     unsigned int reg;
0153
0154     reg = ioread16(imp3a_regs + 0x2);
0155     return (reg >> 8) & 0xff;
0156 }
0157
0158 /* Return compactPCI Geographical Address */
0159 static unsigned int ge_imp3a_get_cpci_geo_addr(void)
0160 {
0161     unsigned int reg;
0162
0163     reg = ioread16(imp3a_regs + 0x6);
0164     return (reg & 0x0f00) >> 8;
0165 }
0166
0167 /* Return compactPCI System Controller Status */
0168 static unsigned int ge_imp3a_get_cpci_is_syscon(void)
0169 {
0170     unsigned int reg;
0171
0172     reg = ioread16(imp3a_regs + 0x6);
0173     return reg & (1 << 12);
0174 }
0175
0176 static void ge_imp3a_show_cpuinfo(struct seq_file *m)
0177 {
0178     seq_printf(m, "Vendor\t\t: GE Intelligent Platforms\n");
0179
0180     seq_printf(m, "Revision\t: %u%c\n", ge_imp3a_get_pcb_rev(),
0181         ('A' + ge_imp3a_get_board_rev() - 1));
0182
0183     seq_printf(m, "FPGA Revision\t: %u\n", ge_imp3a_get_fpga_rev());
0184
0185     seq_printf(m, "cPCI geo. addr\t: %u\n", ge_imp3a_get_cpci_geo_addr());
0186
0187     seq_printf(m, "cPCI syscon\t: %s\n",
0188         ge_imp3a_get_cpci_is_syscon() ? "yes" : "no");
0189 }
0190
0191 /*
0192  * Called very early, device-tree isn't unflattened
0193  */
0194 static int __init ge_imp3a_probe(void)
0195 {
0196     return of_machine_is_compatible("ge,IMP3A");
0197 }
0198
0199 machine_arch_initcall(ge_imp3a, mpc85xx_common_publish_devices);
0200
0201 define_machine(ge_imp3a) {
0202     .name           = "GE_IMP3A",
0203     .probe          = ge_imp3a_probe,
0204     .setup_arch     = ge_imp3a_setup_arch,
0205     .init_IRQ       = ge_imp3a_pic_init,
0206     .show_cpuinfo       = ge_imp3a_show_cpuinfo,
0207 #ifdef CONFIG_PCI
0208     .pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
0209     .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
0210 #endif
0211     .get_irq        = mpic_get_irq,
0212     .calibrate_decr     = generic_calibrate_decr,
0213     .progress       = udbg_progress,
0214 };