platforms/85xx/corenet_generic.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Corenet based SoC DS Setup
0004  *
0005  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
0006  *
0007  * Copyright 2009-2011 Freescale Semiconductor Inc.
0008  */
0009
0010 #include <linux/kernel.h>
0011 #include <linux/pci.h>
0012 #include <linux/kdev_t.h>
0013 #include <linux/delay.h>
0014 #include <linux/interrupt.h>
0015 #include <linux/pgtable.h>
0016
0017 #include <asm/time.h>
0018 #include <asm/machdep.h>
0019 #include <asm/pci-bridge.h>
0020 #include <asm/ppc-pci.h>
0021 #include <mm/mmu_decl.h>
0022 #include <asm/udbg.h>
0023 #include <asm/mpic.h>
0024 #include <asm/ehv_pic.h>
0025 #include <asm/swiotlb.h>
0026
0027 #include <linux/of_platform.h>
0028 #include <sysdev/fsl_soc.h>
0029 #include <sysdev/fsl_pci.h>
0030 #include "smp.h"
0031 #include "mpc85xx.h"
0032
0033 void __init corenet_gen_pic_init(void)
0034 {
0035     struct mpic *mpic;
0036     unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
0037         MPIC_NO_RESET;
0038
0039     if (!IS_ENABLED(CONFIG_HOTPLUG_CPU) && !IS_ENABLED(CONFIG_KEXEC_CORE))
0040         flags |= MPIC_ENABLE_COREINT;
0041
0042     mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC  ");
0043     BUG_ON(mpic == NULL);
0044
0045     mpic_init(mpic);
0046 }
0047
0048 /*
0049  * Setup the architecture
0050  */
0051 void __init corenet_gen_setup_arch(void)
0052 {
0053     mpc85xx_smp_init();
0054
0055     swiotlb_detect_4g();
0056
0057     pr_info("%s board\n", ppc_md.name);
0058 }
0059
0060 static const struct of_device_id of_device_ids[] = {
0061     {
0062         .compatible = "simple-bus"
0063     },
0064     {
0065         .compatible = "mdio-mux-gpio"
0066     },
0067     {
0068         .compatible = "fsl,fpga-ngpixis"
0069     },
0070     {
0071         .compatible = "fsl,fpga-qixis"
0072     },
0073     {
0074         .compatible = "fsl,srio",
0075     },
0076     {
0077         .compatible = "fsl,p4080-pcie",
0078     },
0079     {
0080         .compatible = "fsl,qoriq-pcie-v2.2",
0081     },
0082     {
0083         .compatible = "fsl,qoriq-pcie-v2.3",
0084     },
0085     {
0086         .compatible = "fsl,qoriq-pcie-v2.4",
0087     },
0088     {
0089         .compatible = "fsl,qoriq-pcie-v3.0",
0090     },
0091     {
0092         .compatible = "fsl,qe",
0093     },
0094     /* The following two are for the Freescale hypervisor */
0095     {
0096         .name       = "hypervisor",
0097     },
0098     {
0099         .name       = "handles",
0100     },
0101     {}
0102 };
0103
0104 int __init corenet_gen_publish_devices(void)
0105 {
0106     return of_platform_bus_probe(NULL, of_device_ids, NULL);
0107 }
0108 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
0109
0110 static const char * const boards[] __initconst = {
0111     "fsl,P2041RDB",
0112     "fsl,P3041DS",
0113     "fsl,OCA4080",
0114     "fsl,P4080DS",
0115     "fsl,P5020DS",
0116     "fsl,P5040DS",
0117     "fsl,T2080QDS",
0118     "fsl,T2080RDB",
0119     "fsl,T2081QDS",
0120     "fsl,T4240QDS",
0121     "fsl,T4240RDB",
0122     "fsl,B4860QDS",
0123     "fsl,B4420QDS",
0124     "fsl,B4220QDS",
0125     "fsl,T1023RDB",
0126     "fsl,T1024QDS",
0127     "fsl,T1024RDB",
0128     "fsl,T1040D4RDB",
0129     "fsl,T1042D4RDB",
0130     "fsl,T1040QDS",
0131     "fsl,T1042QDS",
0132     "fsl,T1040RDB",
0133     "fsl,T1042RDB",
0134     "fsl,T1042RDB_PI",
0135     "keymile,kmcent2",
0136     "keymile,kmcoge4",
0137     "varisys,CYRUS",
0138     NULL
0139 };
0140
0141 /*
0142  * Called very early, device-tree isn't unflattened
0143  */
0144 static int __init corenet_generic_probe(void)
0145 {
0146     char hv_compat[24];
0147     int i;
0148 #ifdef CONFIG_SMP
0149     extern struct smp_ops_t smp_85xx_ops;
0150 #endif
0151
0152     if (of_device_compatible_match(of_root, boards))
0153         return 1;
0154
0155     /* Check if we're running under the Freescale hypervisor */
0156     for (i = 0; boards[i]; i++) {
0157         snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
0158         if (of_machine_is_compatible(hv_compat)) {
0159             ppc_md.init_IRQ = ehv_pic_init;
0160
0161             ppc_md.get_irq = ehv_pic_get_irq;
0162             ppc_md.restart = fsl_hv_restart;
0163             pm_power_off = fsl_hv_halt;
0164             ppc_md.halt = fsl_hv_halt;
0165 #ifdef CONFIG_SMP
0166             /*
0167              * Disable the timebase sync operations because we
0168              * can't write to the timebase registers under the
0169              * hypervisor.
0170              */
0171             smp_85xx_ops.give_timebase = NULL;
0172             smp_85xx_ops.take_timebase = NULL;
0173 #endif
0174             return 1;
0175         }
0176     }
0177
0178     return 0;
0179 }
0180
0181 define_machine(corenet_generic) {
0182     .name           = "CoreNet Generic",
0183     .probe          = corenet_generic_probe,
0184     .setup_arch     = corenet_gen_setup_arch,
0185     .init_IRQ       = corenet_gen_pic_init,
0186 #ifdef CONFIG_PCI
0187     .pcibios_fixup_bus  = fsl_pcibios_fixup_bus,
0188     .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
0189 #endif
0190 /*
0191  * Core reset may cause issues if using the proxy mode of MPIC.
0192  * So, use the mixed mode of MPIC if enabling CPU hotplug.
0193  *
0194  * Likewise, problems have been seen with kexec when coreint is enabled.
0195  */
0196 #if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_KEXEC_CORE)
0197     .get_irq        = mpic_get_irq,
0198 #else
0199     .get_irq        = mpic_get_coreint_irq,
0200 #endif
0201     .calibrate_decr     = generic_calibrate_decr,
0202     .progress       = udbg_progress,
0203 #ifdef CONFIG_PPC64
0204     .power_save     = book3e_idle,
0205 #else
0206     .power_save     = e500_idle,
0207 #endif
0208 };