platforms/85xx/common.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Routines common to most mpc85xx-based boards.
0004  */
0005
0006 #include <linux/of_irq.h>
0007 #include <linux/of_platform.h>
0008
0009 #include <asm/fsl_pm.h>
0010 #include <soc/fsl/qe/qe.h>
0011 #include <sysdev/cpm2_pic.h>
0012
0013 #include "mpc85xx.h"
0014
0015 const struct fsl_pm_ops *qoriq_pm_ops;
0016
0017 static const struct of_device_id mpc85xx_common_ids[] __initconst = {
0018     { .type = "soc", },
0019     { .compatible = "soc", },
0020     { .compatible = "simple-bus", },
0021     { .name = "cpm", },
0022     { .name = "localbus", },
0023     { .compatible = "gianfar", },
0024     { .compatible = "fsl,qe", },
0025     { .compatible = "fsl,cpm2", },
0026     { .compatible = "fsl,srio", },
0027     /* So that the DMA channel nodes can be probed individually: */
0028     { .compatible = "fsl,eloplus-dma", },
0029     /* For the PMC driver */
0030     { .compatible = "fsl,mpc8548-guts", },
0031     /* Probably unnecessary? */
0032     { .compatible = "gpio-leds", },
0033     /* For all PCI controllers */
0034     { .compatible = "fsl,mpc8540-pci", },
0035     { .compatible = "fsl,mpc8548-pcie", },
0036     { .compatible = "fsl,p1022-pcie", },
0037     { .compatible = "fsl,p1010-pcie", },
0038     { .compatible = "fsl,p1023-pcie", },
0039     { .compatible = "fsl,p4080-pcie", },
0040     { .compatible = "fsl,qoriq-pcie-v2.4", },
0041     { .compatible = "fsl,qoriq-pcie-v2.3", },
0042     { .compatible = "fsl,qoriq-pcie-v2.2", },
0043     { .compatible = "fsl,fman", },
0044     {},
0045 };
0046
0047 int __init mpc85xx_common_publish_devices(void)
0048 {
0049     return of_platform_bus_probe(NULL, mpc85xx_common_ids, NULL);
0050 }
0051 #ifdef CONFIG_CPM2
0052 static void cpm2_cascade(struct irq_desc *desc)
0053 {
0054     struct irq_chip *chip = irq_desc_get_chip(desc);
0055     int cascade_irq;
0056
0057     while ((cascade_irq = cpm2_get_irq()) >= 0)
0058         generic_handle_irq(cascade_irq);
0059
0060     chip->irq_eoi(&desc->irq_data);
0061 }
0062
0063
0064 void __init mpc85xx_cpm2_pic_init(void)
0065 {
0066     struct device_node *np;
0067     int irq;
0068
0069     /* Setup CPM2 PIC */
0070     np = of_find_compatible_node(NULL, NULL, "fsl,cpm2-pic");
0071     if (np == NULL) {
0072         printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
0073         return;
0074     }
0075     irq = irq_of_parse_and_map(np, 0);
0076     if (!irq) {
0077         of_node_put(np);
0078         printk(KERN_ERR "PIC init: got no IRQ for cpm cascade\n");
0079         return;
0080     }
0081
0082     cpm2_pic_init(np);
0083     of_node_put(np);
0084     irq_set_chained_handler(irq, cpm2_cascade);
0085 }
0086 #endif
0087
0088 #ifdef CONFIG_QUICC_ENGINE
0089 void __init mpc85xx_qe_par_io_init(void)
0090 {
0091     struct device_node *np;
0092
0093     np = of_find_node_by_name(NULL, "par_io");
0094     if (np) {
0095         struct device_node *ucc;
0096
0097         par_io_init(np);
0098         of_node_put(np);
0099
0100         for_each_node_by_name(ucc, "ucc")
0101             par_io_of_config(ucc);
0102
0103     }
0104 }
0105 #endif