platforms/83xx/misc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * misc setup functions for MPC83xx
0004  *
0005  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
0006  */
0007
0008 #include <linux/stddef.h>
0009 #include <linux/kernel.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/pci.h>
0012
0013 #include <asm/debug.h>
0014 #include <asm/io.h>
0015 #include <asm/hw_irq.h>
0016 #include <asm/ipic.h>
0017 #include <sysdev/fsl_soc.h>
0018 #include <sysdev/fsl_pci.h>
0019
0020 #include <mm/mmu_decl.h>
0021
0022 #include "mpc83xx.h"
0023
0024 static __be32 __iomem *restart_reg_base;
0025
0026 static int __init mpc83xx_restart_init(void)
0027 {
0028     /* map reset restart_reg_baseister space */
0029     restart_reg_base = ioremap(get_immrbase() + 0x900, 0xff);
0030
0031     return 0;
0032 }
0033
0034 arch_initcall(mpc83xx_restart_init);
0035
0036 void __noreturn mpc83xx_restart(char *cmd)
0037 {
0038 #define RST_OFFSET  0x00000900
0039 #define RST_PROT_REG    0x00000018
0040 #define RST_CTRL_REG    0x0000001c
0041
0042     local_irq_disable();
0043
0044     if (restart_reg_base) {
0045         /* enable software reset "RSTE" */
0046         out_be32(restart_reg_base + (RST_PROT_REG >> 2), 0x52535445);
0047
0048         /* set software hard reset */
0049         out_be32(restart_reg_base + (RST_CTRL_REG >> 2), 0x2);
0050     } else {
0051         printk (KERN_EMERG "Error: Restart registers not mapped, spinning!\n");
0052     }
0053
0054     for (;;) ;
0055 }
0056
0057 long __init mpc83xx_time_init(void)
0058 {
0059 #define SPCR_OFFSET 0x00000110
0060 #define SPCR_TBEN   0x00400000
0061     __be32 __iomem *spcr = ioremap(get_immrbase() + SPCR_OFFSET, 4);
0062     __be32 tmp;
0063
0064     tmp = in_be32(spcr);
0065     out_be32(spcr, tmp | SPCR_TBEN);
0066
0067     iounmap(spcr);
0068
0069     return 0;
0070 }
0071
0072 void __init mpc83xx_ipic_init_IRQ(void)
0073 {
0074     struct device_node *np;
0075
0076     /* looking for fsl,pq2pro-pic which is asl compatible with fsl,ipic */
0077     np = of_find_compatible_node(NULL, NULL, "fsl,ipic");
0078     if (!np)
0079         np = of_find_node_by_type(NULL, "ipic");
0080     if (!np)
0081         return;
0082
0083     ipic_init(np, 0);
0084
0085     of_node_put(np);
0086
0087     /* Initialize the default interrupt mapping priorities,
0088      * in case the boot rom changed something on us.
0089      */
0090     ipic_set_default_priority();
0091 }
0092
0093 static const struct of_device_id of_bus_ids[] __initconst = {
0094     { .type = "soc", },
0095     { .compatible = "soc", },
0096     { .compatible = "simple-bus" },
0097     { .compatible = "gianfar" },
0098     { .compatible = "gpio-leds", },
0099     { .type = "qe", },
0100     { .compatible = "fsl,qe", },
0101     {},
0102 };
0103
0104 int __init mpc83xx_declare_of_platform_devices(void)
0105 {
0106     of_platform_bus_probe(NULL, of_bus_ids, NULL);
0107     return 0;
0108 }
0109
0110 #ifdef CONFIG_PCI
0111 void __init mpc83xx_setup_pci(void)
0112 {
0113     struct device_node *np;
0114
0115     for_each_compatible_node(np, "pci", "fsl,mpc8349-pci")
0116         mpc83xx_add_bridge(np);
0117     for_each_compatible_node(np, "pci", "fsl,mpc8314-pcie")
0118         mpc83xx_add_bridge(np);
0119 }
0120 #endif
0121
0122 void __init mpc83xx_setup_arch(void)
0123 {
0124     phys_addr_t immrbase = get_immrbase();
0125     int immrsize = IS_ALIGNED(immrbase, SZ_2M) ? SZ_2M : SZ_1M;
0126     unsigned long va = fix_to_virt(FIX_IMMR_BASE);
0127
0128     if (ppc_md.progress)
0129         ppc_md.progress("mpc83xx_setup_arch()", 0);
0130
0131     setbat(-1, va, immrbase, immrsize, PAGE_KERNEL_NCG);
0132     update_bats();
0133 }
0134
0135 int machine_check_83xx(struct pt_regs *regs)
0136 {
0137     u32 mask = 1 << (31 - IPIC_MCP_WDT);
0138
0139     if (!(regs->msr & SRR1_MCE_MCP) || !(ipic_get_mcp_status() & mask))
0140         return machine_check_generic(regs);
0141     ipic_clear_mcp_status(mask);
0142
0143     if (debugger_fault_handler(regs))
0144         return 1;
0145
0146     die("Watchdog NMI Reset", regs, 0);
0147
0148     return 1;
0149 }