platforms/83xx/km83xx.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright 2008-2011 DENX Software Engineering GmbH
0004  * Author: Heiko Schocher <hs@denx.de>
0005  *
0006  * Description:
0007  * Keymile 83xx platform specific routines.
0008  */
0009
0010 #include <linux/stddef.h>
0011 #include <linux/kernel.h>
0012 #include <linux/init.h>
0013 #include <linux/errno.h>
0014 #include <linux/reboot.h>
0015 #include <linux/pci.h>
0016 #include <linux/kdev_t.h>
0017 #include <linux/major.h>
0018 #include <linux/console.h>
0019 #include <linux/delay.h>
0020 #include <linux/seq_file.h>
0021 #include <linux/root_dev.h>
0022 #include <linux/initrd.h>
0023 #include <linux/of_platform.h>
0024 #include <linux/of_device.h>
0025
0026 #include <linux/atomic.h>
0027 #include <linux/time.h>
0028 #include <linux/io.h>
0029 #include <asm/machdep.h>
0030 #include <asm/ipic.h>
0031 #include <asm/irq.h>
0032 #include <asm/udbg.h>
0033 #include <sysdev/fsl_soc.h>
0034 #include <sysdev/fsl_pci.h>
0035 #include <soc/fsl/qe/qe.h>
0036
0037 #include "mpc83xx.h"
0038
0039 #define SVR_REV(svr)    (((svr) >>  0) & 0xFFFF) /* Revision field */
0040
0041 static void __init quirk_mpc8360e_qe_enet10(void)
0042 {
0043     /*
0044      * handle mpc8360E Erratum QE_ENET10:
0045      * RGMII AC values do not meet the specification
0046      */
0047     uint svid = mfspr(SPRN_SVR);
0048     struct  device_node *np_par;
0049     struct  resource res;
0050     void    __iomem *base;
0051     int ret;
0052
0053     np_par = of_find_node_by_name(NULL, "par_io");
0054     if (np_par == NULL) {
0055         pr_warn("%s couldn't find par_io node\n", __func__);
0056         return;
0057     }
0058     /* Map Parallel I/O ports registers */
0059     ret = of_address_to_resource(np_par, 0, &res);
0060     if (ret) {
0061         pr_warn("%s couldn't map par_io registers\n", __func__);
0062         goto out;
0063     }
0064
0065     base = ioremap(res.start, resource_size(&res));
0066     if (!base)
0067         goto out;
0068
0069     /*
0070      * set output delay adjustments to default values according
0071      * table 5 in Errata Rev. 5, 9/2011:
0072      *
0073      * write 0b01 to UCC1 bits 18:19
0074      * write 0b01 to UCC2 option 1 bits 4:5
0075      * write 0b01 to UCC2 option 2 bits 16:17
0076      */
0077     clrsetbits_be32((base + 0xa8), 0x0c00f000, 0x04005000);
0078
0079     /*
0080      * set output delay adjustments to default values according
0081      * table 3-13 in Reference Manual Rev.3 05/2010:
0082      *
0083      * write 0b01 to UCC2 option 2 bits 16:17
0084      * write 0b0101 to UCC1 bits 20:23
0085      * write 0b0101 to UCC2 option 1 bits 24:27
0086      */
0087     clrsetbits_be32((base + 0xac), 0x0000cff0, 0x00004550);
0088
0089     if (SVR_REV(svid) == 0x0021) {
0090         /*
0091          * UCC2 option 1: write 0b1010 to bits 24:27
0092          * at address IMMRBAR+0x14AC
0093          */
0094         clrsetbits_be32((base + 0xac), 0x000000f0, 0x000000a0);
0095     } else if (SVR_REV(svid) == 0x0020) {
0096         /*
0097          * UCC1: write 0b11 to bits 18:19
0098          * at address IMMRBAR+0x14A8
0099          */
0100         setbits32((base + 0xa8), 0x00003000);
0101
0102         /*
0103          * UCC2 option 1: write 0b11 to bits 4:5
0104          * at address IMMRBAR+0x14A8
0105          */
0106         setbits32((base + 0xa8), 0x0c000000);
0107
0108         /*
0109          * UCC2 option 2: write 0b11 to bits 16:17
0110          * at address IMMRBAR+0x14AC
0111          */
0112         setbits32((base + 0xac), 0x0000c000);
0113     }
0114     iounmap(base);
0115 out:
0116     of_node_put(np_par);
0117 }
0118
0119 /* ************************************************************************
0120  *
0121  * Setup the architecture
0122  *
0123  */
0124 static void __init mpc83xx_km_setup_arch(void)
0125 {
0126 #ifdef CONFIG_QUICC_ENGINE
0127     struct device_node *np;
0128 #endif
0129
0130     mpc83xx_setup_arch();
0131
0132 #ifdef CONFIG_QUICC_ENGINE
0133     np = of_find_node_by_name(NULL, "par_io");
0134     if (np != NULL) {
0135         par_io_init(np);
0136         of_node_put(np);
0137
0138         for_each_node_by_name(np, "spi")
0139             par_io_of_config(np);
0140
0141         for_each_node_by_name(np, "ucc")
0142             par_io_of_config(np);
0143
0144         /* Only apply this quirk when par_io is available */
0145         np = of_find_compatible_node(NULL, "network", "ucc_geth");
0146         if (np != NULL) {
0147             quirk_mpc8360e_qe_enet10();
0148             of_node_put(np);
0149         }
0150     }
0151 #endif  /* CONFIG_QUICC_ENGINE */
0152 }
0153
0154 machine_device_initcall(mpc83xx_km, mpc83xx_declare_of_platform_devices);
0155
0156 /* list of the supported boards */
0157 static char *board[] __initdata = {
0158     "Keymile,KMETER1",
0159     "Keymile,kmpbec8321",
0160     NULL
0161 };
0162
0163 /*
0164  * Called very early, MMU is off, device-tree isn't unflattened
0165  */
0166 static int __init mpc83xx_km_probe(void)
0167 {
0168     int i = 0;
0169
0170     while (board[i]) {
0171         if (of_machine_is_compatible(board[i]))
0172             break;
0173         i++;
0174     }
0175     return (board[i] != NULL);
0176 }
0177
0178 define_machine(mpc83xx_km) {
0179     .name       = "mpc83xx-km-platform",
0180     .probe      = mpc83xx_km_probe,
0181     .setup_arch = mpc83xx_km_setup_arch,
0182     .discover_phbs  = mpc83xx_setup_pci,
0183     .init_IRQ   = mpc83xx_ipic_init_IRQ,
0184     .get_irq    = ipic_get_irq,
0185     .restart    = mpc83xx_restart,
0186     .time_init  = mpc83xx_time_init,
0187     .calibrate_decr = generic_calibrate_decr,
0188     .progress   = udbg_progress,
0189 };