platforms/82xx/mpc8272_ads.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * MPC8272 ADS board support
0004  *
0005  * Copyright 2007 Freescale Semiconductor, Inc.
0006  * Author: Scott Wood <scottwood@freescale.com>
0007  *
0008  * Based on code by Vitaly Bordug <vbordug@ru.mvista.com>
0009  * Copyright (c) 2006 MontaVista Software, Inc.
0010  */
0011
0012 #include <linux/init.h>
0013 #include <linux/interrupt.h>
0014 #include <linux/fsl_devices.h>
0015 #include <linux/of_address.h>
0016 #include <linux/of_fdt.h>
0017 #include <linux/of_platform.h>
0018 #include <linux/io.h>
0019
0020 #include <asm/cpm2.h>
0021 #include <asm/udbg.h>
0022 #include <asm/machdep.h>
0023 #include <asm/time.h>
0024
0025 #include <platforms/82xx/pq2.h>
0026
0027 #include <sysdev/fsl_soc.h>
0028 #include <sysdev/cpm2_pic.h>
0029
0030 #include "pq2.h"
0031
0032 static void __init mpc8272_ads_pic_init(void)
0033 {
0034     struct device_node *np = of_find_compatible_node(NULL, NULL,
0035                                                      "fsl,cpm2-pic");
0036     if (!np) {
0037         printk(KERN_ERR "PIC init: can not find fsl,cpm2-pic node\n");
0038         return;
0039     }
0040
0041     cpm2_pic_init(np);
0042     of_node_put(np);
0043
0044     /* Initialize stuff for the 82xx CPLD IC and install demux  */
0045     pq2ads_pci_init_irq();
0046 }
0047
0048 struct cpm_pin {
0049     int port, pin, flags;
0050 };
0051
0052 static struct cpm_pin mpc8272_ads_pins[] = {
0053     /* SCC1 */
0054     {3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0055     {3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0056
0057     /* SCC4 */
0058     {3, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0059     {3, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0060
0061     /* FCC1 */
0062     {0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0063     {0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0064     {0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0065     {0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0066     {0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0067     {0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0068     {0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0069     {0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0070     {0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0071     {0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0072     {0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0073     {0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0074     {0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0075     {0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
0076     {2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0077     {2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0078
0079     /* FCC2 */
0080     {1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0081     {1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0082     {1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0083     {1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0084     {1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0085     {1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0086     {1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0087     {1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0088     {1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0089     {1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0090     {1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0091     {1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
0092     {1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0093     {1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0094     {2, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0095     {2, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0096
0097     /* I2C */
0098     {3, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
0099     {3, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_OPENDRAIN},
0100
0101     /* USB */
0102     {2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0103     {2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0104     {2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0105     {2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0106     {3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0107     {3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
0108     {3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
0109 };
0110
0111 static void __init init_ioports(void)
0112 {
0113     int i;
0114
0115     for (i = 0; i < ARRAY_SIZE(mpc8272_ads_pins); i++) {
0116         struct cpm_pin *pin = &mpc8272_ads_pins[i];
0117         cpm2_set_pin(pin->port, pin->pin, pin->flags);
0118     }
0119
0120     cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
0121     cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
0122     cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_RX);
0123     cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX);
0124     cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_RX);
0125     cpm2_clk_setup(CPM_CLK_SCC4, CPM_BRG4, CPM_CLK_TX);
0126     cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
0127     cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
0128     cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK15, CPM_CLK_RX);
0129     cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK16, CPM_CLK_TX);
0130 }
0131
0132 static void __init mpc8272_ads_setup_arch(void)
0133 {
0134     struct device_node *np;
0135     __be32 __iomem *bcsr;
0136
0137     if (ppc_md.progress)
0138         ppc_md.progress("mpc8272_ads_setup_arch()", 0);
0139
0140     cpm2_reset();
0141
0142     np = of_find_compatible_node(NULL, NULL, "fsl,mpc8272ads-bcsr");
0143     if (!np) {
0144         printk(KERN_ERR "No bcsr in device tree\n");
0145         return;
0146     }
0147
0148     bcsr = of_iomap(np, 0);
0149     of_node_put(np);
0150     if (!bcsr) {
0151         printk(KERN_ERR "Cannot map BCSR registers\n");
0152         return;
0153     }
0154
0155 #define BCSR1_FETHIEN       0x08000000
0156 #define BCSR1_FETH_RST      0x04000000
0157 #define BCSR1_RS232_EN1     0x02000000
0158 #define BCSR1_RS232_EN2     0x01000000
0159 #define BCSR3_USB_nEN       0x80000000
0160 #define BCSR3_FETHIEN2      0x10000000
0161 #define BCSR3_FETH2_RST     0x08000000
0162
0163     clrbits32(&bcsr[1], BCSR1_RS232_EN1 | BCSR1_RS232_EN2 | BCSR1_FETHIEN);
0164     setbits32(&bcsr[1], BCSR1_FETH_RST);
0165
0166     clrbits32(&bcsr[3], BCSR3_FETHIEN2);
0167     setbits32(&bcsr[3], BCSR3_FETH2_RST);
0168
0169     clrbits32(&bcsr[3], BCSR3_USB_nEN);
0170
0171     iounmap(bcsr);
0172
0173     init_ioports();
0174
0175     if (ppc_md.progress)
0176         ppc_md.progress("mpc8272_ads_setup_arch(), finish", 0);
0177 }
0178
0179 static const struct of_device_id of_bus_ids[] __initconst = {
0180     { .name = "soc", },
0181     { .name = "cpm", },
0182     { .name = "localbus", },
0183     {},
0184 };
0185
0186 static int __init declare_of_platform_devices(void)
0187 {
0188     /* Publish the QE devices */
0189     of_platform_bus_probe(NULL, of_bus_ids, NULL);
0190     return 0;
0191 }
0192 machine_device_initcall(mpc8272_ads, declare_of_platform_devices);
0193
0194 /*
0195  * Called very early, device-tree isn't unflattened
0196  */
0197 static int __init mpc8272_ads_probe(void)
0198 {
0199     return of_machine_is_compatible("fsl,mpc8272ads");
0200 }
0201
0202 define_machine(mpc8272_ads)
0203 {
0204     .name = "Freescale MPC8272 ADS",
0205     .probe = mpc8272_ads_probe,
0206     .setup_arch = mpc8272_ads_setup_arch,
0207     .discover_phbs = pq2_init_pci,
0208     .init_IRQ = mpc8272_ads_pic_init,
0209     .get_irq = cpm2_get_irq,
0210     .calibrate_decr = generic_calibrate_decr,
0211     .restart = pq2_restart,
0212     .progress = udbg_progress,
0213 };