platforms/52xx/mpc52xx_sleep.S

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #include <asm/reg.h>
0003 #include <asm/ppc_asm.h>
0004 #include <asm/processor.h>
0005
0006
0007 .text
0008
0009 _GLOBAL(mpc52xx_deep_sleep)
0010 mpc52xx_deep_sleep: /* args r3-r6: SRAM, SDRAM regs, CDM regs, INTR regs */
0011
0012     /* enable interrupts */
0013     mfmsr   r7
0014     ori r7, r7, 0x8000 /* EE */
0015     mtmsr   r7
0016     sync; isync;
0017
0018     li  r10, 0 /* flag that irq handler sets */
0019
0020     /* enable tmr7 (or any other) interrupt */
0021     lwz r8, 0x14(r6) /* intr->main_mask */
0022     ori r8, r8, 0x1
0023     xori    r8, r8, 0x1
0024     stw r8, 0x14(r6)
0025     sync
0026
0027     /* emulate tmr7 interrupt */
0028     li  r8, 0x1
0029     stw r8, 0x40(r6) /* intr->main_emulate */
0030     sync
0031
0032     /* wait for it to happen */
0033 1:
0034     cmpi    cr0, r10, 1
0035     bne cr0, 1b
0036
0037     /* lock icache */
0038     mfspr   r10, SPRN_HID0
0039     ori r10, r10, 0x2000
0040     sync; isync;
0041     mtspr   SPRN_HID0, r10
0042     sync; isync;
0043
0044
0045     mflr    r9 /* save LR */
0046
0047     /* jump to sram */
0048     mtlr    r3
0049     blrl
0050
0051     mtlr    r9 /* restore LR */
0052
0053     /* unlock icache */
0054     mfspr   r10, SPRN_HID0
0055     ori r10, r10, 0x2000
0056     xori    r10, r10, 0x2000
0057     sync; isync;
0058     mtspr   SPRN_HID0, r10
0059     sync; isync;
0060
0061
0062     /* return to C code */
0063     blr
0064
0065
0066 _GLOBAL(mpc52xx_ds_sram)
0067 mpc52xx_ds_sram:
0068     /* put SDRAM into self-refresh */
0069     lwz r8, 0x4(r4) /* sdram->ctrl */
0070
0071     oris    r8, r8, 0x8000 /* mode_en */
0072     stw r8, 0x4(r4)
0073     sync
0074
0075     ori r8, r8, 0x0002 /* soft_pre */
0076     stw r8, 0x4(r4)
0077     sync
0078     xori    r8, r8, 0x0002
0079
0080     xoris   r8, r8, 0x8000 /* !mode_en */
0081     stw r8, 0x4(r4)
0082     sync
0083
0084     oris    r8, r8, 0x5000
0085     xoris   r8, r8, 0x4000 /* ref_en !cke */
0086     stw r8, 0x4(r4)
0087     sync
0088
0089     /* disable SDRAM clock */
0090     lwz r8, 0x14(r5) /* cdm->clkenable */
0091     ori r8, r8, 0x0008
0092     xori    r8, r8, 0x0008
0093     stw r8, 0x14(r5)
0094     sync
0095
0096
0097     /* put mpc5200 to sleep */
0098     mfmsr   r10
0099     oris    r10, r10, 0x0004    /* POW = 1 */
0100     sync; isync;
0101     mtmsr   r10
0102     sync; isync;
0103
0104
0105     /* enable clock */
0106     lwz r8, 0x14(r5)
0107     ori r8, r8, 0x0008
0108     stw r8, 0x14(r5)
0109     sync
0110
0111     /* get ram out of self-refresh */
0112     lwz r8, 0x4(r4)
0113     oris    r8, r8, 0x5000 /* cke ref_en */
0114     stw r8, 0x4(r4)
0115     sync
0116
0117     blr
0118 _GLOBAL(mpc52xx_ds_sram_size)
0119 mpc52xx_ds_sram_size:
0120     .long $-mpc52xx_ds_sram
0121
0122
0123 /* ### interrupt handler for wakeup from deep-sleep ### */
0124 _GLOBAL(mpc52xx_ds_cached)
0125 mpc52xx_ds_cached:
0126     mtspr   SPRN_SPRG0, r7
0127     mtspr   SPRN_SPRG1, r8
0128
0129     /* disable emulated interrupt */
0130     mfspr   r7, 311 /* MBAR */
0131     addi    r7, r7, 0x540   /* intr->main_emul */
0132     li  r8, 0
0133     stw r8, 0(r7)
0134     sync
0135     dcbf    0, r7
0136
0137     /* acknowledge wakeup, so CCS releases power pown */
0138     mfspr   r7, 311 /* MBAR */
0139     addi    r7, r7, 0x524   /* intr->enc_status */
0140     lwz r8, 0(r7)
0141     ori r8, r8, 0x0400
0142     stw r8, 0(r7)
0143     sync
0144     dcbf    0, r7
0145
0146     /* flag - we handled the interrupt */
0147     li  r10, 1
0148
0149     mfspr   r8, SPRN_SPRG1
0150     mfspr   r7, SPRN_SPRG0
0151
0152     rfi
0153 _GLOBAL(mpc52xx_ds_cached_size)
0154 mpc52xx_ds_cached_size:
0155     .long $-mpc52xx_ds_cached