platforms/52xx/mpc52xx_pic.c

0001 /*
0002  *
0003  * Programmable Interrupt Controller functions for the Freescale MPC52xx.
0004  *
0005  * Copyright (C) 2008 Secret Lab Technologies Ltd.
0006  * Copyright (C) 2006 bplan GmbH
0007  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
0008  * Copyright (C) 2003 Montavista Software, Inc
0009  *
0010  * Based on the code from the 2.4 kernel by
0011  * Dale Farnsworth <dfarnsworth@mvista.com> and Kent Borg.
0012  *
0013  * This file is licensed under the terms of the GNU General Public License
0014  * version 2. This program is licensed "as is" without any warranty of any
0015  * kind, whether express or implied.
0016  *
0017  */
0018
0019 /*
0020  * This is the device driver for the MPC5200 interrupt controller.
0021  *
0022  * hardware overview
0023  * -----------------
0024  * The MPC5200 interrupt controller groups the all interrupt sources into
0025  * three groups called 'critical', 'main', and 'peripheral'.  The critical
0026  * group has 3 irqs, External IRQ0, slice timer 0 irq, and wake from deep
0027  * sleep.  Main group include the other 3 external IRQs, slice timer 1, RTC,
0028  * gpios, and the general purpose timers.  Peripheral group contains the
0029  * remaining irq sources from all of the on-chip peripherals (PSCs, Ethernet,
0030  * USB, DMA, etc).
0031  *
0032  * virqs
0033  * -----
0034  * The Linux IRQ subsystem requires that each irq source be assigned a
0035  * system wide unique IRQ number starting at 1 (0 means no irq).  Since
0036  * systems can have multiple interrupt controllers, the virtual IRQ (virq)
0037  * infrastructure lets each interrupt controller to define a local set
0038  * of IRQ numbers and the virq infrastructure maps those numbers into
0039  * a unique range of the global IRQ# space.
0040  *
0041  * To define a range of virq numbers for this controller, this driver first
0042  * assigns a number to each of the irq groups (called the level 1 or L1
0043  * value).  Within each group individual irq sources are also assigned a
0044  * number, as defined by the MPC5200 user guide, and refers to it as the
0045  * level 2 or L2 value.  The virq number is determined by shifting up the
0046  * L1 value by MPC52xx_IRQ_L1_OFFSET and ORing it with the L2 value.
0047  *
0048  * For example, the TMR0 interrupt is irq 9 in the main group.  The
0049  * virq for TMR0 is calculated by ((1 << MPC52xx_IRQ_L1_OFFSET) | 9).
0050  *
0051  * The observant reader will also notice that this driver defines a 4th
0052  * interrupt group called 'bestcomm'.  The bestcomm group isn't physically
0053  * part of the MPC5200 interrupt controller, but it is used here to assign
0054  * a separate virq number for each bestcomm task (since any of the 16
0055  * bestcomm tasks can cause the bestcomm interrupt to be raised).  When a
0056  * bestcomm interrupt occurs (peripheral group, irq 0) this driver determines
0057  * which task needs servicing and returns the irq number for that task.  This
0058  * allows drivers which use bestcomm to define their own interrupt handlers.
0059  *
0060  * irq_chip structures
0061  * -------------------
0062  * For actually manipulating IRQs (masking, enabling, clearing, etc) this
0063  * driver defines four separate 'irq_chip' structures, one for the main
0064  * group, one for the peripherals group, one for the bestcomm group and one
0065  * for external interrupts.  The irq_chip structures provide the hooks needed
0066  * to manipulate each IRQ source, and since each group is has a separate set
0067  * of registers for controlling the irq, it makes sense to divide up the
0068  * hooks along those lines.
0069  *
0070  * You'll notice that there is not an irq_chip for the critical group and
0071  * you'll also notice that there is an irq_chip defined for external
0072  * interrupts even though there is no external interrupt group.  The reason
0073  * for this is that the four external interrupts are all managed with the same
0074  * register even though one of the external IRQs is in the critical group and
0075  * the other three are in the main group.  For this reason it makes sense for
0076  * the 4 external irqs to be managed using a separate set of hooks.  The
0077  * reason there is no crit irq_chip is that of the 3 irqs in the critical
0078  * group, only external interrupt is actually support at this time by this
0079  * driver and since external interrupt is the only one used, it can just
0080  * be directed to make use of the external irq irq_chip.
0081  *
0082  * device tree bindings
0083  * --------------------
0084  * The device tree bindings for this controller reflect the two level
0085  * organization of irqs in the device.  #interrupt-cells = <3> where the
0086  * first cell is the group number [0..3], the second cell is the irq
0087  * number in the group, and the third cell is the sense type (level/edge).
0088  * For reference, the following is a list of the interrupt property values
0089  * associated with external interrupt sources on the MPC5200 (just because
0090  * it is non-obvious to determine what the interrupts property should be
0091  * when reading the mpc5200 manual and it is a frequently asked question).
0092  *
0093  * External interrupts:
0094  * <0 0 n>  external irq0, n is sense   (n=0: level high,
0095  * <1 1 n>  external irq1, n is sense    n=1: edge rising,
0096  * <1 2 n>  external irq2, n is sense    n=2: edge falling,
0097  * <1 3 n>  external irq3, n is sense    n=3: level low)
0098  */
0099 #undef DEBUG
0100
0101 #include <linux/interrupt.h>
0102 #include <linux/irq.h>
0103 #include <linux/of.h>
0104 #include <linux/of_address.h>
0105 #include <linux/of_irq.h>
0106 #include <asm/io.h>
0107 #include <asm/mpc52xx.h>
0108
0109 /* HW IRQ mapping */
0110 #define MPC52xx_IRQ_L1_CRIT (0)
0111 #define MPC52xx_IRQ_L1_MAIN (1)
0112 #define MPC52xx_IRQ_L1_PERP (2)
0113 #define MPC52xx_IRQ_L1_SDMA (3)
0114
0115 #define MPC52xx_IRQ_L1_OFFSET   (6)
0116 #define MPC52xx_IRQ_L1_MASK (0x00c0)
0117 #define MPC52xx_IRQ_L2_MASK (0x003f)
0118
0119 #define MPC52xx_IRQ_HIGHTESTHWIRQ (0xd0)
0120
0121
0122 /* MPC5200 device tree match tables */
0123 static const struct of_device_id mpc52xx_pic_ids[] __initconst = {
0124     { .compatible = "fsl,mpc5200-pic", },
0125     { .compatible = "mpc5200-pic", },
0126     {}
0127 };
0128 static const struct of_device_id mpc52xx_sdma_ids[] __initconst = {
0129     { .compatible = "fsl,mpc5200-bestcomm", },
0130     { .compatible = "mpc5200-bestcomm", },
0131     {}
0132 };
0133
0134 static struct mpc52xx_intr __iomem *intr;
0135 static struct mpc52xx_sdma __iomem *sdma;
0136 static struct irq_domain *mpc52xx_irqhost = NULL;
0137
0138 static unsigned char mpc52xx_map_senses[4] = {
0139     IRQ_TYPE_LEVEL_HIGH,
0140     IRQ_TYPE_EDGE_RISING,
0141     IRQ_TYPE_EDGE_FALLING,
0142     IRQ_TYPE_LEVEL_LOW,
0143 };
0144
0145 /* Utility functions */
0146 static inline void io_be_setbit(u32 __iomem *addr, int bitno)
0147 {
0148     out_be32(addr, in_be32(addr) | (1 << bitno));
0149 }
0150
0151 static inline void io_be_clrbit(u32 __iomem *addr, int bitno)
0152 {
0153     out_be32(addr, in_be32(addr) & ~(1 << bitno));
0154 }
0155
0156 /*
0157  * IRQ[0-3] interrupt irq_chip
0158  */
0159 static void mpc52xx_extirq_mask(struct irq_data *d)
0160 {
0161     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0162     io_be_clrbit(&intr->ctrl, 11 - l2irq);
0163 }
0164
0165 static void mpc52xx_extirq_unmask(struct irq_data *d)
0166 {
0167     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0168     io_be_setbit(&intr->ctrl, 11 - l2irq);
0169 }
0170
0171 static void mpc52xx_extirq_ack(struct irq_data *d)
0172 {
0173     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0174     io_be_setbit(&intr->ctrl, 27-l2irq);
0175 }
0176
0177 static int mpc52xx_extirq_set_type(struct irq_data *d, unsigned int flow_type)
0178 {
0179     u32 ctrl_reg, type;
0180     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0181     void *handler = handle_level_irq;
0182
0183     pr_debug("%s: irq=%x. l2=%d flow_type=%d\n", __func__,
0184         (int) irqd_to_hwirq(d), l2irq, flow_type);
0185
0186     switch (flow_type) {
0187     case IRQF_TRIGGER_HIGH: type = 0; break;
0188     case IRQF_TRIGGER_RISING: type = 1; handler = handle_edge_irq; break;
0189     case IRQF_TRIGGER_FALLING: type = 2; handler = handle_edge_irq; break;
0190     case IRQF_TRIGGER_LOW: type = 3; break;
0191     default:
0192         type = 0;
0193     }
0194
0195     ctrl_reg = in_be32(&intr->ctrl);
0196     ctrl_reg &= ~(0x3 << (22 - (l2irq * 2)));
0197     ctrl_reg |= (type << (22 - (l2irq * 2)));
0198     out_be32(&intr->ctrl, ctrl_reg);
0199
0200     irq_set_handler_locked(d, handler);
0201
0202     return 0;
0203 }
0204
0205 static struct irq_chip mpc52xx_extirq_irqchip = {
0206     .name = "MPC52xx External",
0207     .irq_mask = mpc52xx_extirq_mask,
0208     .irq_unmask = mpc52xx_extirq_unmask,
0209     .irq_ack = mpc52xx_extirq_ack,
0210     .irq_set_type = mpc52xx_extirq_set_type,
0211 };
0212
0213 /*
0214  * Main interrupt irq_chip
0215  */
0216 static int mpc52xx_null_set_type(struct irq_data *d, unsigned int flow_type)
0217 {
0218     return 0; /* Do nothing so that the sense mask will get updated */
0219 }
0220
0221 static void mpc52xx_main_mask(struct irq_data *d)
0222 {
0223     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0224     io_be_setbit(&intr->main_mask, 16 - l2irq);
0225 }
0226
0227 static void mpc52xx_main_unmask(struct irq_data *d)
0228 {
0229     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0230     io_be_clrbit(&intr->main_mask, 16 - l2irq);
0231 }
0232
0233 static struct irq_chip mpc52xx_main_irqchip = {
0234     .name = "MPC52xx Main",
0235     .irq_mask = mpc52xx_main_mask,
0236     .irq_mask_ack = mpc52xx_main_mask,
0237     .irq_unmask = mpc52xx_main_unmask,
0238     .irq_set_type = mpc52xx_null_set_type,
0239 };
0240
0241 /*
0242  * Peripherals interrupt irq_chip
0243  */
0244 static void mpc52xx_periph_mask(struct irq_data *d)
0245 {
0246     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0247     io_be_setbit(&intr->per_mask, 31 - l2irq);
0248 }
0249
0250 static void mpc52xx_periph_unmask(struct irq_data *d)
0251 {
0252     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0253     io_be_clrbit(&intr->per_mask, 31 - l2irq);
0254 }
0255
0256 static struct irq_chip mpc52xx_periph_irqchip = {
0257     .name = "MPC52xx Peripherals",
0258     .irq_mask = mpc52xx_periph_mask,
0259     .irq_mask_ack = mpc52xx_periph_mask,
0260     .irq_unmask = mpc52xx_periph_unmask,
0261     .irq_set_type = mpc52xx_null_set_type,
0262 };
0263
0264 /*
0265  * SDMA interrupt irq_chip
0266  */
0267 static void mpc52xx_sdma_mask(struct irq_data *d)
0268 {
0269     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0270     io_be_setbit(&sdma->IntMask, l2irq);
0271 }
0272
0273 static void mpc52xx_sdma_unmask(struct irq_data *d)
0274 {
0275     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0276     io_be_clrbit(&sdma->IntMask, l2irq);
0277 }
0278
0279 static void mpc52xx_sdma_ack(struct irq_data *d)
0280 {
0281     int l2irq = irqd_to_hwirq(d) & MPC52xx_IRQ_L2_MASK;
0282     out_be32(&sdma->IntPend, 1 << l2irq);
0283 }
0284
0285 static struct irq_chip mpc52xx_sdma_irqchip = {
0286     .name = "MPC52xx SDMA",
0287     .irq_mask = mpc52xx_sdma_mask,
0288     .irq_unmask = mpc52xx_sdma_unmask,
0289     .irq_ack = mpc52xx_sdma_ack,
0290     .irq_set_type = mpc52xx_null_set_type,
0291 };
0292
0293 /**
0294  * mpc52xx_is_extirq - Returns true if hwirq number is for an external IRQ
0295  */
0296 static int mpc52xx_is_extirq(int l1, int l2)
0297 {
0298     return ((l1 == 0) && (l2 == 0)) ||
0299            ((l1 == 1) && (l2 >= 1) && (l2 <= 3));
0300 }
0301
0302 /**
0303  * mpc52xx_irqhost_xlate - translate virq# from device tree interrupts property
0304  */
0305 static int mpc52xx_irqhost_xlate(struct irq_domain *h, struct device_node *ct,
0306                  const u32 *intspec, unsigned int intsize,
0307                  irq_hw_number_t *out_hwirq,
0308                  unsigned int *out_flags)
0309 {
0310     int intrvect_l1;
0311     int intrvect_l2;
0312     int intrvect_type;
0313     int intrvect_linux;
0314
0315     if (intsize != 3)
0316         return -1;
0317
0318     intrvect_l1 = (int)intspec[0];
0319     intrvect_l2 = (int)intspec[1];
0320     intrvect_type = (int)intspec[2] & 0x3;
0321
0322     intrvect_linux = (intrvect_l1 << MPC52xx_IRQ_L1_OFFSET) &
0323              MPC52xx_IRQ_L1_MASK;
0324     intrvect_linux |= intrvect_l2 & MPC52xx_IRQ_L2_MASK;
0325
0326     *out_hwirq = intrvect_linux;
0327     *out_flags = IRQ_TYPE_LEVEL_LOW;
0328     if (mpc52xx_is_extirq(intrvect_l1, intrvect_l2))
0329         *out_flags = mpc52xx_map_senses[intrvect_type];
0330
0331     pr_debug("return %x, l1=%d, l2=%d\n", intrvect_linux, intrvect_l1,
0332          intrvect_l2);
0333     return 0;
0334 }
0335
0336 /**
0337  * mpc52xx_irqhost_map - Hook to map from virq to an irq_chip structure
0338  */
0339 static int mpc52xx_irqhost_map(struct irq_domain *h, unsigned int virq,
0340                    irq_hw_number_t irq)
0341 {
0342     int l1irq;
0343     int l2irq;
0344     struct irq_chip *irqchip;
0345     void *hndlr;
0346     int type;
0347     u32 reg;
0348
0349     l1irq = (irq & MPC52xx_IRQ_L1_MASK) >> MPC52xx_IRQ_L1_OFFSET;
0350     l2irq = irq & MPC52xx_IRQ_L2_MASK;
0351
0352     /*
0353      * External IRQs are handled differently by the hardware so they are
0354      * handled by a dedicated irq_chip structure.
0355      */
0356     if (mpc52xx_is_extirq(l1irq, l2irq)) {
0357         reg = in_be32(&intr->ctrl);
0358         type = mpc52xx_map_senses[(reg >> (22 - l2irq * 2)) & 0x3];
0359         if ((type == IRQ_TYPE_EDGE_FALLING) ||
0360             (type == IRQ_TYPE_EDGE_RISING))
0361             hndlr = handle_edge_irq;
0362         else
0363             hndlr = handle_level_irq;
0364
0365         irq_set_chip_and_handler(virq, &mpc52xx_extirq_irqchip, hndlr);
0366         pr_debug("%s: External IRQ%i virq=%x, hw=%x. type=%x\n",
0367              __func__, l2irq, virq, (int)irq, type);
0368         return 0;
0369     }
0370
0371     /* It is an internal SOC irq.  Choose the correct irq_chip */
0372     switch (l1irq) {
0373     case MPC52xx_IRQ_L1_MAIN: irqchip = &mpc52xx_main_irqchip; break;
0374     case MPC52xx_IRQ_L1_PERP: irqchip = &mpc52xx_periph_irqchip; break;
0375     case MPC52xx_IRQ_L1_SDMA: irqchip = &mpc52xx_sdma_irqchip; break;
0376     case MPC52xx_IRQ_L1_CRIT:
0377         pr_warn("%s: Critical IRQ #%d is unsupported! Nopping it.\n",
0378             __func__, l2irq);
0379         irq_set_chip(virq, &no_irq_chip);
0380         return 0;
0381     }
0382
0383     irq_set_chip_and_handler(virq, irqchip, handle_level_irq);
0384     pr_debug("%s: virq=%x, l1=%i, l2=%i\n", __func__, virq, l1irq, l2irq);
0385
0386     return 0;
0387 }
0388
0389 static const struct irq_domain_ops mpc52xx_irqhost_ops = {
0390     .xlate = mpc52xx_irqhost_xlate,
0391     .map = mpc52xx_irqhost_map,
0392 };
0393
0394 /**
0395  * mpc52xx_init_irq - Initialize and register with the virq subsystem
0396  *
0397  * Hook for setting up IRQs on an mpc5200 system.  A pointer to this function
0398  * is to be put into the machine definition structure.
0399  *
0400  * This function searches the device tree for an MPC5200 interrupt controller,
0401  * initializes it, and registers it with the virq subsystem.
0402  */
0403 void __init mpc52xx_init_irq(void)
0404 {
0405     u32 intr_ctrl;
0406     struct device_node *picnode;
0407     struct device_node *np;
0408
0409     /* Remap the necessary zones */
0410     picnode = of_find_matching_node(NULL, mpc52xx_pic_ids);
0411     intr = of_iomap(picnode, 0);
0412     if (!intr)
0413         panic(__FILE__  ": find_and_map failed on 'mpc5200-pic'. "
0414                 "Check node !");
0415
0416     np = of_find_matching_node(NULL, mpc52xx_sdma_ids);
0417     sdma = of_iomap(np, 0);
0418     of_node_put(np);
0419     if (!sdma)
0420         panic(__FILE__  ": find_and_map failed on 'mpc5200-bestcomm'. "
0421                 "Check node !");
0422
0423     pr_debug("MPC5200 IRQ controller mapped to 0x%p\n", intr);
0424
0425     /* Disable all interrupt sources. */
0426     out_be32(&sdma->IntPend, 0xffffffff);   /* 1 means clear pending */
0427     out_be32(&sdma->IntMask, 0xffffffff);   /* 1 means disabled */
0428     out_be32(&intr->per_mask, 0x7ffffc00);  /* 1 means disabled */
0429     out_be32(&intr->main_mask, 0x00010fff); /* 1 means disabled */
0430     intr_ctrl = in_be32(&intr->ctrl);
0431     intr_ctrl &= 0x00ff0000;    /* Keeps IRQ[0-3] config */
0432     intr_ctrl |=    0x0f000000 |    /* clear IRQ 0-3 */
0433             0x00001000 |    /* MEE master external enable */
0434             0x00000000 |    /* 0 means disable IRQ 0-3 */
0435             0x00000001; /* CEb route critical normally */
0436     out_be32(&intr->ctrl, intr_ctrl);
0437
0438     /* Zero a bunch of the priority settings. */
0439     out_be32(&intr->per_pri1, 0);
0440     out_be32(&intr->per_pri2, 0);
0441     out_be32(&intr->per_pri3, 0);
0442     out_be32(&intr->main_pri1, 0);
0443     out_be32(&intr->main_pri2, 0);
0444
0445     /*
0446      * As last step, add an irq host to translate the real
0447      * hw irq information provided by the ofw to linux virq
0448      */
0449     mpc52xx_irqhost = irq_domain_add_linear(picnode,
0450                                      MPC52xx_IRQ_HIGHTESTHWIRQ,
0451                                      &mpc52xx_irqhost_ops, NULL);
0452
0453     if (!mpc52xx_irqhost)
0454         panic(__FILE__ ": Cannot allocate the IRQ host\n");
0455
0456     irq_set_default_host(mpc52xx_irqhost);
0457
0458     pr_info("MPC52xx PIC is up and running!\n");
0459 }
0460
0461 /**
0462  * mpc52xx_get_irq - Get pending interrupt number hook function
0463  *
0464  * Called by the interrupt handler to determine what IRQ handler needs to be
0465  * executed.
0466  *
0467  * Status of pending interrupts is determined by reading the encoded status
0468  * register.  The encoded status register has three fields; one for each of the
0469  * types of interrupts defined by the controller - 'critical', 'main' and
0470  * 'peripheral'.  This function reads the status register and returns the IRQ
0471  * number associated with the highest priority pending interrupt.  'Critical'
0472  * interrupts have the highest priority, followed by 'main' interrupts, and
0473  * then 'peripheral'.
0474  *
0475  * The mpc5200 interrupt controller can be configured to boost the priority
0476  * of individual 'peripheral' interrupts.  If this is the case then a special
0477  * value will appear in either the crit or main fields indicating a high
0478  * or medium priority peripheral irq has occurred.
0479  *
0480  * This function checks each of the 3 irq request fields and returns the
0481  * first pending interrupt that it finds.
0482  *
0483  * This function also identifies a 4th type of interrupt; 'bestcomm'.  Each
0484  * bestcomm DMA task can raise the bestcomm peripheral interrupt.  When this
0485  * occurs at task-specific IRQ# is decoded so that each task can have its
0486  * own IRQ handler.
0487  */
0488 unsigned int mpc52xx_get_irq(void)
0489 {
0490     u32 status;
0491     int irq;
0492
0493     status = in_be32(&intr->enc_status);
0494     if (status & 0x00000400) {  /* critical */
0495         irq = (status >> 8) & 0x3;
0496         if (irq == 2)   /* high priority peripheral */
0497             goto peripheral;
0498         irq |= (MPC52xx_IRQ_L1_CRIT << MPC52xx_IRQ_L1_OFFSET);
0499     } else if (status & 0x00200000) {   /* main */
0500         irq = (status >> 16) & 0x1f;
0501         if (irq == 4)   /* low priority peripheral */
0502             goto peripheral;
0503         irq |= (MPC52xx_IRQ_L1_MAIN << MPC52xx_IRQ_L1_OFFSET);
0504     } else if (status & 0x20000000) {   /* peripheral */
0505           peripheral:
0506         irq = (status >> 24) & 0x1f;
0507         if (irq == 0) { /* bestcomm */
0508             status = in_be32(&sdma->IntPend);
0509             irq = ffs(status) - 1;
0510             irq |= (MPC52xx_IRQ_L1_SDMA << MPC52xx_IRQ_L1_OFFSET);
0511         } else {
0512             irq |= (MPC52xx_IRQ_L1_PERP << MPC52xx_IRQ_L1_OFFSET);
0513         }
0514     } else {
0515         return 0;
0516     }
0517
0518     return irq_linear_revmap(mpc52xx_irqhost, irq);
0519 }