platforms/52xx/lite5200_pm.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 #include <linux/init.h>
0003 #include <linux/suspend.h>
0004 #include <linux/of_address.h>
0005
0006 #include <asm/io.h>
0007 #include <asm/time.h>
0008 #include <asm/mpc52xx.h>
0009 #include <asm/switch_to.h>
0010
0011 /* defined in lite5200_sleep.S and only used here */
0012 extern void lite5200_low_power(void __iomem *sram, void __iomem *mbar);
0013
0014 static struct mpc52xx_cdm __iomem *cdm;
0015 static struct mpc52xx_intr __iomem *pic;
0016 static struct mpc52xx_sdma __iomem *bes;
0017 static struct mpc52xx_xlb __iomem *xlb;
0018 static struct mpc52xx_gpio __iomem *gps;
0019 static struct mpc52xx_gpio_wkup __iomem *gpw;
0020 static void __iomem *pci;
0021 static void __iomem *sram;
0022 static const int sram_size = 0x4000;    /* 16 kBytes */
0023 static void __iomem *mbar;
0024
0025 static suspend_state_t lite5200_pm_target_state;
0026
0027 static int lite5200_pm_valid(suspend_state_t state)
0028 {
0029     switch (state) {
0030     case PM_SUSPEND_STANDBY:
0031     case PM_SUSPEND_MEM:
0032         return 1;
0033     default:
0034         return 0;
0035     }
0036 }
0037
0038 static int lite5200_pm_begin(suspend_state_t state)
0039 {
0040     if (lite5200_pm_valid(state)) {
0041         lite5200_pm_target_state = state;
0042         return 0;
0043     }
0044     return -EINVAL;
0045 }
0046
0047 static int lite5200_pm_prepare(void)
0048 {
0049     struct device_node *np;
0050     const struct of_device_id immr_ids[] = {
0051         { .compatible = "fsl,mpc5200-immr", },
0052         { .compatible = "fsl,mpc5200b-immr", },
0053         { .type = "soc", .compatible = "mpc5200", }, /* lite5200 */
0054         { .type = "builtin", .compatible = "mpc5200", }, /* efika */
0055         {}
0056     };
0057     u64 regaddr64 = 0;
0058     const u32 *regaddr_p;
0059
0060     /* deep sleep? let mpc52xx code handle that */
0061     if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
0062         return mpc52xx_pm_prepare();
0063
0064     if (lite5200_pm_target_state != PM_SUSPEND_MEM)
0065         return -EINVAL;
0066
0067     /* map registers */
0068     np = of_find_matching_node(NULL, immr_ids);
0069     regaddr_p = of_get_address(np, 0, NULL, NULL);
0070     if (regaddr_p)
0071         regaddr64 = of_translate_address(np, regaddr_p);
0072     of_node_put(np);
0073
0074     mbar = ioremap((u32) regaddr64, 0xC000);
0075     if (!mbar) {
0076         printk(KERN_ERR "%s:%i Error mapping registers\n", __func__, __LINE__);
0077         return -ENOSYS;
0078     }
0079
0080     cdm = mbar + 0x200;
0081     pic = mbar + 0x500;
0082     gps = mbar + 0xb00;
0083     gpw = mbar + 0xc00;
0084     pci = mbar + 0xd00;
0085     bes = mbar + 0x1200;
0086     xlb = mbar + 0x1f00;
0087     sram = mbar + 0x8000;
0088
0089     return 0;
0090 }
0091
0092 /* save and restore registers not bound to any real devices */
0093 static struct mpc52xx_cdm scdm;
0094 static struct mpc52xx_intr spic;
0095 static struct mpc52xx_sdma sbes;
0096 static struct mpc52xx_xlb sxlb;
0097 static struct mpc52xx_gpio sgps;
0098 static struct mpc52xx_gpio_wkup sgpw;
0099 static char spci[0x200];
0100
0101 static void lite5200_save_regs(void)
0102 {
0103     _memcpy_fromio(&spic, pic, sizeof(*pic));
0104     _memcpy_fromio(&sbes, bes, sizeof(*bes));
0105     _memcpy_fromio(&scdm, cdm, sizeof(*cdm));
0106     _memcpy_fromio(&sxlb, xlb, sizeof(*xlb));
0107     _memcpy_fromio(&sgps, gps, sizeof(*gps));
0108     _memcpy_fromio(&sgpw, gpw, sizeof(*gpw));
0109     _memcpy_fromio(spci, pci, 0x200);
0110
0111     _memcpy_fromio(saved_sram, sram, sram_size);
0112 }
0113
0114 static void lite5200_restore_regs(void)
0115 {
0116     int i;
0117     _memcpy_toio(sram, saved_sram, sram_size);
0118
0119     /* PCI Configuration */
0120     _memcpy_toio(pci, spci, 0x200);
0121
0122     /*
0123      * GPIOs. Interrupt Master Enable has higher address then other
0124      * registers, so just memcpy is ok.
0125      */
0126     _memcpy_toio(gpw, &sgpw, sizeof(*gpw));
0127     _memcpy_toio(gps, &sgps, sizeof(*gps));
0128
0129
0130     /* XLB Arbitrer */
0131     out_be32(&xlb->snoop_window, sxlb.snoop_window);
0132     out_be32(&xlb->master_priority, sxlb.master_priority);
0133     out_be32(&xlb->master_pri_enable, sxlb.master_pri_enable);
0134
0135     /* enable */
0136     out_be32(&xlb->int_enable, sxlb.int_enable);
0137     out_be32(&xlb->config, sxlb.config);
0138
0139
0140     /* CDM - Clock Distribution Module */
0141     out_8(&cdm->ipb_clk_sel, scdm.ipb_clk_sel);
0142     out_8(&cdm->pci_clk_sel, scdm.pci_clk_sel);
0143
0144     out_8(&cdm->ext_48mhz_en, scdm.ext_48mhz_en);
0145     out_8(&cdm->fd_enable, scdm.fd_enable);
0146     out_be16(&cdm->fd_counters, scdm.fd_counters);
0147
0148     out_be32(&cdm->clk_enables, scdm.clk_enables);
0149
0150     out_8(&cdm->osc_disable, scdm.osc_disable);
0151
0152     out_be16(&cdm->mclken_div_psc1, scdm.mclken_div_psc1);
0153     out_be16(&cdm->mclken_div_psc2, scdm.mclken_div_psc2);
0154     out_be16(&cdm->mclken_div_psc3, scdm.mclken_div_psc3);
0155     out_be16(&cdm->mclken_div_psc6, scdm.mclken_div_psc6);
0156
0157
0158     /* BESTCOMM */
0159     out_be32(&bes->taskBar, sbes.taskBar);
0160     out_be32(&bes->currentPointer, sbes.currentPointer);
0161     out_be32(&bes->endPointer, sbes.endPointer);
0162     out_be32(&bes->variablePointer, sbes.variablePointer);
0163
0164     out_8(&bes->IntVect1, sbes.IntVect1);
0165     out_8(&bes->IntVect2, sbes.IntVect2);
0166     out_be16(&bes->PtdCntrl, sbes.PtdCntrl);
0167
0168     for (i=0; i<32; i++)
0169         out_8(&bes->ipr[i], sbes.ipr[i]);
0170
0171     out_be32(&bes->cReqSelect, sbes.cReqSelect);
0172     out_be32(&bes->task_size0, sbes.task_size0);
0173     out_be32(&bes->task_size1, sbes.task_size1);
0174     out_be32(&bes->MDEDebug, sbes.MDEDebug);
0175     out_be32(&bes->ADSDebug, sbes.ADSDebug);
0176     out_be32(&bes->Value1, sbes.Value1);
0177     out_be32(&bes->Value2, sbes.Value2);
0178     out_be32(&bes->Control, sbes.Control);
0179     out_be32(&bes->Status, sbes.Status);
0180     out_be32(&bes->PTDDebug, sbes.PTDDebug);
0181
0182     /* restore tasks */
0183     for (i=0; i<16; i++)
0184         out_be16(&bes->tcr[i], sbes.tcr[i]);
0185
0186     /* enable interrupts */
0187     out_be32(&bes->IntPend, sbes.IntPend);
0188     out_be32(&bes->IntMask, sbes.IntMask);
0189
0190
0191     /* PIC */
0192     out_be32(&pic->per_pri1, spic.per_pri1);
0193     out_be32(&pic->per_pri2, spic.per_pri2);
0194     out_be32(&pic->per_pri3, spic.per_pri3);
0195
0196     out_be32(&pic->main_pri1, spic.main_pri1);
0197     out_be32(&pic->main_pri2, spic.main_pri2);
0198
0199     out_be32(&pic->enc_status, spic.enc_status);
0200
0201     /* unmask and enable interrupts */
0202     out_be32(&pic->per_mask, spic.per_mask);
0203     out_be32(&pic->main_mask, spic.main_mask);
0204     out_be32(&pic->ctrl, spic.ctrl);
0205 }
0206
0207 static int lite5200_pm_enter(suspend_state_t state)
0208 {
0209     /* deep sleep? let mpc52xx code handle that */
0210     if (state == PM_SUSPEND_STANDBY) {
0211         return mpc52xx_pm_enter(state);
0212     }
0213
0214     lite5200_save_regs();
0215
0216     /* effectively save FP regs */
0217     enable_kernel_fp();
0218
0219     lite5200_low_power(sram, mbar);
0220
0221     lite5200_restore_regs();
0222
0223     iounmap(mbar);
0224     return 0;
0225 }
0226
0227 static void lite5200_pm_finish(void)
0228 {
0229     /* deep sleep? let mpc52xx code handle that */
0230     if (lite5200_pm_target_state == PM_SUSPEND_STANDBY)
0231         mpc52xx_pm_finish();
0232 }
0233
0234 static void lite5200_pm_end(void)
0235 {
0236     lite5200_pm_target_state = PM_SUSPEND_ON;
0237 }
0238
0239 static const struct platform_suspend_ops lite5200_pm_ops = {
0240     .valid      = lite5200_pm_valid,
0241     .begin      = lite5200_pm_begin,
0242     .prepare    = lite5200_pm_prepare,
0243     .enter      = lite5200_pm_enter,
0244     .finish     = lite5200_pm_finish,
0245     .end        = lite5200_pm_end,
0246 };
0247
0248 int __init lite5200_pm_init(void)
0249 {
0250     suspend_set_ops(&lite5200_pm_ops);
0251     return 0;
0252 }