platforms/4xx/pci.c

0001 /*
0002  * PCI / PCI-X / PCI-Express support for 4xx parts
0003  *
0004  * Copyright 2007 Ben. Herrenschmidt <benh@kernel.crashing.org>, IBM Corp.
0005  *
0006  * Most PCI Express code is coming from Stefan Roese implementation for
0007  * arch/ppc in the Denx tree, slightly reworked by me.
0008  *
0009  * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
0010  *
0011  * Some of that comes itself from a previous implementation for 440SPE only
0012  * by Roland Dreier:
0013  *
0014  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
0015  * Roland Dreier <rolandd@cisco.com>
0016  *
0017  */
0018
0019 #undef DEBUG
0020
0021 #include <linux/kernel.h>
0022 #include <linux/pci.h>
0023 #include <linux/init.h>
0024 #include <linux/of.h>
0025 #include <linux/of_address.h>
0026 #include <linux/delay.h>
0027 #include <linux/slab.h>
0028
0029 #include <asm/io.h>
0030 #include <asm/pci-bridge.h>
0031 #include <asm/machdep.h>
0032 #include <asm/dcr.h>
0033 #include <asm/dcr-regs.h>
0034 #include <mm/mmu_decl.h>
0035
0036 #include "pci.h"
0037
0038 static int dma_offset_set;
0039
0040 #define U64_TO_U32_LOW(val) ((u32)((val) & 0x00000000ffffffffULL))
0041 #define U64_TO_U32_HIGH(val)    ((u32)((val) >> 32))
0042
0043 #define RES_TO_U32_LOW(val) \
0044     ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_LOW(val) : (val))
0045 #define RES_TO_U32_HIGH(val)    \
0046     ((sizeof(resource_size_t) > sizeof(u32)) ? U64_TO_U32_HIGH(val) : (0))
0047
0048 static inline int ppc440spe_revA(void)
0049 {
0050     /* Catch both 440SPe variants, with and without RAID6 support */
0051         if ((mfspr(SPRN_PVR) & 0xffefffff) == 0x53421890)
0052                 return 1;
0053         else
0054                 return 0;
0055 }
0056
0057 static void fixup_ppc4xx_pci_bridge(struct pci_dev *dev)
0058 {
0059     struct pci_controller *hose;
0060     int i;
0061
0062     if (dev->devfn != 0 || dev->bus->self != NULL)
0063         return;
0064
0065     hose = pci_bus_to_host(dev->bus);
0066     if (hose == NULL)
0067         return;
0068
0069     if (!of_device_is_compatible(hose->dn, "ibm,plb-pciex") &&
0070         !of_device_is_compatible(hose->dn, "ibm,plb-pcix") &&
0071         !of_device_is_compatible(hose->dn, "ibm,plb-pci"))
0072         return;
0073
0074     if (of_device_is_compatible(hose->dn, "ibm,plb440epx-pci") ||
0075         of_device_is_compatible(hose->dn, "ibm,plb440grx-pci")) {
0076         hose->indirect_type |= PPC_INDIRECT_TYPE_BROKEN_MRM;
0077     }
0078
0079     /* Hide the PCI host BARs from the kernel as their content doesn't
0080      * fit well in the resource management
0081      */
0082     for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
0083         dev->resource[i].start = dev->resource[i].end = 0;
0084         dev->resource[i].flags = 0;
0085     }
0086
0087     printk(KERN_INFO "PCI: Hiding 4xx host bridge resources %s\n",
0088            pci_name(dev));
0089 }
0090 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, fixup_ppc4xx_pci_bridge);
0091
0092 static int __init ppc4xx_parse_dma_ranges(struct pci_controller *hose,
0093                       void __iomem *reg,
0094                       struct resource *res)
0095 {
0096     u64 size;
0097     const u32 *ranges;
0098     int rlen;
0099     int pna = of_n_addr_cells(hose->dn);
0100     int np = pna + 5;
0101
0102     /* Default */
0103     res->start = 0;
0104     size = 0x80000000;
0105     res->end = size - 1;
0106     res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
0107
0108     /* Get dma-ranges property */
0109     ranges = of_get_property(hose->dn, "dma-ranges", &rlen);
0110     if (ranges == NULL)
0111         goto out;
0112
0113     /* Walk it */
0114     while ((rlen -= np * 4) >= 0) {
0115         u32 pci_space = ranges[0];
0116         u64 pci_addr = of_read_number(ranges + 1, 2);
0117         u64 cpu_addr = of_translate_dma_address(hose->dn, ranges + 3);
0118         size = of_read_number(ranges + pna + 3, 2);
0119         ranges += np;
0120         if (cpu_addr == OF_BAD_ADDR || size == 0)
0121             continue;
0122
0123         /* We only care about memory */
0124         if ((pci_space & 0x03000000) != 0x02000000)
0125             continue;
0126
0127         /* We currently only support memory at 0, and pci_addr
0128          * within 32 bits space
0129          */
0130         if (cpu_addr != 0 || pci_addr > 0xffffffff) {
0131             printk(KERN_WARNING "%pOF: Ignored unsupported dma range"
0132                    " 0x%016llx...0x%016llx -> 0x%016llx\n",
0133                    hose->dn,
0134                    pci_addr, pci_addr + size - 1, cpu_addr);
0135             continue;
0136         }
0137
0138         /* Check if not prefetchable */
0139         if (!(pci_space & 0x40000000))
0140             res->flags &= ~IORESOURCE_PREFETCH;
0141
0142
0143         /* Use that */
0144         res->start = pci_addr;
0145         /* Beware of 32 bits resources */
0146         if (sizeof(resource_size_t) == sizeof(u32) &&
0147             (pci_addr + size) > 0x100000000ull)
0148             res->end = 0xffffffff;
0149         else
0150             res->end = res->start + size - 1;
0151         break;
0152     }
0153
0154     /* We only support one global DMA offset */
0155     if (dma_offset_set && pci_dram_offset != res->start) {
0156         printk(KERN_ERR "%pOF: dma-ranges(s) mismatch\n", hose->dn);
0157         return -ENXIO;
0158     }
0159
0160     /* Check that we can fit all of memory as we don't support
0161      * DMA bounce buffers
0162      */
0163     if (size < total_memory) {
0164         printk(KERN_ERR "%pOF: dma-ranges too small "
0165                "(size=%llx total_memory=%llx)\n",
0166                hose->dn, size, (u64)total_memory);
0167         return -ENXIO;
0168     }
0169
0170     /* Check we are a power of 2 size and that base is a multiple of size*/
0171     if ((size & (size - 1)) != 0  ||
0172         (res->start & (size - 1)) != 0) {
0173         printk(KERN_ERR "%pOF: dma-ranges unaligned\n", hose->dn);
0174         return -ENXIO;
0175     }
0176
0177     /* Check that we are fully contained within 32 bits space if we are not
0178      * running on a 460sx or 476fpe which have 64 bit bus addresses.
0179      */
0180     if (res->end > 0xffffffff &&
0181         !(of_device_is_compatible(hose->dn, "ibm,plb-pciex-460sx")
0182           || of_device_is_compatible(hose->dn, "ibm,plb-pciex-476fpe"))) {
0183         printk(KERN_ERR "%pOF: dma-ranges outside of 32 bits space\n",
0184                hose->dn);
0185         return -ENXIO;
0186     }
0187  out:
0188     dma_offset_set = 1;
0189     pci_dram_offset = res->start;
0190     hose->dma_window_base_cur = res->start;
0191     hose->dma_window_size = resource_size(res);
0192
0193     printk(KERN_INFO "4xx PCI DMA offset set to 0x%08lx\n",
0194            pci_dram_offset);
0195     printk(KERN_INFO "4xx PCI DMA window base to 0x%016llx\n",
0196            (unsigned long long)hose->dma_window_base_cur);
0197     printk(KERN_INFO "DMA window size 0x%016llx\n",
0198            (unsigned long long)hose->dma_window_size);
0199     return 0;
0200 }
0201
0202 /*
0203  * 4xx PCI 2.x part
0204  */
0205
0206 static int __init ppc4xx_setup_one_pci_PMM(struct pci_controller    *hose,
0207                        void __iomem         *reg,
0208                        u64              plb_addr,
0209                        u64              pci_addr,
0210                        u64              size,
0211                        unsigned int         flags,
0212                        int              index)
0213 {
0214     u32 ma, pcila, pciha;
0215
0216     /* Hack warning ! The "old" PCI 2.x cell only let us configure the low
0217      * 32-bit of incoming PLB addresses. The top 4 bits of the 36-bit
0218      * address are actually hard wired to a value that appears to depend
0219      * on the specific SoC. For example, it's 0 on 440EP and 1 on 440EPx.
0220      *
0221      * The trick here is we just crop those top bits and ignore them when
0222      * programming the chip. That means the device-tree has to be right
0223      * for the specific part used (we don't print a warning if it's wrong
0224      * but on the other hand, you'll crash quickly enough), but at least
0225      * this code should work whatever the hard coded value is
0226      */
0227     plb_addr &= 0xffffffffull;
0228
0229     /* Note: Due to the above hack, the test below doesn't actually test
0230      * if you address is above 4G, but it tests that address and
0231      * (address + size) are both contained in the same 4G
0232      */
0233     if ((plb_addr + size) > 0xffffffffull || !is_power_of_2(size) ||
0234         size < 0x1000 || (plb_addr & (size - 1)) != 0) {
0235         printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn);
0236         return -1;
0237     }
0238     ma = (0xffffffffu << ilog2(size)) | 1;
0239     if (flags & IORESOURCE_PREFETCH)
0240         ma |= 2;
0241
0242     pciha = RES_TO_U32_HIGH(pci_addr);
0243     pcila = RES_TO_U32_LOW(pci_addr);
0244
0245     writel(plb_addr, reg + PCIL0_PMM0LA + (0x10 * index));
0246     writel(pcila, reg + PCIL0_PMM0PCILA + (0x10 * index));
0247     writel(pciha, reg + PCIL0_PMM0PCIHA + (0x10 * index));
0248     writel(ma, reg + PCIL0_PMM0MA + (0x10 * index));
0249
0250     return 0;
0251 }
0252
0253 static void __init ppc4xx_configure_pci_PMMs(struct pci_controller *hose,
0254                          void __iomem *reg)
0255 {
0256     int i, j, found_isa_hole = 0;
0257
0258     /* Setup outbound memory windows */
0259     for (i = j = 0; i < 3; i++) {
0260         struct resource *res = &hose->mem_resources[i];
0261         resource_size_t offset = hose->mem_offset[i];
0262
0263         /* we only care about memory windows */
0264         if (!(res->flags & IORESOURCE_MEM))
0265             continue;
0266         if (j > 2) {
0267             printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn);
0268             break;
0269         }
0270
0271         /* Configure the resource */
0272         if (ppc4xx_setup_one_pci_PMM(hose, reg,
0273                          res->start,
0274                          res->start - offset,
0275                          resource_size(res),
0276                          res->flags,
0277                          j) == 0) {
0278             j++;
0279
0280             /* If the resource PCI address is 0 then we have our
0281              * ISA memory hole
0282              */
0283             if (res->start == offset)
0284                 found_isa_hole = 1;
0285         }
0286     }
0287
0288     /* Handle ISA memory hole if not already covered */
0289     if (j <= 2 && !found_isa_hole && hose->isa_mem_size)
0290         if (ppc4xx_setup_one_pci_PMM(hose, reg, hose->isa_mem_phys, 0,
0291                          hose->isa_mem_size, 0, j) == 0)
0292             printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n",
0293                    hose->dn);
0294 }
0295
0296 static void __init ppc4xx_configure_pci_PTMs(struct pci_controller *hose,
0297                          void __iomem *reg,
0298                          const struct resource *res)
0299 {
0300     resource_size_t size = resource_size(res);
0301     u32 sa;
0302
0303     /* Calculate window size */
0304     sa = (0xffffffffu << ilog2(size)) | 1;
0305     sa |= 0x1;
0306
0307     /* RAM is always at 0 local for now */
0308     writel(0, reg + PCIL0_PTM1LA);
0309     writel(sa, reg + PCIL0_PTM1MS);
0310
0311     /* Map on PCI side */
0312     early_write_config_dword(hose, hose->first_busno, 0,
0313                  PCI_BASE_ADDRESS_1, res->start);
0314     early_write_config_dword(hose, hose->first_busno, 0,
0315                  PCI_BASE_ADDRESS_2, 0x00000000);
0316     early_write_config_word(hose, hose->first_busno, 0,
0317                 PCI_COMMAND, 0x0006);
0318 }
0319
0320 static void __init ppc4xx_probe_pci_bridge(struct device_node *np)
0321 {
0322     /* NYI */
0323     struct resource rsrc_cfg;
0324     struct resource rsrc_reg;
0325     struct resource dma_window;
0326     struct pci_controller *hose = NULL;
0327     void __iomem *reg = NULL;
0328     const int *bus_range;
0329     int primary = 0;
0330
0331     /* Check if device is enabled */
0332     if (!of_device_is_available(np)) {
0333         printk(KERN_INFO "%pOF: Port disabled via device-tree\n", np);
0334         return;
0335     }
0336
0337     /* Fetch config space registers address */
0338     if (of_address_to_resource(np, 0, &rsrc_cfg)) {
0339         printk(KERN_ERR "%pOF: Can't get PCI config register base !",
0340                np);
0341         return;
0342     }
0343     /* Fetch host bridge internal registers address */
0344     if (of_address_to_resource(np, 3, &rsrc_reg)) {
0345         printk(KERN_ERR "%pOF: Can't get PCI internal register base !",
0346                np);
0347         return;
0348     }
0349
0350     /* Check if primary bridge */
0351     if (of_get_property(np, "primary", NULL))
0352         primary = 1;
0353
0354     /* Get bus range if any */
0355     bus_range = of_get_property(np, "bus-range", NULL);
0356
0357     /* Map registers */
0358     reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
0359     if (reg == NULL) {
0360         printk(KERN_ERR "%pOF: Can't map registers !", np);
0361         goto fail;
0362     }
0363
0364     /* Allocate the host controller data structure */
0365     hose = pcibios_alloc_controller(np);
0366     if (!hose)
0367         goto fail;
0368
0369     hose->first_busno = bus_range ? bus_range[0] : 0x0;
0370     hose->last_busno = bus_range ? bus_range[1] : 0xff;
0371
0372     /* Setup config space */
0373     setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4, 0);
0374
0375     /* Disable all windows */
0376     writel(0, reg + PCIL0_PMM0MA);
0377     writel(0, reg + PCIL0_PMM1MA);
0378     writel(0, reg + PCIL0_PMM2MA);
0379     writel(0, reg + PCIL0_PTM1MS);
0380     writel(0, reg + PCIL0_PTM2MS);
0381
0382     /* Parse outbound mapping resources */
0383     pci_process_bridge_OF_ranges(hose, np, primary);
0384
0385     /* Parse inbound mapping resources */
0386     if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
0387         goto fail;
0388
0389     /* Configure outbound ranges POMs */
0390     ppc4xx_configure_pci_PMMs(hose, reg);
0391
0392     /* Configure inbound ranges PIMs */
0393     ppc4xx_configure_pci_PTMs(hose, reg, &dma_window);
0394
0395     /* We don't need the registers anymore */
0396     iounmap(reg);
0397     return;
0398
0399  fail:
0400     if (hose)
0401         pcibios_free_controller(hose);
0402     if (reg)
0403         iounmap(reg);
0404 }
0405
0406 /*
0407  * 4xx PCI-X part
0408  */
0409
0410 static int __init ppc4xx_setup_one_pcix_POM(struct pci_controller   *hose,
0411                         void __iomem        *reg,
0412                         u64             plb_addr,
0413                         u64             pci_addr,
0414                         u64             size,
0415                         unsigned int        flags,
0416                         int             index)
0417 {
0418     u32 lah, lal, pciah, pcial, sa;
0419
0420     if (!is_power_of_2(size) || size < 0x1000 ||
0421         (plb_addr & (size - 1)) != 0) {
0422         printk(KERN_WARNING "%pOF: Resource out of range\n",
0423                hose->dn);
0424         return -1;
0425     }
0426
0427     /* Calculate register values */
0428     lah = RES_TO_U32_HIGH(plb_addr);
0429     lal = RES_TO_U32_LOW(plb_addr);
0430     pciah = RES_TO_U32_HIGH(pci_addr);
0431     pcial = RES_TO_U32_LOW(pci_addr);
0432     sa = (0xffffffffu << ilog2(size)) | 0x1;
0433
0434     /* Program register values */
0435     if (index == 0) {
0436         writel(lah, reg + PCIX0_POM0LAH);
0437         writel(lal, reg + PCIX0_POM0LAL);
0438         writel(pciah, reg + PCIX0_POM0PCIAH);
0439         writel(pcial, reg + PCIX0_POM0PCIAL);
0440         writel(sa, reg + PCIX0_POM0SA);
0441     } else {
0442         writel(lah, reg + PCIX0_POM1LAH);
0443         writel(lal, reg + PCIX0_POM1LAL);
0444         writel(pciah, reg + PCIX0_POM1PCIAH);
0445         writel(pcial, reg + PCIX0_POM1PCIAL);
0446         writel(sa, reg + PCIX0_POM1SA);
0447     }
0448
0449     return 0;
0450 }
0451
0452 static void __init ppc4xx_configure_pcix_POMs(struct pci_controller *hose,
0453                           void __iomem *reg)
0454 {
0455     int i, j, found_isa_hole = 0;
0456
0457     /* Setup outbound memory windows */
0458     for (i = j = 0; i < 3; i++) {
0459         struct resource *res = &hose->mem_resources[i];
0460         resource_size_t offset = hose->mem_offset[i];
0461
0462         /* we only care about memory windows */
0463         if (!(res->flags & IORESOURCE_MEM))
0464             continue;
0465         if (j > 1) {
0466             printk(KERN_WARNING "%pOF: Too many ranges\n", hose->dn);
0467             break;
0468         }
0469
0470         /* Configure the resource */
0471         if (ppc4xx_setup_one_pcix_POM(hose, reg,
0472                           res->start,
0473                           res->start - offset,
0474                           resource_size(res),
0475                           res->flags,
0476                           j) == 0) {
0477             j++;
0478
0479             /* If the resource PCI address is 0 then we have our
0480              * ISA memory hole
0481              */
0482             if (res->start == offset)
0483                 found_isa_hole = 1;
0484         }
0485     }
0486
0487     /* Handle ISA memory hole if not already covered */
0488     if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
0489         if (ppc4xx_setup_one_pcix_POM(hose, reg, hose->isa_mem_phys, 0,
0490                           hose->isa_mem_size, 0, j) == 0)
0491             printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n",
0492                    hose->dn);
0493 }
0494
0495 static void __init ppc4xx_configure_pcix_PIMs(struct pci_controller *hose,
0496                           void __iomem *reg,
0497                           const struct resource *res,
0498                           int big_pim,
0499                           int enable_msi_hole)
0500 {
0501     resource_size_t size = resource_size(res);
0502     u32 sa;
0503
0504     /* RAM is always at 0 */
0505     writel(0x00000000, reg + PCIX0_PIM0LAH);
0506     writel(0x00000000, reg + PCIX0_PIM0LAL);
0507
0508     /* Calculate window size */
0509     sa = (0xffffffffu << ilog2(size)) | 1;
0510     sa |= 0x1;
0511     if (res->flags & IORESOURCE_PREFETCH)
0512         sa |= 0x2;
0513     if (enable_msi_hole)
0514         sa |= 0x4;
0515     writel(sa, reg + PCIX0_PIM0SA);
0516     if (big_pim)
0517         writel(0xffffffff, reg + PCIX0_PIM0SAH);
0518
0519     /* Map on PCI side */
0520     writel(0x00000000, reg + PCIX0_BAR0H);
0521     writel(res->start, reg + PCIX0_BAR0L);
0522     writew(0x0006, reg + PCIX0_COMMAND);
0523 }
0524
0525 static void __init ppc4xx_probe_pcix_bridge(struct device_node *np)
0526 {
0527     struct resource rsrc_cfg;
0528     struct resource rsrc_reg;
0529     struct resource dma_window;
0530     struct pci_controller *hose = NULL;
0531     void __iomem *reg = NULL;
0532     const int *bus_range;
0533     int big_pim = 0, msi = 0, primary = 0;
0534
0535     /* Fetch config space registers address */
0536     if (of_address_to_resource(np, 0, &rsrc_cfg)) {
0537         printk(KERN_ERR "%pOF: Can't get PCI-X config register base !",
0538                np);
0539         return;
0540     }
0541     /* Fetch host bridge internal registers address */
0542     if (of_address_to_resource(np, 3, &rsrc_reg)) {
0543         printk(KERN_ERR "%pOF: Can't get PCI-X internal register base !",
0544                np);
0545         return;
0546     }
0547
0548     /* Check if it supports large PIMs (440GX) */
0549     if (of_get_property(np, "large-inbound-windows", NULL))
0550         big_pim = 1;
0551
0552     /* Check if we should enable MSIs inbound hole */
0553     if (of_get_property(np, "enable-msi-hole", NULL))
0554         msi = 1;
0555
0556     /* Check if primary bridge */
0557     if (of_get_property(np, "primary", NULL))
0558         primary = 1;
0559
0560     /* Get bus range if any */
0561     bus_range = of_get_property(np, "bus-range", NULL);
0562
0563     /* Map registers */
0564     reg = ioremap(rsrc_reg.start, resource_size(&rsrc_reg));
0565     if (reg == NULL) {
0566         printk(KERN_ERR "%pOF: Can't map registers !", np);
0567         goto fail;
0568     }
0569
0570     /* Allocate the host controller data structure */
0571     hose = pcibios_alloc_controller(np);
0572     if (!hose)
0573         goto fail;
0574
0575     hose->first_busno = bus_range ? bus_range[0] : 0x0;
0576     hose->last_busno = bus_range ? bus_range[1] : 0xff;
0577
0578     /* Setup config space */
0579     setup_indirect_pci(hose, rsrc_cfg.start, rsrc_cfg.start + 0x4,
0580                     PPC_INDIRECT_TYPE_SET_CFG_TYPE);
0581
0582     /* Disable all windows */
0583     writel(0, reg + PCIX0_POM0SA);
0584     writel(0, reg + PCIX0_POM1SA);
0585     writel(0, reg + PCIX0_POM2SA);
0586     writel(0, reg + PCIX0_PIM0SA);
0587     writel(0, reg + PCIX0_PIM1SA);
0588     writel(0, reg + PCIX0_PIM2SA);
0589     if (big_pim) {
0590         writel(0, reg + PCIX0_PIM0SAH);
0591         writel(0, reg + PCIX0_PIM2SAH);
0592     }
0593
0594     /* Parse outbound mapping resources */
0595     pci_process_bridge_OF_ranges(hose, np, primary);
0596
0597     /* Parse inbound mapping resources */
0598     if (ppc4xx_parse_dma_ranges(hose, reg, &dma_window) != 0)
0599         goto fail;
0600
0601     /* Configure outbound ranges POMs */
0602     ppc4xx_configure_pcix_POMs(hose, reg);
0603
0604     /* Configure inbound ranges PIMs */
0605     ppc4xx_configure_pcix_PIMs(hose, reg, &dma_window, big_pim, msi);
0606
0607     /* We don't need the registers anymore */
0608     iounmap(reg);
0609     return;
0610
0611  fail:
0612     if (hose)
0613         pcibios_free_controller(hose);
0614     if (reg)
0615         iounmap(reg);
0616 }
0617
0618 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
0619
0620 /*
0621  * 4xx PCI-Express part
0622  *
0623  * We support 3 parts currently based on the compatible property:
0624  *
0625  * ibm,plb-pciex-440spe
0626  * ibm,plb-pciex-405ex
0627  * ibm,plb-pciex-460ex
0628  *
0629  * Anything else will be rejected for now as they are all subtly
0630  * different unfortunately.
0631  *
0632  */
0633
0634 #define MAX_PCIE_BUS_MAPPED 0x40
0635
0636 struct ppc4xx_pciex_port
0637 {
0638     struct pci_controller   *hose;
0639     struct device_node  *node;
0640     unsigned int        index;
0641     int         endpoint;
0642     int         link;
0643     int         has_ibpre;
0644     unsigned int        sdr_base;
0645     dcr_host_t      dcrs;
0646     struct resource     cfg_space;
0647     struct resource     utl_regs;
0648     void __iomem        *utl_base;
0649 };
0650
0651 static struct ppc4xx_pciex_port *ppc4xx_pciex_ports;
0652 static unsigned int ppc4xx_pciex_port_count;
0653
0654 struct ppc4xx_pciex_hwops
0655 {
0656     bool want_sdr;
0657     int (*core_init)(struct device_node *np);
0658     int (*port_init_hw)(struct ppc4xx_pciex_port *port);
0659     int (*setup_utl)(struct ppc4xx_pciex_port *port);
0660     void (*check_link)(struct ppc4xx_pciex_port *port);
0661 };
0662
0663 static struct ppc4xx_pciex_hwops *ppc4xx_pciex_hwops;
0664
0665 static int __init ppc4xx_pciex_wait_on_sdr(struct ppc4xx_pciex_port *port,
0666                        unsigned int sdr_offset,
0667                        unsigned int mask,
0668                        unsigned int value,
0669                        int timeout_ms)
0670 {
0671     u32 val;
0672
0673     while(timeout_ms--) {
0674         val = mfdcri(SDR0, port->sdr_base + sdr_offset);
0675         if ((val & mask) == value) {
0676             pr_debug("PCIE%d: Wait on SDR %x success with tm %d (%08x)\n",
0677                  port->index, sdr_offset, timeout_ms, val);
0678             return 0;
0679         }
0680         msleep(1);
0681     }
0682     return -1;
0683 }
0684
0685 static int __init ppc4xx_pciex_port_reset_sdr(struct ppc4xx_pciex_port *port)
0686 {
0687     /* Wait for reset to complete */
0688     if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS, 1 << 20, 0, 10)) {
0689         printk(KERN_WARNING "PCIE%d: PGRST failed\n",
0690                port->index);
0691         return -1;
0692     }
0693     return 0;
0694 }
0695
0696
0697 static void __init ppc4xx_pciex_check_link_sdr(struct ppc4xx_pciex_port *port)
0698 {
0699     printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
0700
0701     /* Check for card presence detect if supported, if not, just wait for
0702      * link unconditionally.
0703      *
0704      * note that we don't fail if there is no link, we just filter out
0705      * config space accesses. That way, it will be easier to implement
0706      * hotplug later on.
0707      */
0708     if (!port->has_ibpre ||
0709         !ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
0710                       1 << 28, 1 << 28, 100)) {
0711         printk(KERN_INFO
0712                "PCIE%d: Device detected, waiting for link...\n",
0713                port->index);
0714         if (ppc4xx_pciex_wait_on_sdr(port, PESDRn_LOOP,
0715                          0x1000, 0x1000, 2000))
0716             printk(KERN_WARNING
0717                    "PCIE%d: Link up failed\n", port->index);
0718         else {
0719             printk(KERN_INFO
0720                    "PCIE%d: link is up !\n", port->index);
0721             port->link = 1;
0722         }
0723     } else
0724         printk(KERN_INFO "PCIE%d: No device detected.\n", port->index);
0725 }
0726
0727 #ifdef CONFIG_44x
0728
0729 /* Check various reset bits of the 440SPe PCIe core */
0730 static int __init ppc440spe_pciex_check_reset(struct device_node *np)
0731 {
0732     u32 valPE0, valPE1, valPE2;
0733     int err = 0;
0734
0735     /* SDR0_PEGPLLLCT1 reset */
0736     if (!(mfdcri(SDR0, PESDR0_PLLLCT1) & 0x01000000)) {
0737         /*
0738          * the PCIe core was probably already initialised
0739          * by firmware - let's re-reset RCSSET regs
0740          *
0741          * -- Shouldn't we also re-reset the whole thing ? -- BenH
0742          */
0743         pr_debug("PCIE: SDR0_PLLLCT1 already reset.\n");
0744         mtdcri(SDR0, PESDR0_440SPE_RCSSET, 0x01010000);
0745         mtdcri(SDR0, PESDR1_440SPE_RCSSET, 0x01010000);
0746         mtdcri(SDR0, PESDR2_440SPE_RCSSET, 0x01010000);
0747     }
0748
0749     valPE0 = mfdcri(SDR0, PESDR0_440SPE_RCSSET);
0750     valPE1 = mfdcri(SDR0, PESDR1_440SPE_RCSSET);
0751     valPE2 = mfdcri(SDR0, PESDR2_440SPE_RCSSET);
0752
0753     /* SDR0_PExRCSSET rstgu */
0754     if (!(valPE0 & 0x01000000) ||
0755         !(valPE1 & 0x01000000) ||
0756         !(valPE2 & 0x01000000)) {
0757         printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstgu error\n");
0758         err = -1;
0759     }
0760
0761     /* SDR0_PExRCSSET rstdl */
0762     if (!(valPE0 & 0x00010000) ||
0763         !(valPE1 & 0x00010000) ||
0764         !(valPE2 & 0x00010000)) {
0765         printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstdl error\n");
0766         err = -1;
0767     }
0768
0769     /* SDR0_PExRCSSET rstpyn */
0770     if ((valPE0 & 0x00001000) ||
0771         (valPE1 & 0x00001000) ||
0772         (valPE2 & 0x00001000)) {
0773         printk(KERN_INFO "PCIE: SDR0_PExRCSSET rstpyn error\n");
0774         err = -1;
0775     }
0776
0777     /* SDR0_PExRCSSET hldplb */
0778     if ((valPE0 & 0x10000000) ||
0779         (valPE1 & 0x10000000) ||
0780         (valPE2 & 0x10000000)) {
0781         printk(KERN_INFO "PCIE: SDR0_PExRCSSET hldplb error\n");
0782         err = -1;
0783     }
0784
0785     /* SDR0_PExRCSSET rdy */
0786     if ((valPE0 & 0x00100000) ||
0787         (valPE1 & 0x00100000) ||
0788         (valPE2 & 0x00100000)) {
0789         printk(KERN_INFO "PCIE: SDR0_PExRCSSET rdy error\n");
0790         err = -1;
0791     }
0792
0793     /* SDR0_PExRCSSET shutdown */
0794     if ((valPE0 & 0x00000100) ||
0795         (valPE1 & 0x00000100) ||
0796         (valPE2 & 0x00000100)) {
0797         printk(KERN_INFO "PCIE: SDR0_PExRCSSET shutdown error\n");
0798         err = -1;
0799     }
0800
0801     return err;
0802 }
0803
0804 /* Global PCIe core initializations for 440SPe core */
0805 static int __init ppc440spe_pciex_core_init(struct device_node *np)
0806 {
0807     int time_out = 20;
0808
0809     /* Set PLL clock receiver to LVPECL */
0810     dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
0811
0812     /* Shouldn't we do all the calibration stuff etc... here ? */
0813     if (ppc440spe_pciex_check_reset(np))
0814         return -ENXIO;
0815
0816     if (!(mfdcri(SDR0, PESDR0_PLLLCT2) & 0x10000)) {
0817         printk(KERN_INFO "PCIE: PESDR_PLLCT2 resistance calibration "
0818                "failed (0x%08x)\n",
0819                mfdcri(SDR0, PESDR0_PLLLCT2));
0820         return -1;
0821     }
0822
0823     /* De-assert reset of PCIe PLL, wait for lock */
0824     dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
0825     udelay(3);
0826
0827     while (time_out) {
0828         if (!(mfdcri(SDR0, PESDR0_PLLLCT3) & 0x10000000)) {
0829             time_out--;
0830             udelay(1);
0831         } else
0832             break;
0833     }
0834     if (!time_out) {
0835         printk(KERN_INFO "PCIE: VCO output not locked\n");
0836         return -1;
0837     }
0838
0839     pr_debug("PCIE initialization OK\n");
0840
0841     return 3;
0842 }
0843
0844 static int __init ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
0845 {
0846     u32 val = 1 << 24;
0847
0848     if (port->endpoint)
0849         val = PTYPE_LEGACY_ENDPOINT << 20;
0850     else
0851         val = PTYPE_ROOT_PORT << 20;
0852
0853     if (port->index == 0)
0854         val |= LNKW_X8 << 12;
0855     else
0856         val |= LNKW_X4 << 12;
0857
0858     mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
0859     mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x20222222);
0860     if (ppc440spe_revA())
0861         mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x11000000);
0862     mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL0SET1, 0x35000000);
0863     mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL1SET1, 0x35000000);
0864     mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL2SET1, 0x35000000);
0865     mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL3SET1, 0x35000000);
0866     if (port->index == 0) {
0867         mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL4SET1,
0868                0x35000000);
0869         mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL5SET1,
0870                0x35000000);
0871         mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL6SET1,
0872                0x35000000);
0873         mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
0874                0x35000000);
0875     }
0876     dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
0877             (1 << 24) | (1 << 16), 1 << 12);
0878
0879     return ppc4xx_pciex_port_reset_sdr(port);
0880 }
0881
0882 static int __init ppc440speA_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
0883 {
0884     return ppc440spe_pciex_init_port_hw(port);
0885 }
0886
0887 static int __init ppc440speB_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
0888 {
0889     int rc = ppc440spe_pciex_init_port_hw(port);
0890
0891     port->has_ibpre = 1;
0892
0893     return rc;
0894 }
0895
0896 static int ppc440speA_pciex_init_utl(struct ppc4xx_pciex_port *port)
0897 {
0898     /* XXX Check what that value means... I hate magic */
0899     dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x68782800);
0900
0901     /*
0902      * Set buffer allocations and then assert VRB and TXE.
0903      */
0904     out_be32(port->utl_base + PEUTL_OUTTR,   0x08000000);
0905     out_be32(port->utl_base + PEUTL_INTR,    0x02000000);
0906     out_be32(port->utl_base + PEUTL_OPDBSZ,  0x10000000);
0907     out_be32(port->utl_base + PEUTL_PBBSZ,   0x53000000);
0908     out_be32(port->utl_base + PEUTL_IPHBSZ,  0x08000000);
0909     out_be32(port->utl_base + PEUTL_IPDBSZ,  0x10000000);
0910     out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
0911     out_be32(port->utl_base + PEUTL_PCTL,    0x80800066);
0912
0913     return 0;
0914 }
0915
0916 static int ppc440speB_pciex_init_utl(struct ppc4xx_pciex_port *port)
0917 {
0918     /* Report CRS to the operating system */
0919     out_be32(port->utl_base + PEUTL_PBCTL,    0x08000000);
0920
0921     return 0;
0922 }
0923
0924 static struct ppc4xx_pciex_hwops ppc440speA_pcie_hwops __initdata =
0925 {
0926     .want_sdr   = true,
0927     .core_init  = ppc440spe_pciex_core_init,
0928     .port_init_hw   = ppc440speA_pciex_init_port_hw,
0929     .setup_utl  = ppc440speA_pciex_init_utl,
0930     .check_link = ppc4xx_pciex_check_link_sdr,
0931 };
0932
0933 static struct ppc4xx_pciex_hwops ppc440speB_pcie_hwops __initdata =
0934 {
0935     .want_sdr   = true,
0936     .core_init  = ppc440spe_pciex_core_init,
0937     .port_init_hw   = ppc440speB_pciex_init_port_hw,
0938     .setup_utl  = ppc440speB_pciex_init_utl,
0939     .check_link = ppc4xx_pciex_check_link_sdr,
0940 };
0941
0942 static int __init ppc460ex_pciex_core_init(struct device_node *np)
0943 {
0944     /* Nothing to do, return 2 ports */
0945     return 2;
0946 }
0947
0948 static int __init ppc460ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
0949 {
0950     u32 val;
0951     u32 utlset1;
0952
0953     if (port->endpoint)
0954         val = PTYPE_LEGACY_ENDPOINT << 20;
0955     else
0956         val = PTYPE_ROOT_PORT << 20;
0957
0958     if (port->index == 0) {
0959         val |= LNKW_X1 << 12;
0960         utlset1 = 0x20000000;
0961     } else {
0962         val |= LNKW_X4 << 12;
0963         utlset1 = 0x20101101;
0964     }
0965
0966     mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
0967     mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, utlset1);
0968     mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01210000);
0969
0970     switch (port->index) {
0971     case 0:
0972         mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
0973         mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
0974         mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
0975
0976         mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST,0x10000000);
0977         break;
0978
0979     case 1:
0980         mtdcri(SDR0, PESDR1_460EX_L0CDRCTL, 0x00003230);
0981         mtdcri(SDR0, PESDR1_460EX_L1CDRCTL, 0x00003230);
0982         mtdcri(SDR0, PESDR1_460EX_L2CDRCTL, 0x00003230);
0983         mtdcri(SDR0, PESDR1_460EX_L3CDRCTL, 0x00003230);
0984         mtdcri(SDR0, PESDR1_460EX_L0DRV, 0x00000130);
0985         mtdcri(SDR0, PESDR1_460EX_L1DRV, 0x00000130);
0986         mtdcri(SDR0, PESDR1_460EX_L2DRV, 0x00000130);
0987         mtdcri(SDR0, PESDR1_460EX_L3DRV, 0x00000130);
0988         mtdcri(SDR0, PESDR1_460EX_L0CLK, 0x00000006);
0989         mtdcri(SDR0, PESDR1_460EX_L1CLK, 0x00000006);
0990         mtdcri(SDR0, PESDR1_460EX_L2CLK, 0x00000006);
0991         mtdcri(SDR0, PESDR1_460EX_L3CLK, 0x00000006);
0992
0993         mtdcri(SDR0, PESDR1_460EX_PHY_CTL_RST,0x10000000);
0994         break;
0995     }
0996
0997     mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
0998            mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
0999            (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
1000
1001     /* Poll for PHY reset */
1002     /* XXX FIXME add timeout */
1003     switch (port->index) {
1004     case 0:
1005         while (!(mfdcri(SDR0, PESDR0_460EX_RSTSTA) & 0x1))
1006             udelay(10);
1007         break;
1008     case 1:
1009         while (!(mfdcri(SDR0, PESDR1_460EX_RSTSTA) & 0x1))
1010             udelay(10);
1011         break;
1012     }
1013
1014     mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1015            (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1016         ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1017            PESDRx_RCSSET_RSTPYN);
1018
1019     port->has_ibpre = 1;
1020
1021     return ppc4xx_pciex_port_reset_sdr(port);
1022 }
1023
1024 static int ppc460ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1025 {
1026     dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1027
1028     /*
1029      * Set buffer allocations and then assert VRB and TXE.
1030      */
1031     out_be32(port->utl_base + PEUTL_PBCTL,  0x0800000c);
1032     out_be32(port->utl_base + PEUTL_OUTTR,  0x08000000);
1033     out_be32(port->utl_base + PEUTL_INTR,   0x02000000);
1034     out_be32(port->utl_base + PEUTL_OPDBSZ, 0x04000000);
1035     out_be32(port->utl_base + PEUTL_PBBSZ,  0x00000000);
1036     out_be32(port->utl_base + PEUTL_IPHBSZ, 0x02000000);
1037     out_be32(port->utl_base + PEUTL_IPDBSZ, 0x04000000);
1038     out_be32(port->utl_base + PEUTL_RCIRQEN,0x00f00000);
1039     out_be32(port->utl_base + PEUTL_PCTL,   0x80800066);
1040
1041     return 0;
1042 }
1043
1044 static struct ppc4xx_pciex_hwops ppc460ex_pcie_hwops __initdata =
1045 {
1046     .want_sdr   = true,
1047     .core_init  = ppc460ex_pciex_core_init,
1048     .port_init_hw   = ppc460ex_pciex_init_port_hw,
1049     .setup_utl  = ppc460ex_pciex_init_utl,
1050     .check_link = ppc4xx_pciex_check_link_sdr,
1051 };
1052
1053 static int __init apm821xx_pciex_core_init(struct device_node *np)
1054 {
1055     /* Return the number of pcie port */
1056     return 1;
1057 }
1058
1059 static int __init apm821xx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1060 {
1061     u32 val;
1062
1063     /*
1064      * Do a software reset on PCIe ports.
1065      * This code is to fix the issue that pci drivers doesn't re-assign
1066      * bus number for PCIE devices after Uboot
1067      * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
1068      * PT quad port, SAS LSI 1064E)
1069      */
1070
1071     mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
1072     mdelay(10);
1073
1074     if (port->endpoint)
1075         val = PTYPE_LEGACY_ENDPOINT << 20;
1076     else
1077         val = PTYPE_ROOT_PORT << 20;
1078
1079     val |= LNKW_X1 << 12;
1080
1081     mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET, val);
1082     mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1083     mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1084
1085     mtdcri(SDR0, PESDR0_460EX_L0CDRCTL, 0x00003230);
1086     mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
1087     mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
1088
1089     mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
1090     mdelay(50);
1091     mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
1092
1093     mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1094         mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |
1095         (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTPYN));
1096
1097     /* Poll for PHY reset */
1098     val = PESDR0_460EX_RSTSTA - port->sdr_base;
1099     if (ppc4xx_pciex_wait_on_sdr(port, val, 0x1, 1, 100)) {
1100         printk(KERN_WARNING "%s: PCIE: Can't reset PHY\n", __func__);
1101         return -EBUSY;
1102     } else {
1103         mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
1104             (mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) &
1105             ~(PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL)) |
1106             PESDRx_RCSSET_RSTPYN);
1107
1108         port->has_ibpre = 1;
1109         return 0;
1110     }
1111 }
1112
1113 static struct ppc4xx_pciex_hwops apm821xx_pcie_hwops __initdata = {
1114     .want_sdr   = true,
1115     .core_init  = apm821xx_pciex_core_init,
1116     .port_init_hw   = apm821xx_pciex_init_port_hw,
1117     .setup_utl  = ppc460ex_pciex_init_utl,
1118     .check_link = ppc4xx_pciex_check_link_sdr,
1119 };
1120
1121 static int __init ppc460sx_pciex_core_init(struct device_node *np)
1122 {
1123     /* HSS drive amplitude */
1124     mtdcri(SDR0, PESDR0_460SX_HSSL0DAMP, 0xB9843211);
1125     mtdcri(SDR0, PESDR0_460SX_HSSL1DAMP, 0xB9843211);
1126     mtdcri(SDR0, PESDR0_460SX_HSSL2DAMP, 0xB9843211);
1127     mtdcri(SDR0, PESDR0_460SX_HSSL3DAMP, 0xB9843211);
1128     mtdcri(SDR0, PESDR0_460SX_HSSL4DAMP, 0xB9843211);
1129     mtdcri(SDR0, PESDR0_460SX_HSSL5DAMP, 0xB9843211);
1130     mtdcri(SDR0, PESDR0_460SX_HSSL6DAMP, 0xB9843211);
1131     mtdcri(SDR0, PESDR0_460SX_HSSL7DAMP, 0xB9843211);
1132
1133     mtdcri(SDR0, PESDR1_460SX_HSSL0DAMP, 0xB9843211);
1134     mtdcri(SDR0, PESDR1_460SX_HSSL1DAMP, 0xB9843211);
1135     mtdcri(SDR0, PESDR1_460SX_HSSL2DAMP, 0xB9843211);
1136     mtdcri(SDR0, PESDR1_460SX_HSSL3DAMP, 0xB9843211);
1137
1138     mtdcri(SDR0, PESDR2_460SX_HSSL0DAMP, 0xB9843211);
1139     mtdcri(SDR0, PESDR2_460SX_HSSL1DAMP, 0xB9843211);
1140     mtdcri(SDR0, PESDR2_460SX_HSSL2DAMP, 0xB9843211);
1141     mtdcri(SDR0, PESDR2_460SX_HSSL3DAMP, 0xB9843211);
1142
1143     /* HSS TX pre-emphasis */
1144     mtdcri(SDR0, PESDR0_460SX_HSSL0COEFA, 0xDCB98987);
1145     mtdcri(SDR0, PESDR0_460SX_HSSL1COEFA, 0xDCB98987);
1146     mtdcri(SDR0, PESDR0_460SX_HSSL2COEFA, 0xDCB98987);
1147     mtdcri(SDR0, PESDR0_460SX_HSSL3COEFA, 0xDCB98987);
1148     mtdcri(SDR0, PESDR0_460SX_HSSL4COEFA, 0xDCB98987);
1149     mtdcri(SDR0, PESDR0_460SX_HSSL5COEFA, 0xDCB98987);
1150     mtdcri(SDR0, PESDR0_460SX_HSSL6COEFA, 0xDCB98987);
1151     mtdcri(SDR0, PESDR0_460SX_HSSL7COEFA, 0xDCB98987);
1152
1153     mtdcri(SDR0, PESDR1_460SX_HSSL0COEFA, 0xDCB98987);
1154     mtdcri(SDR0, PESDR1_460SX_HSSL1COEFA, 0xDCB98987);
1155     mtdcri(SDR0, PESDR1_460SX_HSSL2COEFA, 0xDCB98987);
1156     mtdcri(SDR0, PESDR1_460SX_HSSL3COEFA, 0xDCB98987);
1157
1158     mtdcri(SDR0, PESDR2_460SX_HSSL0COEFA, 0xDCB98987);
1159     mtdcri(SDR0, PESDR2_460SX_HSSL1COEFA, 0xDCB98987);
1160     mtdcri(SDR0, PESDR2_460SX_HSSL2COEFA, 0xDCB98987);
1161     mtdcri(SDR0, PESDR2_460SX_HSSL3COEFA, 0xDCB98987);
1162
1163     /* HSS TX calibration control */
1164     mtdcri(SDR0, PESDR0_460SX_HSSL1CALDRV, 0x22222222);
1165     mtdcri(SDR0, PESDR1_460SX_HSSL1CALDRV, 0x22220000);
1166     mtdcri(SDR0, PESDR2_460SX_HSSL1CALDRV, 0x22220000);
1167
1168     /* HSS TX slew control */
1169     mtdcri(SDR0, PESDR0_460SX_HSSSLEW, 0xFFFFFFFF);
1170     mtdcri(SDR0, PESDR1_460SX_HSSSLEW, 0xFFFF0000);
1171     mtdcri(SDR0, PESDR2_460SX_HSSSLEW, 0xFFFF0000);
1172
1173     /* Set HSS PRBS enabled */
1174     mtdcri(SDR0, PESDR0_460SX_HSSCTLSET, 0x00001130);
1175     mtdcri(SDR0, PESDR2_460SX_HSSCTLSET, 0x00001130);
1176
1177     udelay(100);
1178
1179     /* De-assert PLLRESET */
1180     dcri_clrset(SDR0, PESDR0_PLLLCT2, 0x00000100, 0);
1181
1182     /* Reset DL, UTL, GPL before configuration */
1183     mtdcri(SDR0, PESDR0_460SX_RCSSET,
1184             PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1185     mtdcri(SDR0, PESDR1_460SX_RCSSET,
1186             PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1187     mtdcri(SDR0, PESDR2_460SX_RCSSET,
1188             PESDRx_RCSSET_RSTDL | PESDRx_RCSSET_RSTGU);
1189
1190     udelay(100);
1191
1192     /*
1193      * If bifurcation is not enabled, u-boot would have disabled the
1194      * third PCIe port
1195      */
1196     if (((mfdcri(SDR0, PESDR1_460SX_HSSCTLSET) & 0x00000001) ==
1197                 0x00000001)) {
1198         printk(KERN_INFO "PCI: PCIE bifurcation setup successfully.\n");
1199         printk(KERN_INFO "PCI: Total 3 PCIE ports are present\n");
1200         return 3;
1201     }
1202
1203     printk(KERN_INFO "PCI: Total 2 PCIE ports are present\n");
1204     return 2;
1205 }
1206
1207 static int __init ppc460sx_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1208 {
1209
1210     if (port->endpoint)
1211         dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1212                 0x01000000, 0);
1213     else
1214         dcri_clrset(SDR0, port->sdr_base + PESDRn_UTLSET2,
1215                 0, 0x01000000);
1216
1217     dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
1218             (PESDRx_RCSSET_RSTGU | PESDRx_RCSSET_RSTDL),
1219             PESDRx_RCSSET_RSTPYN);
1220
1221     port->has_ibpre = 1;
1222
1223     return ppc4xx_pciex_port_reset_sdr(port);
1224 }
1225
1226 static int ppc460sx_pciex_init_utl(struct ppc4xx_pciex_port *port)
1227 {
1228     /* Max 128 Bytes */
1229     out_be32 (port->utl_base + PEUTL_PBBSZ,   0x00000000);
1230     /* Assert VRB and TXE - per datasheet turn off addr validation */
1231     out_be32(port->utl_base + PEUTL_PCTL,  0x80800000);
1232     return 0;
1233 }
1234
1235 static void __init ppc460sx_pciex_check_link(struct ppc4xx_pciex_port *port)
1236 {
1237     void __iomem *mbase;
1238     int attempt = 50;
1239
1240     port->link = 0;
1241
1242     mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1243     if (mbase == NULL) {
1244         printk(KERN_ERR "%pOF: Can't map internal config space !",
1245             port->node);
1246         return;
1247     }
1248
1249     while (attempt && (0 == (in_le32(mbase + PECFG_460SX_DLLSTA)
1250             & PECFG_460SX_DLLSTA_LINKUP))) {
1251         attempt--;
1252         mdelay(10);
1253     }
1254     if (attempt)
1255         port->link = 1;
1256     iounmap(mbase);
1257 }
1258
1259 static struct ppc4xx_pciex_hwops ppc460sx_pcie_hwops __initdata = {
1260     .want_sdr   = true,
1261     .core_init  = ppc460sx_pciex_core_init,
1262     .port_init_hw   = ppc460sx_pciex_init_port_hw,
1263     .setup_utl  = ppc460sx_pciex_init_utl,
1264     .check_link = ppc460sx_pciex_check_link,
1265 };
1266
1267 #endif /* CONFIG_44x */
1268
1269 #ifdef CONFIG_40x
1270
1271 static int __init ppc405ex_pciex_core_init(struct device_node *np)
1272 {
1273     /* Nothing to do, return 2 ports */
1274     return 2;
1275 }
1276
1277 static void __init ppc405ex_pcie_phy_reset(struct ppc4xx_pciex_port *port)
1278 {
1279     /* Assert the PE0_PHY reset */
1280     mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01010000);
1281     msleep(1);
1282
1283     /* deassert the PE0_hotreset */
1284     if (port->endpoint)
1285         mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01111000);
1286     else
1287         mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x01101000);
1288
1289     /* poll for phy !reset */
1290     /* XXX FIXME add timeout */
1291     while (!(mfdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSTA) & 0x00001000))
1292         ;
1293
1294     /* deassert the PE0_gpl_utl_reset */
1295     mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET, 0x00101000);
1296 }
1297
1298 static int __init ppc405ex_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
1299 {
1300     u32 val;
1301
1302     if (port->endpoint)
1303         val = PTYPE_LEGACY_ENDPOINT;
1304     else
1305         val = PTYPE_ROOT_PORT;
1306
1307     mtdcri(SDR0, port->sdr_base + PESDRn_DLPSET,
1308            1 << 24 | val << 20 | LNKW_X1 << 12);
1309
1310     mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET1, 0x00000000);
1311     mtdcri(SDR0, port->sdr_base + PESDRn_UTLSET2, 0x01010000);
1312     mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET1, 0x720F0000);
1313     mtdcri(SDR0, port->sdr_base + PESDRn_405EX_PHYSET2, 0x70600003);
1314
1315     /*
1316      * Only reset the PHY when no link is currently established.
1317      * This is for the Atheros PCIe board which has problems to establish
1318      * the link (again) after this PHY reset. All other currently tested
1319      * PCIe boards don't show this problem.
1320      * This has to be re-tested and fixed in a later release!
1321      */
1322     val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
1323     if (!(val & 0x00001000))
1324         ppc405ex_pcie_phy_reset(port);
1325
1326     dcr_write(port->dcrs, DCRO_PEGPL_CFG, 0x10000000);  /* guarded on */
1327
1328     port->has_ibpre = 1;
1329
1330     return ppc4xx_pciex_port_reset_sdr(port);
1331 }
1332
1333 static int ppc405ex_pciex_init_utl(struct ppc4xx_pciex_port *port)
1334 {
1335     dcr_write(port->dcrs, DCRO_PEGPL_SPECIAL, 0x0);
1336
1337     /*
1338      * Set buffer allocations and then assert VRB and TXE.
1339      */
1340     out_be32(port->utl_base + PEUTL_OUTTR,   0x02000000);
1341     out_be32(port->utl_base + PEUTL_INTR,    0x02000000);
1342     out_be32(port->utl_base + PEUTL_OPDBSZ,  0x04000000);
1343     out_be32(port->utl_base + PEUTL_PBBSZ,   0x21000000);
1344     out_be32(port->utl_base + PEUTL_IPHBSZ,  0x02000000);
1345     out_be32(port->utl_base + PEUTL_IPDBSZ,  0x04000000);
1346     out_be32(port->utl_base + PEUTL_RCIRQEN, 0x00f00000);
1347     out_be32(port->utl_base + PEUTL_PCTL,    0x80800066);
1348
1349     out_be32(port->utl_base + PEUTL_PBCTL,   0x08000000);
1350
1351     return 0;
1352 }
1353
1354 static struct ppc4xx_pciex_hwops ppc405ex_pcie_hwops __initdata =
1355 {
1356     .want_sdr   = true,
1357     .core_init  = ppc405ex_pciex_core_init,
1358     .port_init_hw   = ppc405ex_pciex_init_port_hw,
1359     .setup_utl  = ppc405ex_pciex_init_utl,
1360     .check_link = ppc4xx_pciex_check_link_sdr,
1361 };
1362
1363 #endif /* CONFIG_40x */
1364
1365 #ifdef CONFIG_476FPE
1366 static int __init ppc_476fpe_pciex_core_init(struct device_node *np)
1367 {
1368     return 4;
1369 }
1370
1371 static void __init ppc_476fpe_pciex_check_link(struct ppc4xx_pciex_port *port)
1372 {
1373     u32 timeout_ms = 20;
1374     u32 val = 0, mask = (PECFG_TLDLP_LNKUP|PECFG_TLDLP_PRESENT);
1375     void __iomem *mbase = ioremap(port->cfg_space.start + 0x10000000,
1376                                   0x1000);
1377
1378     printk(KERN_INFO "PCIE%d: Checking link...\n", port->index);
1379
1380     if (mbase == NULL) {
1381         printk(KERN_WARNING "PCIE%d: failed to get cfg space\n",
1382                             port->index);
1383         return;
1384     }
1385
1386     while (timeout_ms--) {
1387         val = in_le32(mbase + PECFG_TLDLP);
1388
1389         if ((val & mask) == mask)
1390             break;
1391         msleep(10);
1392     }
1393
1394     if (val & PECFG_TLDLP_PRESENT) {
1395         printk(KERN_INFO "PCIE%d: link is up !\n", port->index);
1396         port->link = 1;
1397     } else
1398         printk(KERN_WARNING "PCIE%d: Link up failed\n", port->index);
1399
1400     iounmap(mbase);
1401 }
1402
1403 static struct ppc4xx_pciex_hwops ppc_476fpe_pcie_hwops __initdata =
1404 {
1405     .core_init  = ppc_476fpe_pciex_core_init,
1406     .check_link = ppc_476fpe_pciex_check_link,
1407 };
1408 #endif /* CONFIG_476FPE */
1409
1410 /* Check that the core has been initied and if not, do it */
1411 static int __init ppc4xx_pciex_check_core_init(struct device_node *np)
1412 {
1413     static int core_init;
1414     int count = -ENODEV;
1415
1416     if (core_init++)
1417         return 0;
1418
1419 #ifdef CONFIG_44x
1420     if (of_device_is_compatible(np, "ibm,plb-pciex-440spe")) {
1421         if (ppc440spe_revA())
1422             ppc4xx_pciex_hwops = &ppc440speA_pcie_hwops;
1423         else
1424             ppc4xx_pciex_hwops = &ppc440speB_pcie_hwops;
1425     }
1426     if (of_device_is_compatible(np, "ibm,plb-pciex-460ex"))
1427         ppc4xx_pciex_hwops = &ppc460ex_pcie_hwops;
1428     if (of_device_is_compatible(np, "ibm,plb-pciex-460sx"))
1429         ppc4xx_pciex_hwops = &ppc460sx_pcie_hwops;
1430     if (of_device_is_compatible(np, "ibm,plb-pciex-apm821xx"))
1431         ppc4xx_pciex_hwops = &apm821xx_pcie_hwops;
1432 #endif /* CONFIG_44x    */
1433 #ifdef CONFIG_40x
1434     if (of_device_is_compatible(np, "ibm,plb-pciex-405ex"))
1435         ppc4xx_pciex_hwops = &ppc405ex_pcie_hwops;
1436 #endif
1437 #ifdef CONFIG_476FPE
1438     if (of_device_is_compatible(np, "ibm,plb-pciex-476fpe")
1439         || of_device_is_compatible(np, "ibm,plb-pciex-476gtr"))
1440         ppc4xx_pciex_hwops = &ppc_476fpe_pcie_hwops;
1441 #endif
1442     if (ppc4xx_pciex_hwops == NULL) {
1443         printk(KERN_WARNING "PCIE: unknown host type %pOF\n", np);
1444         return -ENODEV;
1445     }
1446
1447     count = ppc4xx_pciex_hwops->core_init(np);
1448     if (count > 0) {
1449         ppc4xx_pciex_ports =
1450                kcalloc(count, sizeof(struct ppc4xx_pciex_port),
1451                    GFP_KERNEL);
1452         if (ppc4xx_pciex_ports) {
1453             ppc4xx_pciex_port_count = count;
1454             return 0;
1455         }
1456         printk(KERN_WARNING "PCIE: failed to allocate ports array\n");
1457         return -ENOMEM;
1458     }
1459     return -ENODEV;
1460 }
1461
1462 static void __init ppc4xx_pciex_port_init_mapping(struct ppc4xx_pciex_port *port)
1463 {
1464     /* We map PCI Express configuration based on the reg property */
1465     dcr_write(port->dcrs, DCRO_PEGPL_CFGBAH,
1466           RES_TO_U32_HIGH(port->cfg_space.start));
1467     dcr_write(port->dcrs, DCRO_PEGPL_CFGBAL,
1468           RES_TO_U32_LOW(port->cfg_space.start));
1469
1470     /* XXX FIXME: Use size from reg property. For now, map 512M */
1471     dcr_write(port->dcrs, DCRO_PEGPL_CFGMSK, 0xe0000001);
1472
1473     /* We map UTL registers based on the reg property */
1474     dcr_write(port->dcrs, DCRO_PEGPL_REGBAH,
1475           RES_TO_U32_HIGH(port->utl_regs.start));
1476     dcr_write(port->dcrs, DCRO_PEGPL_REGBAL,
1477           RES_TO_U32_LOW(port->utl_regs.start));
1478
1479     /* XXX FIXME: Use size from reg property */
1480     dcr_write(port->dcrs, DCRO_PEGPL_REGMSK, 0x00007001);
1481
1482     /* Disable all other outbound windows */
1483     dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL, 0);
1484     dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL, 0);
1485     dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL, 0);
1486     dcr_write(port->dcrs, DCRO_PEGPL_MSGMSK, 0);
1487 }
1488
1489 static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
1490 {
1491     int rc = 0;
1492
1493     /* Init HW */
1494     if (ppc4xx_pciex_hwops->port_init_hw)
1495         rc = ppc4xx_pciex_hwops->port_init_hw(port);
1496     if (rc != 0)
1497         return rc;
1498
1499     /*
1500      * Initialize mapping: disable all regions and configure
1501      * CFG and REG regions based on resources in the device tree
1502      */
1503     ppc4xx_pciex_port_init_mapping(port);
1504
1505     if (ppc4xx_pciex_hwops->check_link)
1506         ppc4xx_pciex_hwops->check_link(port);
1507
1508     /*
1509      * Map UTL
1510      */
1511     port->utl_base = ioremap(port->utl_regs.start, 0x100);
1512     BUG_ON(port->utl_base == NULL);
1513
1514     /*
1515      * Setup UTL registers --BenH.
1516      */
1517     if (ppc4xx_pciex_hwops->setup_utl)
1518         ppc4xx_pciex_hwops->setup_utl(port);
1519
1520     /*
1521      * Check for VC0 active or PLL Locked and assert RDY.
1522      */
1523     if (port->sdr_base) {
1524         if (of_device_is_compatible(port->node,
1525                 "ibm,plb-pciex-460sx")){
1526             if (port->link && ppc4xx_pciex_wait_on_sdr(port,
1527                     PESDRn_RCSSTS,
1528                     1 << 12, 1 << 12, 5000)) {
1529                 printk(KERN_INFO "PCIE%d: PLL not locked\n",
1530                         port->index);
1531                 port->link = 0;
1532             }
1533         } else if (port->link &&
1534             ppc4xx_pciex_wait_on_sdr(port, PESDRn_RCSSTS,
1535                 1 << 16, 1 << 16, 5000)) {
1536             printk(KERN_INFO "PCIE%d: VC0 not active\n",
1537                     port->index);
1538             port->link = 0;
1539         }
1540
1541         dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
1542     }
1543
1544     msleep(100);
1545
1546     return 0;
1547 }
1548
1549 static int ppc4xx_pciex_validate_bdf(struct ppc4xx_pciex_port *port,
1550                      struct pci_bus *bus,
1551                      unsigned int devfn)
1552 {
1553     static int message;
1554
1555     /* Endpoint can not generate upstream(remote) config cycles */
1556     if (port->endpoint && bus->number != port->hose->first_busno)
1557         return PCIBIOS_DEVICE_NOT_FOUND;
1558
1559     /* Check we are within the mapped range */
1560     if (bus->number > port->hose->last_busno) {
1561         if (!message) {
1562             printk(KERN_WARNING "Warning! Probing bus %u"
1563                    " out of range !\n", bus->number);
1564             message++;
1565         }
1566         return PCIBIOS_DEVICE_NOT_FOUND;
1567     }
1568
1569     /* The root complex has only one device / function */
1570     if (bus->number == port->hose->first_busno && devfn != 0)
1571         return PCIBIOS_DEVICE_NOT_FOUND;
1572
1573     /* The other side of the RC has only one device as well */
1574     if (bus->number == (port->hose->first_busno + 1) &&
1575         PCI_SLOT(devfn) != 0)
1576         return PCIBIOS_DEVICE_NOT_FOUND;
1577
1578     /* Check if we have a link */
1579     if ((bus->number != port->hose->first_busno) && !port->link)
1580         return PCIBIOS_DEVICE_NOT_FOUND;
1581
1582     return 0;
1583 }
1584
1585 static void __iomem *ppc4xx_pciex_get_config_base(struct ppc4xx_pciex_port *port,
1586                           struct pci_bus *bus,
1587                           unsigned int devfn)
1588 {
1589     int relbus;
1590
1591     /* Remove the casts when we finally remove the stupid volatile
1592      * in struct pci_controller
1593      */
1594     if (bus->number == port->hose->first_busno)
1595         return (void __iomem *)port->hose->cfg_addr;
1596
1597     relbus = bus->number - (port->hose->first_busno + 1);
1598     return (void __iomem *)port->hose->cfg_data +
1599         ((relbus  << 20) | (devfn << 12));
1600 }
1601
1602 static int ppc4xx_pciex_read_config(struct pci_bus *bus, unsigned int devfn,
1603                     int offset, int len, u32 *val)
1604 {
1605     struct pci_controller *hose = pci_bus_to_host(bus);
1606     struct ppc4xx_pciex_port *port =
1607         &ppc4xx_pciex_ports[hose->indirect_type];
1608     void __iomem *addr;
1609     u32 gpl_cfg;
1610
1611     BUG_ON(hose != port->hose);
1612
1613     if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1614         return PCIBIOS_DEVICE_NOT_FOUND;
1615
1616     addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1617
1618     /*
1619      * Reading from configuration space of non-existing device can
1620      * generate transaction errors. For the read duration we suppress
1621      * assertion of machine check exceptions to avoid those.
1622      */
1623     gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1624     dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1625
1626     /* Make sure no CRS is recorded */
1627     out_be32(port->utl_base + PEUTL_RCSTA, 0x00040000);
1628
1629     switch (len) {
1630     case 1:
1631         *val = in_8((u8 *)(addr + offset));
1632         break;
1633     case 2:
1634         *val = in_le16((u16 *)(addr + offset));
1635         break;
1636     default:
1637         *val = in_le32((u32 *)(addr + offset));
1638         break;
1639     }
1640
1641     pr_debug("pcie-config-read: bus=%3d [%3d..%3d] devfn=0x%04x"
1642          " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1643          bus->number, hose->first_busno, hose->last_busno,
1644          devfn, offset, len, addr + offset, *val);
1645
1646     /* Check for CRS (440SPe rev B does that for us but heh ..) */
1647     if (in_be32(port->utl_base + PEUTL_RCSTA) & 0x00040000) {
1648         pr_debug("Got CRS !\n");
1649         if (len != 4 || offset != 0)
1650             return PCIBIOS_DEVICE_NOT_FOUND;
1651         *val = 0xffff0001;
1652     }
1653
1654     dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1655
1656     return PCIBIOS_SUCCESSFUL;
1657 }
1658
1659 static int ppc4xx_pciex_write_config(struct pci_bus *bus, unsigned int devfn,
1660                      int offset, int len, u32 val)
1661 {
1662     struct pci_controller *hose = pci_bus_to_host(bus);
1663     struct ppc4xx_pciex_port *port =
1664         &ppc4xx_pciex_ports[hose->indirect_type];
1665     void __iomem *addr;
1666     u32 gpl_cfg;
1667
1668     if (ppc4xx_pciex_validate_bdf(port, bus, devfn) != 0)
1669         return PCIBIOS_DEVICE_NOT_FOUND;
1670
1671     addr = ppc4xx_pciex_get_config_base(port, bus, devfn);
1672
1673     /*
1674      * Reading from configuration space of non-existing device can
1675      * generate transaction errors. For the read duration we suppress
1676      * assertion of machine check exceptions to avoid those.
1677      */
1678     gpl_cfg = dcr_read(port->dcrs, DCRO_PEGPL_CFG);
1679     dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg | GPL_DMER_MASK_DISA);
1680
1681     pr_debug("pcie-config-write: bus=%3d [%3d..%3d] devfn=0x%04x"
1682          " offset=0x%04x len=%d, addr=0x%p val=0x%08x\n",
1683          bus->number, hose->first_busno, hose->last_busno,
1684          devfn, offset, len, addr + offset, val);
1685
1686     switch (len) {
1687     case 1:
1688         out_8((u8 *)(addr + offset), val);
1689         break;
1690     case 2:
1691         out_le16((u16 *)(addr + offset), val);
1692         break;
1693     default:
1694         out_le32((u32 *)(addr + offset), val);
1695         break;
1696     }
1697
1698     dcr_write(port->dcrs, DCRO_PEGPL_CFG, gpl_cfg);
1699
1700     return PCIBIOS_SUCCESSFUL;
1701 }
1702
1703 static struct pci_ops ppc4xx_pciex_pci_ops =
1704 {
1705     .read  = ppc4xx_pciex_read_config,
1706     .write = ppc4xx_pciex_write_config,
1707 };
1708
1709 static int __init ppc4xx_setup_one_pciex_POM(struct ppc4xx_pciex_port   *port,
1710                          struct pci_controller  *hose,
1711                          void __iomem       *mbase,
1712                          u64            plb_addr,
1713                          u64            pci_addr,
1714                          u64            size,
1715                          unsigned int       flags,
1716                          int            index)
1717 {
1718     u32 lah, lal, pciah, pcial, sa;
1719
1720     if (!is_power_of_2(size) ||
1721         (index < 2 && size < 0x100000) ||
1722         (index == 2 && size < 0x100) ||
1723         (plb_addr & (size - 1)) != 0) {
1724         printk(KERN_WARNING "%pOF: Resource out of range\n", hose->dn);
1725         return -1;
1726     }
1727
1728     /* Calculate register values */
1729     lah = RES_TO_U32_HIGH(plb_addr);
1730     lal = RES_TO_U32_LOW(plb_addr);
1731     pciah = RES_TO_U32_HIGH(pci_addr);
1732     pcial = RES_TO_U32_LOW(pci_addr);
1733     sa = (0xffffffffu << ilog2(size)) | 0x1;
1734
1735     /* Program register values */
1736     switch (index) {
1737     case 0:
1738         out_le32(mbase + PECFG_POM0LAH, pciah);
1739         out_le32(mbase + PECFG_POM0LAL, pcial);
1740         dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAH, lah);
1741         dcr_write(port->dcrs, DCRO_PEGPL_OMR1BAL, lal);
1742         dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKH, 0x7fffffff);
1743         /*Enabled and single region */
1744         if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
1745             dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1746                 sa | DCRO_PEGPL_460SX_OMR1MSKL_UOT
1747                     | DCRO_PEGPL_OMRxMSKL_VAL);
1748         else if (of_device_is_compatible(
1749                 port->node, "ibm,plb-pciex-476fpe") ||
1750             of_device_is_compatible(
1751                 port->node, "ibm,plb-pciex-476gtr"))
1752             dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1753                 sa | DCRO_PEGPL_476FPE_OMR1MSKL_UOT
1754                     | DCRO_PEGPL_OMRxMSKL_VAL);
1755         else
1756             dcr_write(port->dcrs, DCRO_PEGPL_OMR1MSKL,
1757                 sa | DCRO_PEGPL_OMR1MSKL_UOT
1758                     | DCRO_PEGPL_OMRxMSKL_VAL);
1759         break;
1760     case 1:
1761         out_le32(mbase + PECFG_POM1LAH, pciah);
1762         out_le32(mbase + PECFG_POM1LAL, pcial);
1763         dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAH, lah);
1764         dcr_write(port->dcrs, DCRO_PEGPL_OMR2BAL, lal);
1765         dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKH, 0x7fffffff);
1766         dcr_write(port->dcrs, DCRO_PEGPL_OMR2MSKL,
1767                 sa | DCRO_PEGPL_OMRxMSKL_VAL);
1768         break;
1769     case 2:
1770         out_le32(mbase + PECFG_POM2LAH, pciah);
1771         out_le32(mbase + PECFG_POM2LAL, pcial);
1772         dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAH, lah);
1773         dcr_write(port->dcrs, DCRO_PEGPL_OMR3BAL, lal);
1774         dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKH, 0x7fffffff);
1775         /* Note that 3 here means enabled | IO space !!! */
1776         dcr_write(port->dcrs, DCRO_PEGPL_OMR3MSKL,
1777                 sa | DCRO_PEGPL_OMR3MSKL_IO
1778                     | DCRO_PEGPL_OMRxMSKL_VAL);
1779         break;
1780     }
1781
1782     return 0;
1783 }
1784
1785 static void __init ppc4xx_configure_pciex_POMs(struct ppc4xx_pciex_port *port,
1786                            struct pci_controller *hose,
1787                            void __iomem *mbase)
1788 {
1789     int i, j, found_isa_hole = 0;
1790
1791     /* Setup outbound memory windows */
1792     for (i = j = 0; i < 3; i++) {
1793         struct resource *res = &hose->mem_resources[i];
1794         resource_size_t offset = hose->mem_offset[i];
1795
1796         /* we only care about memory windows */
1797         if (!(res->flags & IORESOURCE_MEM))
1798             continue;
1799         if (j > 1) {
1800             printk(KERN_WARNING "%pOF: Too many ranges\n",
1801                    port->node);
1802             break;
1803         }
1804
1805         /* Configure the resource */
1806         if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1807                            res->start,
1808                            res->start - offset,
1809                            resource_size(res),
1810                            res->flags,
1811                            j) == 0) {
1812             j++;
1813
1814             /* If the resource PCI address is 0 then we have our
1815              * ISA memory hole
1816              */
1817             if (res->start == offset)
1818                 found_isa_hole = 1;
1819         }
1820     }
1821
1822     /* Handle ISA memory hole if not already covered */
1823     if (j <= 1 && !found_isa_hole && hose->isa_mem_size)
1824         if (ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1825                            hose->isa_mem_phys, 0,
1826                            hose->isa_mem_size, 0, j) == 0)
1827             printk(KERN_INFO "%pOF: Legacy ISA memory support enabled\n",
1828                    hose->dn);
1829
1830     /* Configure IO, always 64K starting at 0. We hard wire it to 64K !
1831      * Note also that it -has- to be region index 2 on this HW
1832      */
1833     if (hose->io_resource.flags & IORESOURCE_IO)
1834         ppc4xx_setup_one_pciex_POM(port, hose, mbase,
1835                        hose->io_base_phys, 0,
1836                        0x10000, IORESOURCE_IO, 2);
1837 }
1838
1839 static void __init ppc4xx_configure_pciex_PIMs(struct ppc4xx_pciex_port *port,
1840                            struct pci_controller *hose,
1841                            void __iomem *mbase,
1842                            struct resource *res)
1843 {
1844     resource_size_t size = resource_size(res);
1845     u64 sa;
1846
1847     if (port->endpoint) {
1848         resource_size_t ep_addr = 0;
1849         resource_size_t ep_size = 32 << 20;
1850
1851         /* Currently we map a fixed 64MByte window to PLB address
1852          * 0 (SDRAM). This should probably be configurable via a dts
1853          * property.
1854          */
1855
1856         /* Calculate window size */
1857         sa = (0xffffffffffffffffull << ilog2(ep_size));
1858
1859         /* Setup BAR0 */
1860         out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1861         out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa) |
1862              PCI_BASE_ADDRESS_MEM_TYPE_64);
1863
1864         /* Disable BAR1 & BAR2 */
1865         out_le32(mbase + PECFG_BAR1MPA, 0);
1866         out_le32(mbase + PECFG_BAR2HMPA, 0);
1867         out_le32(mbase + PECFG_BAR2LMPA, 0);
1868
1869         out_le32(mbase + PECFG_PIM01SAH, RES_TO_U32_HIGH(sa));
1870         out_le32(mbase + PECFG_PIM01SAL, RES_TO_U32_LOW(sa));
1871
1872         out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(ep_addr));
1873         out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(ep_addr));
1874     } else {
1875         /* Calculate window size */
1876         sa = (0xffffffffffffffffull << ilog2(size));
1877         if (res->flags & IORESOURCE_PREFETCH)
1878             sa |= PCI_BASE_ADDRESS_MEM_PREFETCH;
1879
1880         if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx") ||
1881             of_device_is_compatible(
1882                 port->node, "ibm,plb-pciex-476fpe") ||
1883             of_device_is_compatible(
1884                 port->node, "ibm,plb-pciex-476gtr"))
1885             sa |= PCI_BASE_ADDRESS_MEM_TYPE_64;
1886
1887         out_le32(mbase + PECFG_BAR0HMPA, RES_TO_U32_HIGH(sa));
1888         out_le32(mbase + PECFG_BAR0LMPA, RES_TO_U32_LOW(sa));
1889
1890         /* The setup of the split looks weird to me ... let's see
1891          * if it works
1892          */
1893         out_le32(mbase + PECFG_PIM0LAL, 0x00000000);
1894         out_le32(mbase + PECFG_PIM0LAH, 0x00000000);
1895         out_le32(mbase + PECFG_PIM1LAL, 0x00000000);
1896         out_le32(mbase + PECFG_PIM1LAH, 0x00000000);
1897         out_le32(mbase + PECFG_PIM01SAH, 0xffff0000);
1898         out_le32(mbase + PECFG_PIM01SAL, 0x00000000);
1899
1900         out_le32(mbase + PCI_BASE_ADDRESS_0, RES_TO_U32_LOW(res->start));
1901         out_le32(mbase + PCI_BASE_ADDRESS_1, RES_TO_U32_HIGH(res->start));
1902     }
1903
1904     /* Enable inbound mapping */
1905     out_le32(mbase + PECFG_PIMEN, 0x1);
1906
1907     /* Enable I/O, Mem, and Busmaster cycles */
1908     out_le16(mbase + PCI_COMMAND,
1909          in_le16(mbase + PCI_COMMAND) |
1910          PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
1911 }
1912
1913 static void __init ppc4xx_pciex_port_setup_hose(struct ppc4xx_pciex_port *port)
1914 {
1915     struct resource dma_window;
1916     struct pci_controller *hose = NULL;
1917     const int *bus_range;
1918     int primary = 0, busses;
1919     void __iomem *mbase = NULL, *cfg_data = NULL;
1920     const u32 *pval;
1921     u32 val;
1922
1923     /* Check if primary bridge */
1924     if (of_get_property(port->node, "primary", NULL))
1925         primary = 1;
1926
1927     /* Get bus range if any */
1928     bus_range = of_get_property(port->node, "bus-range", NULL);
1929
1930     /* Allocate the host controller data structure */
1931     hose = pcibios_alloc_controller(port->node);
1932     if (!hose)
1933         goto fail;
1934
1935     /* We stick the port number in "indirect_type" so the config space
1936      * ops can retrieve the port data structure easily
1937      */
1938     hose->indirect_type = port->index;
1939
1940     /* Get bus range */
1941     hose->first_busno = bus_range ? bus_range[0] : 0x0;
1942     hose->last_busno = bus_range ? bus_range[1] : 0xff;
1943
1944     /* Because of how big mapping the config space is (1M per bus), we
1945      * limit how many busses we support. In the long run, we could replace
1946      * that with something akin to kmap_atomic instead. We set aside 1 bus
1947      * for the host itself too.
1948      */
1949     busses = hose->last_busno - hose->first_busno; /* This is off by 1 */
1950     if (busses > MAX_PCIE_BUS_MAPPED) {
1951         busses = MAX_PCIE_BUS_MAPPED;
1952         hose->last_busno = hose->first_busno + busses;
1953     }
1954
1955     if (!port->endpoint) {
1956         /* Only map the external config space in cfg_data for
1957          * PCIe root-complexes. External space is 1M per bus
1958          */
1959         cfg_data = ioremap(port->cfg_space.start +
1960                    (hose->first_busno + 1) * 0x100000,
1961                    busses * 0x100000);
1962         if (cfg_data == NULL) {
1963             printk(KERN_ERR "%pOF: Can't map external config space !",
1964                    port->node);
1965             goto fail;
1966         }
1967         hose->cfg_data = cfg_data;
1968     }
1969
1970     /* Always map the host config space in cfg_addr.
1971      * Internal space is 4K
1972      */
1973     mbase = ioremap(port->cfg_space.start + 0x10000000, 0x1000);
1974     if (mbase == NULL) {
1975         printk(KERN_ERR "%pOF: Can't map internal config space !",
1976                port->node);
1977         goto fail;
1978     }
1979     hose->cfg_addr = mbase;
1980
1981     pr_debug("PCIE %pOF, bus %d..%d\n", port->node,
1982          hose->first_busno, hose->last_busno);
1983     pr_debug("     config space mapped at: root @0x%p, other @0x%p\n",
1984          hose->cfg_addr, hose->cfg_data);
1985
1986     /* Setup config space */
1987     hose->ops = &ppc4xx_pciex_pci_ops;
1988     port->hose = hose;
1989     mbase = (void __iomem *)hose->cfg_addr;
1990
1991     if (!port->endpoint) {
1992         /*
1993          * Set bus numbers on our root port
1994          */
1995         out_8(mbase + PCI_PRIMARY_BUS, hose->first_busno);
1996         out_8(mbase + PCI_SECONDARY_BUS, hose->first_busno + 1);
1997         out_8(mbase + PCI_SUBORDINATE_BUS, hose->last_busno);
1998     }
1999
2000     /*
2001      * OMRs are already reset, also disable PIMs
2002      */
2003     out_le32(mbase + PECFG_PIMEN, 0);
2004
2005     /* Parse outbound mapping resources */
2006     pci_process_bridge_OF_ranges(hose, port->node, primary);
2007
2008     /* Parse inbound mapping resources */
2009     if (ppc4xx_parse_dma_ranges(hose, mbase, &dma_window) != 0)
2010         goto fail;
2011
2012     /* Configure outbound ranges POMs */
2013     ppc4xx_configure_pciex_POMs(port, hose, mbase);
2014
2015     /* Configure inbound ranges PIMs */
2016     ppc4xx_configure_pciex_PIMs(port, hose, mbase, &dma_window);
2017
2018     /* The root complex doesn't show up if we don't set some vendor
2019      * and device IDs into it. The defaults below are the same bogus
2020      * one that the initial code in arch/ppc had. This can be
2021      * overwritten by setting the "vendor-id/device-id" properties
2022      * in the pciex node.
2023      */
2024
2025     /* Get the (optional) vendor-/device-id from the device-tree */
2026     pval = of_get_property(port->node, "vendor-id", NULL);
2027     if (pval) {
2028         val = *pval;
2029     } else {
2030         if (!port->endpoint)
2031             val = 0xaaa0 + port->index;
2032         else
2033             val = 0xeee0 + port->index;
2034     }
2035     out_le16(mbase + 0x200, val);
2036
2037     pval = of_get_property(port->node, "device-id", NULL);
2038     if (pval) {
2039         val = *pval;
2040     } else {
2041         if (!port->endpoint)
2042             val = 0xbed0 + port->index;
2043         else
2044             val = 0xfed0 + port->index;
2045     }
2046     out_le16(mbase + 0x202, val);
2047
2048     /* Enable Bus master, memory, and io space */
2049     if (of_device_is_compatible(port->node, "ibm,plb-pciex-460sx"))
2050         out_le16(mbase + 0x204, 0x7);
2051
2052     if (!port->endpoint) {
2053         /* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
2054         out_le32(mbase + 0x208, 0x06040001);
2055
2056         printk(KERN_INFO "PCIE%d: successfully set as root-complex\n",
2057                port->index);
2058     } else {
2059         /* Set Class Code to Processor/PPC */
2060         out_le32(mbase + 0x208, 0x0b200001);
2061
2062         printk(KERN_INFO "PCIE%d: successfully set as endpoint\n",
2063                port->index);
2064     }
2065
2066     return;
2067  fail:
2068     if (hose)
2069         pcibios_free_controller(hose);
2070     if (cfg_data)
2071         iounmap(cfg_data);
2072     if (mbase)
2073         iounmap(mbase);
2074 }
2075
2076 static void __init ppc4xx_probe_pciex_bridge(struct device_node *np)
2077 {
2078     struct ppc4xx_pciex_port *port;
2079     const u32 *pval;
2080     int portno;
2081     unsigned int dcrs;
2082
2083     /* First, proceed to core initialization as we assume there's
2084      * only one PCIe core in the system
2085      */
2086     if (ppc4xx_pciex_check_core_init(np))
2087         return;
2088
2089     /* Get the port number from the device-tree */
2090     pval = of_get_property(np, "port", NULL);
2091     if (pval == NULL) {
2092         printk(KERN_ERR "PCIE: Can't find port number for %pOF\n", np);
2093         return;
2094     }
2095     portno = *pval;
2096     if (portno >= ppc4xx_pciex_port_count) {
2097         printk(KERN_ERR "PCIE: port number out of range for %pOF\n",
2098                np);
2099         return;
2100     }
2101     port = &ppc4xx_pciex_ports[portno];
2102     port->index = portno;
2103
2104     /*
2105      * Check if device is enabled
2106      */
2107     if (!of_device_is_available(np)) {
2108         printk(KERN_INFO "PCIE%d: Port disabled via device-tree\n", port->index);
2109         return;
2110     }
2111
2112     port->node = of_node_get(np);
2113     if (ppc4xx_pciex_hwops->want_sdr) {
2114         pval = of_get_property(np, "sdr-base", NULL);
2115         if (pval == NULL) {
2116             printk(KERN_ERR "PCIE: missing sdr-base for %pOF\n",
2117                    np);
2118             return;
2119         }
2120         port->sdr_base = *pval;
2121     }
2122
2123     /* Check if device_type property is set to "pci" or "pci-endpoint".
2124      * Resulting from this setup this PCIe port will be configured
2125      * as root-complex or as endpoint.
2126      */
2127     if (of_node_is_type(port->node, "pci-endpoint")) {
2128         port->endpoint = 1;
2129     } else if (of_node_is_type(port->node, "pci")) {
2130         port->endpoint = 0;
2131     } else {
2132         printk(KERN_ERR "PCIE: missing or incorrect device_type for %pOF\n",
2133                np);
2134         return;
2135     }
2136
2137     /* Fetch config space registers address */
2138     if (of_address_to_resource(np, 0, &port->cfg_space)) {
2139         printk(KERN_ERR "%pOF: Can't get PCI-E config space !", np);
2140         return;
2141     }
2142     /* Fetch host bridge internal registers address */
2143     if (of_address_to_resource(np, 1, &port->utl_regs)) {
2144         printk(KERN_ERR "%pOF: Can't get UTL register base !", np);
2145         return;
2146     }
2147
2148     /* Map DCRs */
2149     dcrs = dcr_resource_start(np, 0);
2150     if (dcrs == 0) {
2151         printk(KERN_ERR "%pOF: Can't get DCR register base !", np);
2152         return;
2153     }
2154     port->dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
2155
2156     /* Initialize the port specific registers */
2157     if (ppc4xx_pciex_port_init(port)) {
2158         printk(KERN_WARNING "PCIE%d: Port init failed\n", port->index);
2159         return;
2160     }
2161
2162     /* Setup the linux hose data structure */
2163     ppc4xx_pciex_port_setup_hose(port);
2164 }
2165
2166 #endif /* CONFIG_PPC4xx_PCI_EXPRESS */
2167
2168 static int __init ppc4xx_pci_find_bridges(void)
2169 {
2170     struct device_node *np;
2171
2172     pci_add_flags(PCI_ENABLE_PROC_DOMAINS | PCI_COMPAT_DOMAIN_0);
2173
2174 #ifdef CONFIG_PPC4xx_PCI_EXPRESS
2175     for_each_compatible_node(np, NULL, "ibm,plb-pciex")
2176         ppc4xx_probe_pciex_bridge(np);
2177 #endif
2178     for_each_compatible_node(np, NULL, "ibm,plb-pcix")
2179         ppc4xx_probe_pcix_bridge(np);
2180     for_each_compatible_node(np, NULL, "ibm,plb-pci")
2181         ppc4xx_probe_pci_bridge(np);
2182
2183     return 0;
2184 }
2185 arch_initcall(ppc4xx_pci_find_bridges);
2186