platforms/4xx/gpio.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * PPC4xx gpio driver
0004  *
0005  * Copyright (c) 2008 Harris Corporation
0006  * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
0007  * Copyright (c) MontaVista Software, Inc. 2008.
0008  *
0009  * Author: Steve Falco <sfalco@harris.com>
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/init.h>
0014 #include <linux/spinlock.h>
0015 #include <linux/io.h>
0016 #include <linux/of.h>
0017 #include <linux/of_gpio.h>
0018 #include <linux/gpio/driver.h>
0019 #include <linux/types.h>
0020 #include <linux/slab.h>
0021
0022 #define GPIO_MASK(gpio)     (0x80000000 >> (gpio))
0023 #define GPIO_MASK2(gpio)    (0xc0000000 >> ((gpio) * 2))
0024
0025 /* Physical GPIO register layout */
0026 struct ppc4xx_gpio {
0027     __be32 or;
0028     __be32 tcr;
0029     __be32 osrl;
0030     __be32 osrh;
0031     __be32 tsrl;
0032     __be32 tsrh;
0033     __be32 odr;
0034     __be32 ir;
0035     __be32 rr1;
0036     __be32 rr2;
0037     __be32 rr3;
0038     __be32 reserved1;
0039     __be32 isr1l;
0040     __be32 isr1h;
0041     __be32 isr2l;
0042     __be32 isr2h;
0043     __be32 isr3l;
0044     __be32 isr3h;
0045 };
0046
0047 struct ppc4xx_gpio_chip {
0048     struct of_mm_gpio_chip mm_gc;
0049     spinlock_t lock;
0050 };
0051
0052 /*
0053  * GPIO LIB API implementation for GPIOs
0054  *
0055  * There are a maximum of 32 gpios in each gpio controller.
0056  */
0057
0058 static int ppc4xx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
0059 {
0060     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0061     struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
0062
0063     return !!(in_be32(&regs->ir) & GPIO_MASK(gpio));
0064 }
0065
0066 static inline void
0067 __ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
0068 {
0069     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0070     struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
0071
0072     if (val)
0073         setbits32(&regs->or, GPIO_MASK(gpio));
0074     else
0075         clrbits32(&regs->or, GPIO_MASK(gpio));
0076 }
0077
0078 static void
0079 ppc4xx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
0080 {
0081     struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
0082     unsigned long flags;
0083
0084     spin_lock_irqsave(&chip->lock, flags);
0085
0086     __ppc4xx_gpio_set(gc, gpio, val);
0087
0088     spin_unlock_irqrestore(&chip->lock, flags);
0089
0090     pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
0091 }
0092
0093 static int ppc4xx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
0094 {
0095     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0096     struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
0097     struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
0098     unsigned long flags;
0099
0100     spin_lock_irqsave(&chip->lock, flags);
0101
0102     /* Disable open-drain function */
0103     clrbits32(&regs->odr, GPIO_MASK(gpio));
0104
0105     /* Float the pin */
0106     clrbits32(&regs->tcr, GPIO_MASK(gpio));
0107
0108     /* Bits 0-15 use TSRL/OSRL, bits 16-31 use TSRH/OSRH */
0109     if (gpio < 16) {
0110         clrbits32(&regs->osrl, GPIO_MASK2(gpio));
0111         clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
0112     } else {
0113         clrbits32(&regs->osrh, GPIO_MASK2(gpio));
0114         clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
0115     }
0116
0117     spin_unlock_irqrestore(&chip->lock, flags);
0118
0119     return 0;
0120 }
0121
0122 static int
0123 ppc4xx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
0124 {
0125     struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
0126     struct ppc4xx_gpio_chip *chip = gpiochip_get_data(gc);
0127     struct ppc4xx_gpio __iomem *regs = mm_gc->regs;
0128     unsigned long flags;
0129
0130     spin_lock_irqsave(&chip->lock, flags);
0131
0132     /* First set initial value */
0133     __ppc4xx_gpio_set(gc, gpio, val);
0134
0135     /* Disable open-drain function */
0136     clrbits32(&regs->odr, GPIO_MASK(gpio));
0137
0138     /* Drive the pin */
0139     setbits32(&regs->tcr, GPIO_MASK(gpio));
0140
0141     /* Bits 0-15 use TSRL, bits 16-31 use TSRH */
0142     if (gpio < 16) {
0143         clrbits32(&regs->osrl, GPIO_MASK2(gpio));
0144         clrbits32(&regs->tsrl, GPIO_MASK2(gpio));
0145     } else {
0146         clrbits32(&regs->osrh, GPIO_MASK2(gpio));
0147         clrbits32(&regs->tsrh, GPIO_MASK2(gpio));
0148     }
0149
0150     spin_unlock_irqrestore(&chip->lock, flags);
0151
0152     pr_debug("%s: gpio: %d val: %d\n", __func__, gpio, val);
0153
0154     return 0;
0155 }
0156
0157 static int __init ppc4xx_add_gpiochips(void)
0158 {
0159     struct device_node *np;
0160
0161     for_each_compatible_node(np, NULL, "ibm,ppc4xx-gpio") {
0162         int ret;
0163         struct ppc4xx_gpio_chip *ppc4xx_gc;
0164         struct of_mm_gpio_chip *mm_gc;
0165         struct gpio_chip *gc;
0166
0167         ppc4xx_gc = kzalloc(sizeof(*ppc4xx_gc), GFP_KERNEL);
0168         if (!ppc4xx_gc) {
0169             ret = -ENOMEM;
0170             goto err;
0171         }
0172
0173         spin_lock_init(&ppc4xx_gc->lock);
0174
0175         mm_gc = &ppc4xx_gc->mm_gc;
0176         gc = &mm_gc->gc;
0177
0178         gc->ngpio = 32;
0179         gc->direction_input = ppc4xx_gpio_dir_in;
0180         gc->direction_output = ppc4xx_gpio_dir_out;
0181         gc->get = ppc4xx_gpio_get;
0182         gc->set = ppc4xx_gpio_set;
0183
0184         ret = of_mm_gpiochip_add_data(np, mm_gc, ppc4xx_gc);
0185         if (ret)
0186             goto err;
0187         continue;
0188 err:
0189         pr_err("%pOF: registration failed with status %d\n", np, ret);
0190         kfree(ppc4xx_gc);
0191         /* try others anyway */
0192     }
0193     return 0;
0194 }
0195 arch_initcall(ppc4xx_add_gpiochips);