platforms/44x/machine_check.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  */
0004
0005 #include <linux/kernel.h>
0006 #include <linux/printk.h>
0007 #include <linux/ptrace.h>
0008
0009 #include <asm/reg.h>
0010 #include <asm/cacheflush.h>
0011
0012 int machine_check_440A(struct pt_regs *regs)
0013 {
0014     unsigned long reason = regs->esr;
0015
0016     printk("Machine check in kernel mode.\n");
0017     if (reason & ESR_IMCP){
0018         printk("Instruction Synchronous Machine Check exception\n");
0019         mtspr(SPRN_ESR, reason & ~ESR_IMCP);
0020     }
0021     else {
0022         u32 mcsr = mfspr(SPRN_MCSR);
0023         if (mcsr & MCSR_IB)
0024             printk("Instruction Read PLB Error\n");
0025         if (mcsr & MCSR_DRB)
0026             printk("Data Read PLB Error\n");
0027         if (mcsr & MCSR_DWB)
0028             printk("Data Write PLB Error\n");
0029         if (mcsr & MCSR_TLBP)
0030             printk("TLB Parity Error\n");
0031         if (mcsr & MCSR_ICP){
0032             flush_instruction_cache();
0033             printk("I-Cache Parity Error\n");
0034         }
0035         if (mcsr & MCSR_DCSP)
0036             printk("D-Cache Search Parity Error\n");
0037         if (mcsr & MCSR_DCFP)
0038             printk("D-Cache Flush Parity Error\n");
0039         if (mcsr & MCSR_IMPE)
0040             printk("Machine Check exception is imprecise\n");
0041
0042         /* Clear MCSR */
0043         mtspr(SPRN_MCSR, mcsr);
0044     }
0045     return 0;
0046 }
0047
0048 #ifdef CONFIG_PPC_47x
0049 int machine_check_47x(struct pt_regs *regs)
0050 {
0051     unsigned long reason = regs->esr;
0052     u32 mcsr;
0053
0054     printk(KERN_ERR "Machine check in kernel mode.\n");
0055     if (reason & ESR_IMCP) {
0056         printk(KERN_ERR "Instruction Synchronous Machine Check exception\n");
0057         mtspr(SPRN_ESR, reason & ~ESR_IMCP);
0058         return 0;
0059     }
0060     mcsr = mfspr(SPRN_MCSR);
0061     if (mcsr & MCSR_IB)
0062         printk(KERN_ERR "Instruction Read PLB Error\n");
0063     if (mcsr & MCSR_DRB)
0064         printk(KERN_ERR "Data Read PLB Error\n");
0065     if (mcsr & MCSR_DWB)
0066         printk(KERN_ERR "Data Write PLB Error\n");
0067     if (mcsr & MCSR_TLBP)
0068         printk(KERN_ERR "TLB Parity Error\n");
0069     if (mcsr & MCSR_ICP) {
0070         flush_instruction_cache();
0071         printk(KERN_ERR "I-Cache Parity Error\n");
0072     }
0073     if (mcsr & MCSR_DCSP)
0074         printk(KERN_ERR "D-Cache Search Parity Error\n");
0075     if (mcsr & PPC47x_MCSR_GPR)
0076         printk(KERN_ERR "GPR Parity Error\n");
0077     if (mcsr & PPC47x_MCSR_FPR)
0078         printk(KERN_ERR "FPR Parity Error\n");
0079     if (mcsr & PPC47x_MCSR_IPR)
0080         printk(KERN_ERR "Machine Check exception is imprecise\n");
0081
0082     /* Clear MCSR */
0083     mtspr(SPRN_MCSR, mcsr);
0084
0085     return 0;
0086 }
0087 #endif /* CONFIG_PPC_47x */