platforms/44x/fsp2.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * FSP-2 board specific routines
0004  *
0005  * Based on earlier code:
0006  *    Matt Porter <mporter@kernel.crashing.org>
0007  *    Copyright 2002-2005 MontaVista Software Inc.
0008  *
0009  *    Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
0010  *    Copyright (c) 2003-2005 Zultys Technologies
0011  *
0012  *    Rewritten and ported to the merged powerpc tree:
0013  *    Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
0014  */
0015
0016 #include <linux/init.h>
0017 #include <linux/of_fdt.h>
0018 #include <linux/of_platform.h>
0019 #include <linux/rtc.h>
0020
0021 #include <asm/machdep.h>
0022 #include <asm/udbg.h>
0023 #include <asm/time.h>
0024 #include <asm/uic.h>
0025 #include <asm/ppc4xx.h>
0026 #include <asm/dcr.h>
0027 #include <linux/interrupt.h>
0028 #include <linux/of_irq.h>
0029 #include "fsp2.h"
0030
0031 #define FSP2_BUS_ERR    "ibm,bus-error-irq"
0032 #define FSP2_CMU_ERR    "ibm,cmu-error-irq"
0033 #define FSP2_CONF_ERR   "ibm,conf-error-irq"
0034 #define FSP2_OPBD_ERR   "ibm,opbd-error-irq"
0035 #define FSP2_MCUE   "ibm,mc-ue-irq"
0036 #define FSP2_RST_WRN    "ibm,reset-warning-irq"
0037
0038 static __initdata struct of_device_id fsp2_of_bus[] = {
0039     { .compatible = "ibm,plb4", },
0040     { .compatible = "ibm,plb6", },
0041     { .compatible = "ibm,opb", },
0042     {},
0043 };
0044
0045 static void l2regs(void)
0046 {
0047     pr_err("L2 Controller:\n");
0048     pr_err("MCK:      0x%08x\n", mfl2(L2MCK));
0049     pr_err("INT:      0x%08x\n", mfl2(L2INT));
0050     pr_err("PLBSTAT0: 0x%08x\n", mfl2(L2PLBSTAT0));
0051     pr_err("PLBSTAT1: 0x%08x\n", mfl2(L2PLBSTAT1));
0052     pr_err("ARRSTAT0: 0x%08x\n", mfl2(L2ARRSTAT0));
0053     pr_err("ARRSTAT1: 0x%08x\n", mfl2(L2ARRSTAT1));
0054     pr_err("ARRSTAT2: 0x%08x\n", mfl2(L2ARRSTAT2));
0055     pr_err("CPUSTAT:  0x%08x\n", mfl2(L2CPUSTAT));
0056     pr_err("RACSTAT0: 0x%08x\n", mfl2(L2RACSTAT0));
0057     pr_err("WACSTAT0: 0x%08x\n", mfl2(L2WACSTAT0));
0058     pr_err("WACSTAT1: 0x%08x\n", mfl2(L2WACSTAT1));
0059     pr_err("WACSTAT2: 0x%08x\n", mfl2(L2WACSTAT2));
0060     pr_err("WDFSTAT:  0x%08x\n", mfl2(L2WDFSTAT));
0061     pr_err("LOG0:     0x%08x\n", mfl2(L2LOG0));
0062     pr_err("LOG1:     0x%08x\n", mfl2(L2LOG1));
0063     pr_err("LOG2:     0x%08x\n", mfl2(L2LOG2));
0064     pr_err("LOG3:     0x%08x\n", mfl2(L2LOG3));
0065     pr_err("LOG4:     0x%08x\n", mfl2(L2LOG4));
0066     pr_err("LOG5:     0x%08x\n", mfl2(L2LOG5));
0067 }
0068
0069 static void show_plbopb_regs(u32 base, int num)
0070 {
0071     pr_err("\nPLBOPB Bridge %d:\n", num);
0072     pr_err("GESR0: 0x%08x\n", mfdcr(base + PLB4OPB_GESR0));
0073     pr_err("GESR1: 0x%08x\n", mfdcr(base + PLB4OPB_GESR1));
0074     pr_err("GESR2: 0x%08x\n", mfdcr(base + PLB4OPB_GESR2));
0075     pr_err("GEARU: 0x%08x\n", mfdcr(base + PLB4OPB_GEARU));
0076     pr_err("GEAR:  0x%08x\n", mfdcr(base + PLB4OPB_GEAR));
0077 }
0078
0079 static irqreturn_t bus_err_handler(int irq, void *data)
0080 {
0081     pr_err("Bus Error\n");
0082
0083     l2regs();
0084
0085     pr_err("\nPLB6 Controller:\n");
0086     pr_err("BC_SHD: 0x%08x\n", mfdcr(DCRN_PLB6_SHD));
0087     pr_err("BC_ERR: 0x%08x\n", mfdcr(DCRN_PLB6_ERR));
0088
0089     pr_err("\nPLB6-to-PLB4 Bridge:\n");
0090     pr_err("ESR:  0x%08x\n", mfdcr(DCRN_PLB6PLB4_ESR));
0091     pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARH));
0092     pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB6PLB4_EARL));
0093
0094     pr_err("\nPLB4-to-PLB6 Bridge:\n");
0095     pr_err("ESR:  0x%08x\n", mfdcr(DCRN_PLB4PLB6_ESR));
0096     pr_err("EARH: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARH));
0097     pr_err("EARL: 0x%08x\n", mfdcr(DCRN_PLB4PLB6_EARL));
0098
0099     pr_err("\nPLB6-to-MCIF Bridge:\n");
0100     pr_err("BESR0: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR0));
0101     pr_err("BESR1: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BESR1));
0102     pr_err("BEARH: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARH));
0103     pr_err("BEARL: 0x%08x\n", mfdcr(DCRN_PLB6MCIF_BEARL));
0104
0105     pr_err("\nPLB4 Arbiter:\n");
0106     pr_err("P0ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRH));
0107     pr_err("P0ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P0ESRL));
0108     pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));
0109     pr_err("P0EARH 0x%08x\n", mfdcr(DCRN_PLB4_P0EARH));
0110     pr_err("P1ESRH 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRH));
0111     pr_err("P1ESRL 0x%08x\n", mfdcr(DCRN_PLB4_P1ESRL));
0112     pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));
0113     pr_err("P1EARH 0x%08x\n", mfdcr(DCRN_PLB4_P1EARH));
0114
0115     show_plbopb_regs(DCRN_PLB4OPB0_BASE, 0);
0116     show_plbopb_regs(DCRN_PLB4OPB1_BASE, 1);
0117     show_plbopb_regs(DCRN_PLB4OPB2_BASE, 2);
0118     show_plbopb_regs(DCRN_PLB4OPB3_BASE, 3);
0119
0120     pr_err("\nPLB4-to-AHB Bridge:\n");
0121     pr_err("ESR:   0x%08x\n", mfdcr(DCRN_PLB4AHB_ESR));
0122     pr_err("SEUAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SEUAR));
0123     pr_err("SELAR: 0x%08x\n", mfdcr(DCRN_PLB4AHB_SELAR));
0124
0125     pr_err("\nAHB-to-PLB4 Bridge:\n");
0126     pr_err("\nESR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_ESR));
0127     pr_err("\nEAR: 0x%08x\n", mfdcr(DCRN_AHBPLB4_EAR));
0128     panic("Bus Error\n");
0129 }
0130
0131 static irqreturn_t cmu_err_handler(int irq, void *data) {
0132     pr_err("CMU Error\n");
0133     pr_err("FIR0: 0x%08x\n", mfcmu(CMUN_FIR0));
0134     panic("CMU Error\n");
0135 }
0136
0137 static irqreturn_t conf_err_handler(int irq, void *data) {
0138     pr_err("Configuration Logic Error\n");
0139     pr_err("CONF_FIR: 0x%08x\n", mfdcr(DCRN_CONF_FIR_RWC));
0140     pr_err("RPERR0:   0x%08x\n", mfdcr(DCRN_CONF_RPERR0));
0141     pr_err("RPERR1:   0x%08x\n", mfdcr(DCRN_CONF_RPERR1));
0142     panic("Configuration Logic Error\n");
0143 }
0144
0145 static irqreturn_t opbd_err_handler(int irq, void *data) {
0146     panic("OPBD Error\n");
0147 }
0148
0149 static irqreturn_t mcue_handler(int irq, void *data) {
0150     pr_err("DDR: Uncorrectable Error\n");
0151     pr_err("MCSTAT:            0x%08x\n",
0152         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCSTAT));
0153     pr_err("MCOPT1:            0x%08x\n",
0154         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT1));
0155     pr_err("MCOPT2:            0x%08x\n",
0156         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_MCOPT2));
0157     pr_err("PHYSTAT:           0x%08x\n",
0158         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_PHYSTAT));
0159     pr_err("CFGR0:             0x%08x\n",
0160         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR0));
0161     pr_err("CFGR1:             0x%08x\n",
0162         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR1));
0163     pr_err("CFGR2:             0x%08x\n",
0164         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR2));
0165     pr_err("CFGR3:             0x%08x\n",
0166         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_CFGR3));
0167     pr_err("SCRUB_CNTL:        0x%08x\n",
0168         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_SCRUB_CNTL));
0169     pr_err("ECCERR_PORT0:      0x%08x\n",
0170         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_PORT0));
0171     pr_err("ECCERR_ADDR_PORT0: 0x%08x\n",
0172         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_ADDR_PORT0));
0173     pr_err("ECCERR_CNT_PORT0:  0x%08x\n",
0174         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECCERR_COUNT_PORT0));
0175     pr_err("ECC_CHECK_PORT0:   0x%08x\n",
0176         mfdcr(DCRN_DDR34_BASE + DCRN_DDR34_ECC_CHECK_PORT0));
0177     pr_err("MCER0:            0x%08x\n",
0178         mfdcr(DCRN_CW_BASE + DCRN_CW_MCER0));
0179     pr_err("MCER1:            0x%08x\n",
0180         mfdcr(DCRN_CW_BASE + DCRN_CW_MCER1));
0181     pr_err("BESR:             0x%08x\n",
0182         mfdcr(DCRN_PLB6MCIF_BESR0));
0183     pr_err("BEARL:            0x%08x\n",
0184         mfdcr(DCRN_PLB6MCIF_BEARL));
0185     pr_err("BEARH:            0x%08x\n",
0186         mfdcr(DCRN_PLB6MCIF_BEARH));
0187     panic("DDR: Uncorrectable Error\n");
0188 }
0189
0190 static irqreturn_t rst_wrn_handler(int irq, void *data) {
0191     u32 crcs = mfcmu(CMUN_CRCS);
0192     switch (crcs & CRCS_STAT_MASK) {
0193     case CRCS_STAT_CHIP_RST_B:
0194         panic("Received chassis-initiated reset request");
0195     default:
0196         panic("Unknown external reset: CRCS=0x%x", crcs);
0197     }
0198 }
0199
0200 static void __init node_irq_request(const char *compat, irq_handler_t errirq_handler)
0201 {
0202     struct device_node *np;
0203     unsigned int irq;
0204     int32_t rc;
0205
0206     for_each_compatible_node(np, NULL, compat) {
0207         irq = irq_of_parse_and_map(np, 0);
0208         if (irq == NO_IRQ) {
0209             pr_err("device tree node %pOFn is missing a interrupt",
0210                   np);
0211             of_node_put(np);
0212             return;
0213         }
0214
0215         rc = request_irq(irq, errirq_handler, 0, np->name, np);
0216         if (rc) {
0217             pr_err("fsp_of_probe: request_irq failed: np=%pOF rc=%d",
0218                   np, rc);
0219             of_node_put(np);
0220             return;
0221         }
0222     }
0223 }
0224
0225 static void __init critical_irq_setup(void)
0226 {
0227     node_irq_request(FSP2_CMU_ERR, cmu_err_handler);
0228     node_irq_request(FSP2_BUS_ERR, bus_err_handler);
0229     node_irq_request(FSP2_CONF_ERR, conf_err_handler);
0230     node_irq_request(FSP2_OPBD_ERR, opbd_err_handler);
0231     node_irq_request(FSP2_MCUE, mcue_handler);
0232     node_irq_request(FSP2_RST_WRN, rst_wrn_handler);
0233 }
0234
0235 static int __init fsp2_device_probe(void)
0236 {
0237     of_platform_bus_probe(NULL, fsp2_of_bus, NULL);
0238     return 0;
0239 }
0240 machine_device_initcall(fsp2, fsp2_device_probe);
0241
0242 static int __init fsp2_probe(void)
0243 {
0244     u32 val;
0245     unsigned long root = of_get_flat_dt_root();
0246
0247     if (!of_flat_dt_is_compatible(root, "ibm,fsp2"))
0248         return 0;
0249
0250     /* Clear BC_ERR and mask snoopable request plb errors. */
0251     val = mfdcr(DCRN_PLB6_CR0);
0252     val |= 0x20000000;
0253     mtdcr(DCRN_PLB6_BASE, val);
0254     mtdcr(DCRN_PLB6_HD, 0xffff0000);
0255     mtdcr(DCRN_PLB6_SHD, 0xffff0000);
0256
0257     /* TVSENSE reset is blocked (clock gated) by the POR default of the TVS
0258      * sleep config bit. As a consequence, TVSENSE will provide erratic
0259      * sensor values, which may result in spurious (parity) errors
0260      * recorded in the CMU FIR and leading to erroneous interrupt requests
0261      * once the CMU interrupt is unmasked.
0262      */
0263
0264     /* 1. set TVS1[UNDOZE] */
0265     val = mfcmu(CMUN_TVS1);
0266     val |= 0x4;
0267     mtcmu(CMUN_TVS1, val);
0268
0269     /* 2. clear FIR[TVS] and FIR[TVSPAR] */
0270     val = mfcmu(CMUN_FIR0);
0271     val |= 0x30000000;
0272     mtcmu(CMUN_FIR0, val);
0273
0274     /* L2 machine checks */
0275     mtl2(L2PLBMCKEN0, 0xffffffff);
0276     mtl2(L2PLBMCKEN1, 0x0000ffff);
0277     mtl2(L2ARRMCKEN0, 0xffffffff);
0278     mtl2(L2ARRMCKEN1, 0xffffffff);
0279     mtl2(L2ARRMCKEN2, 0xfffff000);
0280     mtl2(L2CPUMCKEN,  0xffffffff);
0281     mtl2(L2RACMCKEN0, 0xffffffff);
0282     mtl2(L2WACMCKEN0, 0xffffffff);
0283     mtl2(L2WACMCKEN1, 0xffffffff);
0284     mtl2(L2WACMCKEN2, 0xffffffff);
0285     mtl2(L2WDFMCKEN,  0xffffffff);
0286
0287     /* L2 interrupts */
0288     mtl2(L2PLBINTEN1, 0xffff0000);
0289
0290     /*
0291      * At a global level, enable all L2 machine checks and interrupts
0292      * reported by the L2 subsystems, except for the external machine check
0293      * input (UIC0.1).
0294      */
0295     mtl2(L2MCKEN, 0x000007ff);
0296     mtl2(L2INTEN, 0x000004ff);
0297
0298     /* Enable FSP-2 configuration logic parity errors */
0299     mtdcr(DCRN_CONF_EIR_RS, 0x80000000);
0300     return 1;
0301 }
0302
0303 static void __init fsp2_irq_init(void)
0304 {
0305     uic_init_tree();
0306     critical_irq_setup();
0307 }
0308
0309 define_machine(fsp2) {
0310     .name           = "FSP-2",
0311     .probe          = fsp2_probe,
0312     .progress       = udbg_progress,
0313     .init_IRQ       = fsp2_irq_init,
0314     .get_irq        = uic_get_irq,
0315     .restart        = ppc4xx_reset_system,
0316     .calibrate_decr     = generic_calibrate_decr,
0317 };