powerpc/perf/power9-events-list.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Performance counter support for POWER9 processors.
0004  *
0005  * Copyright 2016 Madhavan Srinivasan, IBM Corporation.
0006  */
0007
0008 /*
0009  * Power9 event codes.
0010  */
0011 EVENT(PM_CYC,                   0x0001e)
0012 EVENT(PM_ICT_NOSLOT_CYC,            0x100f8)
0013 EVENT(PM_CMPLU_STALL,               0x1e054)
0014 EVENT(PM_INST_CMPL,             0x00002)
0015 EVENT(PM_BR_CMPL,               0x4d05e)
0016 EVENT(PM_BR_MPRED_CMPL,             0x400f6)
0017
0018 /* All L1 D cache load references counted at finish, gated by reject */
0019 EVENT(PM_LD_REF_L1,             0x100fc)
0020 /* Load Missed L1 */
0021 EVENT(PM_LD_MISS_L1_FIN,            0x2c04e)
0022 EVENT(PM_LD_MISS_L1,                0x3e054)
0023 /* Alternate event code for PM_LD_MISS_L1 */
0024 EVENT(PM_LD_MISS_L1_ALT,            0x400f0)
0025 /* Store Missed L1 */
0026 EVENT(PM_ST_MISS_L1,                0x300f0)
0027 /* L1 cache data prefetches */
0028 EVENT(PM_L1_PREF,               0x20054)
0029 /* Instruction fetches from L1 */
0030 EVENT(PM_INST_FROM_L1,              0x04080)
0031 /* Demand iCache Miss */
0032 EVENT(PM_L1_ICACHE_MISS,            0x200fd)
0033 /* Instruction Demand sectors wriittent into IL1 */
0034 EVENT(PM_L1_DEMAND_WRITE,           0x0408c)
0035 /* Instruction prefetch written into IL1 */
0036 EVENT(PM_IC_PREF_WRITE,             0x0488c)
0037 /* The data cache was reloaded from local core's L3 due to a demand load */
0038 EVENT(PM_DATA_FROM_L3,              0x4c042)
0039 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
0040 EVENT(PM_DATA_FROM_L3MISS,          0x300fe)
0041 /* All successful D-side store dispatches for this thread */
0042 EVENT(PM_L2_ST,                 0x16880)
0043 /* All successful D-side store dispatches for this thread that were L2 Miss */
0044 EVENT(PM_L2_ST_MISS,                0x26880)
0045 /* Total HW L3 prefetches(Load+store) */
0046 EVENT(PM_L3_PREF_ALL,               0x4e052)
0047 /* Data PTEG reload */
0048 EVENT(PM_DTLB_MISS,             0x300fc)
0049 /* ITLB Reloaded */
0050 EVENT(PM_ITLB_MISS,             0x400fc)
0051 /* Run_Instructions */
0052 EVENT(PM_RUN_INST_CMPL,             0x500fa)
0053 /* Alternate event code for PM_RUN_INST_CMPL */
0054 EVENT(PM_RUN_INST_CMPL_ALT,         0x400fa)
0055 /* Run_cycles */
0056 EVENT(PM_RUN_CYC,               0x600f4)
0057 /* Alternate event code for Run_cycles */
0058 EVENT(PM_RUN_CYC_ALT,               0x200f4)
0059 /* Instruction Dispatched */
0060 EVENT(PM_INST_DISP,             0x200f2)
0061 EVENT(PM_INST_DISP_ALT,             0x300f2)
0062 /* Branch event that are not strongly biased */
0063 EVENT(PM_BR_2PATH,              0x20036)
0064 /* ALternate branch event that are not strongly biased */
0065 EVENT(PM_BR_2PATH_ALT,              0x40036)
0066
0067 /* Blacklisted events */
0068 EVENT(PM_MRK_ST_DONE_L2,            0x10134)
0069 EVENT(PM_RADIX_PWC_L1_HIT,          0x1f056)
0070 EVENT(PM_FLOP_CMPL,             0x100f4)
0071 EVENT(PM_MRK_NTF_FIN,               0x20112)
0072 EVENT(PM_RADIX_PWC_L2_HIT,          0x2d024)
0073 EVENT(PM_IFETCH_THROTTLE,           0x3405e)
0074 EVENT(PM_MRK_L2_TM_ST_ABORT_SISTER,     0x3e15c)
0075 EVENT(PM_RADIX_PWC_L3_HIT,          0x3f056)
0076 EVENT(PM_RUN_CYC_SMT2_MODE,         0x3006c)
0077 EVENT(PM_TM_TX_PASS_RUN_INST,           0x4e014)
0078 EVENT(PM_DISP_HELD_SYNC_HOLD,           0x4003c)
0079 EVENT(PM_DTLB_MISS_16G,             0x1c058)
0080 EVENT(PM_DERAT_MISS_2M,             0x1c05a)
0081 EVENT(PM_DTLB_MISS_2M,              0x1c05c)
0082 EVENT(PM_MRK_DTLB_MISS_1G,          0x1d15c)
0083 EVENT(PM_DTLB_MISS_4K,              0x2c056)
0084 EVENT(PM_DERAT_MISS_1G,             0x2c05a)
0085 EVENT(PM_MRK_DERAT_MISS_2M,         0x2d152)
0086 EVENT(PM_MRK_DTLB_MISS_4K,          0x2d156)
0087 EVENT(PM_MRK_DTLB_MISS_16G,         0x2d15e)
0088 EVENT(PM_DTLB_MISS_64K,             0x3c056)
0089 EVENT(PM_MRK_DERAT_MISS_1G,         0x3d152)
0090 EVENT(PM_MRK_DTLB_MISS_64K,         0x3d156)
0091 EVENT(PM_DTLB_MISS_16M,             0x4c056)
0092 EVENT(PM_DTLB_MISS_1G,              0x4c05a)
0093 EVENT(PM_MRK_DTLB_MISS_16M,         0x4c15e)
0094
0095 /*
0096  * Memory Access Events
0097  *
0098  * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
0099  * To enable capturing of memory profiling, these MMCRA bits
0100  * needs to be programmed and corresponding raw event format
0101  * encoding.
0102  *
0103  * MMCRA bits encoding needed are
0104  *     SM (Sampling Mode)
0105  *     EM (Eligibility for Random Sampling)
0106  *     TECE (Threshold Event Counter Event)
0107  *     TS (Threshold Start Event)
0108  *     TE (Threshold End Event)
0109  *
0110  * Corresponding Raw Encoding bits:
0111  *     sample [EM,SM]
0112  *     thresh_sel (TECE)
0113  *     thresh start (TS)
0114  *     thresh end (TE)
0115  */
0116 EVENT(MEM_LOADS,                0x34340401e0)
0117 EVENT(MEM_STORES,               0x343c0401e0)