powerpc/perf/power8-events-list.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Performance counter support for POWER8 processors.
0004  *
0005  * Copyright 2014 Sukadev Bhattiprolu, IBM Corporation.
0006  */
0007
0008 /*
0009  * Power8 event codes.
0010  */
0011 EVENT(PM_CYC,                   0x0001e)
0012 EVENT(PM_GCT_NOSLOT_CYC,            0x100f8)
0013 EVENT(PM_CMPLU_STALL,               0x4000a)
0014 EVENT(PM_INST_CMPL,             0x00002)
0015 EVENT(PM_BRU_FIN,               0x10068)
0016 EVENT(PM_BR_MPRED_CMPL,             0x400f6)
0017
0018 /* All L1 D cache load references counted at finish, gated by reject */
0019 EVENT(PM_LD_REF_L1,             0x100ee)
0020 /* Load Missed L1 */
0021 EVENT(PM_LD_MISS_L1,                0x3e054)
0022 /* Store Missed L1 */
0023 EVENT(PM_ST_MISS_L1,                0x300f0)
0024 /* L1 cache data prefetches */
0025 EVENT(PM_L1_PREF,               0x0d8b8)
0026 /* Instruction fetches from L1 */
0027 EVENT(PM_INST_FROM_L1,              0x04080)
0028 /* Demand iCache Miss */
0029 EVENT(PM_L1_ICACHE_MISS,            0x200fd)
0030 /* Instruction Demand sectors wriittent into IL1 */
0031 EVENT(PM_L1_DEMAND_WRITE,           0x0408c)
0032 /* Instruction prefetch written into IL1 */
0033 EVENT(PM_IC_PREF_WRITE,             0x0408e)
0034 /* The data cache was reloaded from local core's L3 due to a demand load */
0035 EVENT(PM_DATA_FROM_L3,              0x4c042)
0036 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
0037 EVENT(PM_DATA_FROM_L3MISS,          0x300fe)
0038 /* All successful D-side store dispatches for this thread */
0039 EVENT(PM_L2_ST,                 0x17080)
0040 /* All successful D-side store dispatches for this thread that were L2 Miss */
0041 EVENT(PM_L2_ST_MISS,                0x17082)
0042 /* Total HW L3 prefetches(Load+store) */
0043 EVENT(PM_L3_PREF_ALL,               0x4e052)
0044 /* Data PTEG reload */
0045 EVENT(PM_DTLB_MISS,             0x300fc)
0046 /* ITLB Reloaded */
0047 EVENT(PM_ITLB_MISS,             0x400fc)
0048 /* Run_Instructions */
0049 EVENT(PM_RUN_INST_CMPL,             0x500fa)
0050 /* Alternate event code for PM_RUN_INST_CMPL */
0051 EVENT(PM_RUN_INST_CMPL_ALT,         0x400fa)
0052 /* Run_cycles */
0053 EVENT(PM_RUN_CYC,               0x600f4)
0054 /* Alternate event code for Run_cycles */
0055 EVENT(PM_RUN_CYC_ALT,               0x200f4)
0056 /* Marked store completed */
0057 EVENT(PM_MRK_ST_CMPL,               0x10134)
0058 /* Alternate event code for Marked store completed */
0059 EVENT(PM_MRK_ST_CMPL_ALT,           0x301e2)
0060 /* Marked two path branch */
0061 EVENT(PM_BR_MRK_2PATH,              0x10138)
0062 /* Alternate event code for PM_BR_MRK_2PATH */
0063 EVENT(PM_BR_MRK_2PATH_ALT,          0x40138)
0064 /* L3 castouts in Mepf state */
0065 EVENT(PM_L3_CO_MEPF,                0x18082)
0066 /* Alternate event code for PM_L3_CO_MEPF */
0067 EVENT(PM_L3_CO_MEPF_ALT,            0x3e05e)
0068 /* Data cache was reloaded from a location other than L2 due to a marked load */
0069 EVENT(PM_MRK_DATA_FROM_L2MISS,          0x1d14e)
0070 /* Alternate event code for PM_MRK_DATA_FROM_L2MISS */
0071 EVENT(PM_MRK_DATA_FROM_L2MISS_ALT,      0x401e8)
0072 /* Alternate event code for  PM_CMPLU_STALL */
0073 EVENT(PM_CMPLU_STALL_ALT,           0x1e054)
0074 /* Two path branch */
0075 EVENT(PM_BR_2PATH,              0x20036)
0076 /* Alternate event code for PM_BR_2PATH */
0077 EVENT(PM_BR_2PATH_ALT,              0x40036)
0078 /* # PPC Dispatched */
0079 EVENT(PM_INST_DISP,             0x200f2)
0080 /* Alternate event code for PM_INST_DISP */
0081 EVENT(PM_INST_DISP_ALT,             0x300f2)
0082 /* Marked filter Match */
0083 EVENT(PM_MRK_FILT_MATCH,            0x2013c)
0084 /* Alternate event code for PM_MRK_FILT_MATCH */
0085 EVENT(PM_MRK_FILT_MATCH_ALT,            0x3012e)
0086 /* Alternate event code for PM_LD_MISS_L1 */
0087 EVENT(PM_LD_MISS_L1_ALT,            0x400f0)
0088 /*
0089  * Memory Access Event -- mem_access
0090  * Primary PMU event used here is PM_MRK_INST_CMPL, along with
0091  * Random Load/Store Facility Sampling (RIS) in Random sampling mode (MMCRA[SM]).
0092  */
0093 EVENT(MEM_ACCESS,               0x10401e0)