powerpc/perf/power6-pmu.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Performance counter support for POWER6 processors.
0004  *
0005  * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/perf_event.h>
0009 #include <linux/string.h>
0010 #include <asm/reg.h>
0011 #include <asm/cputable.h>
0012
0013 #include "internal.h"
0014
0015 /*
0016  * Bits in event code for POWER6
0017  */
0018 #define PM_PMC_SH   20  /* PMC number (1-based) for direct events */
0019 #define PM_PMC_MSK  0x7
0020 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
0021 #define PM_UNIT_SH  16  /* Unit event comes (TTMxSEL encoding) */
0022 #define PM_UNIT_MSK 0xf
0023 #define PM_UNIT_MSKS    (PM_UNIT_MSK << PM_UNIT_SH)
0024 #define PM_LLAV     0x8000  /* Load lookahead match value */
0025 #define PM_LLA      0x4000  /* Load lookahead match enable */
0026 #define PM_BYTE_SH  12  /* Byte of event bus to use */
0027 #define PM_BYTE_MSK 3
0028 #define PM_SUBUNIT_SH   8   /* Subunit event comes from (NEST_SEL enc.) */
0029 #define PM_SUBUNIT_MSK  7
0030 #define PM_SUBUNIT_MSKS (PM_SUBUNIT_MSK << PM_SUBUNIT_SH)
0031 #define PM_PMCSEL_MSK   0xff    /* PMCxSEL value */
0032 #define PM_BUSEVENT_MSK 0xf3700
0033
0034 /*
0035  * Bits in MMCR1 for POWER6
0036  */
0037 #define MMCR1_TTM0SEL_SH    60
0038 #define MMCR1_TTMSEL_SH(n)  (MMCR1_TTM0SEL_SH - (n) * 4)
0039 #define MMCR1_TTMSEL_MSK    0xf
0040 #define MMCR1_TTMSEL(m, n)  (((m) >> MMCR1_TTMSEL_SH(n)) & MMCR1_TTMSEL_MSK)
0041 #define MMCR1_NESTSEL_SH    45
0042 #define MMCR1_NESTSEL_MSK   0x7
0043 #define MMCR1_NESTSEL(m)    (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
0044 #define MMCR1_PMC1_LLA      (1ul << 44)
0045 #define MMCR1_PMC1_LLA_VALUE    (1ul << 39)
0046 #define MMCR1_PMC1_ADDR_SEL (1ul << 35)
0047 #define MMCR1_PMC1SEL_SH    24
0048 #define MMCR1_PMCSEL_SH(n)  (MMCR1_PMC1SEL_SH - (n) * 8)
0049 #define MMCR1_PMCSEL_MSK    0xff
0050
0051 /*
0052  * Map of which direct events on which PMCs are marked instruction events.
0053  * Indexed by PMCSEL value >> 1.
0054  * Bottom 4 bits are a map of which PMCs are interesting,
0055  * top 4 bits say what sort of event:
0056  *   0 = direct marked event,
0057  *   1 = byte decode event,
0058  *   4 = add/and event (PMC1 -> bits 0 & 4),
0059  *   5 = add/and event (PMC1 -> bits 1 & 5),
0060  *   6 = add/and event (PMC1 -> bits 2 & 6),
0061  *   7 = add/and event (PMC1 -> bits 3 & 7).
0062  */
0063 static unsigned char direct_event_is_marked[0x60 >> 1] = {
0064     0,  /* 00 */
0065     0,  /* 02 */
0066     0,  /* 04 */
0067     0x07,   /* 06 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
0068     0x04,   /* 08 PM_MRK_DFU_FIN */
0069     0x06,   /* 0a PM_MRK_IFU_FIN, PM_MRK_INST_FIN */
0070     0,  /* 0c */
0071     0,  /* 0e */
0072     0x02,   /* 10 PM_MRK_INST_DISP */
0073     0x08,   /* 12 PM_MRK_LSU_DERAT_MISS */
0074     0,  /* 14 */
0075     0,  /* 16 */
0076     0x0c,   /* 18 PM_THRESH_TIMEO, PM_MRK_INST_FIN */
0077     0x0f,   /* 1a PM_MRK_INST_DISP, PM_MRK_{FXU,FPU,LSU}_FIN */
0078     0x01,   /* 1c PM_MRK_INST_ISSUED */
0079     0,  /* 1e */
0080     0,  /* 20 */
0081     0,  /* 22 */
0082     0,  /* 24 */
0083     0,  /* 26 */
0084     0x15,   /* 28 PM_MRK_DATA_FROM_L2MISS, PM_MRK_DATA_FROM_L3MISS */
0085     0,  /* 2a */
0086     0,  /* 2c */
0087     0,  /* 2e */
0088     0x4f,   /* 30 */
0089     0x7f,   /* 32 */
0090     0x4f,   /* 34 */
0091     0x5f,   /* 36 */
0092     0x6f,   /* 38 */
0093     0x4f,   /* 3a */
0094     0,  /* 3c */
0095     0x08,   /* 3e PM_MRK_INST_TIMEO */
0096     0x1f,   /* 40 */
0097     0x1f,   /* 42 */
0098     0x1f,   /* 44 */
0099     0x1f,   /* 46 */
0100     0x1f,   /* 48 */
0101     0x1f,   /* 4a */
0102     0x1f,   /* 4c */
0103     0x1f,   /* 4e */
0104     0,  /* 50 */
0105     0x05,   /* 52 PM_MRK_BR_TAKEN, PM_MRK_BR_MPRED */
0106     0x1c,   /* 54 PM_MRK_PTEG_FROM_L3MISS, PM_MRK_PTEG_FROM_L2MISS */
0107     0x02,   /* 56 PM_MRK_LD_MISS_L1 */
0108     0,  /* 58 */
0109     0,  /* 5a */
0110     0,  /* 5c */
0111     0,  /* 5e */
0112 };
0113
0114 /*
0115  * Masks showing for each unit which bits are marked events.
0116  * These masks are in LE order, i.e. 0x00000001 is byte 0, bit 0.
0117  */
0118 static u32 marked_bus_events[16] = {
0119     0x01000000, /* direct events set 1: byte 3 bit 0 */
0120     0x00010000, /* direct events set 2: byte 2 bit 0 */
0121     0, 0, 0, 0, /* IDU, IFU, nest: nothing */
0122     0x00000088, /* VMX set 1: byte 0 bits 3, 7 */
0123     0x000000c0, /* VMX set 2: byte 0 bits 4-7 */
0124     0x04010000, /* LSU set 1: byte 2 bit 0, byte 3 bit 2 */
0125     0xff010000u,    /* LSU set 2: byte 2 bit 0, all of byte 3 */
0126     0,      /* LSU set 3 */
0127     0x00000010, /* VMX set 3: byte 0 bit 4 */
0128     0,      /* BFP set 1 */
0129     0x00000022, /* BFP set 2: byte 0 bits 1, 5 */
0130     0, 0
0131 };
0132
0133 /*
0134  * Returns 1 if event counts things relating to marked instructions
0135  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
0136  */
0137 static int power6_marked_instr_event(u64 event)
0138 {
0139     int pmc, psel, ptype;
0140     int bit, byte, unit;
0141     u32 mask;
0142
0143     pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
0144     psel = (event & PM_PMCSEL_MSK) >> 1;    /* drop edge/level bit */
0145     if (pmc >= 5)
0146         return 0;
0147
0148     bit = -1;
0149     if (psel < sizeof(direct_event_is_marked)) {
0150         ptype = direct_event_is_marked[psel];
0151         if (pmc == 0 || !(ptype & (1 << (pmc - 1))))
0152             return 0;
0153         ptype >>= 4;
0154         if (ptype == 0)
0155             return 1;
0156         if (ptype == 1)
0157             bit = 0;
0158         else
0159             bit = ptype ^ (pmc - 1);
0160     } else if ((psel & 0x48) == 0x40)
0161         bit = psel & 7;
0162
0163     if (!(event & PM_BUSEVENT_MSK) || bit == -1)
0164         return 0;
0165
0166     byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
0167     unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
0168     mask = marked_bus_events[unit];
0169     return (mask >> (byte * 8 + bit)) & 1;
0170 }
0171
0172 /*
0173  * Assign PMC numbers and compute MMCR1 value for a set of events
0174  */
0175 static int p6_compute_mmcr(u64 event[], int n_ev,
0176                unsigned int hwc[], struct mmcr_regs *mmcr, struct perf_event *pevents[],
0177                u32 flags __maybe_unused)
0178 {
0179     unsigned long mmcr1 = 0;
0180     unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
0181     int i;
0182     unsigned int pmc, ev, b, u, s, psel;
0183     unsigned int ttmset = 0;
0184     unsigned int pmc_inuse = 0;
0185
0186     if (n_ev > 6)
0187         return -1;
0188     for (i = 0; i < n_ev; ++i) {
0189         pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
0190         if (pmc) {
0191             if (pmc_inuse & (1 << (pmc - 1)))
0192                 return -1;  /* collision! */
0193             pmc_inuse |= 1 << (pmc - 1);
0194         }
0195     }
0196     for (i = 0; i < n_ev; ++i) {
0197         ev = event[i];
0198         pmc = (ev >> PM_PMC_SH) & PM_PMC_MSK;
0199         if (pmc) {
0200             --pmc;
0201         } else {
0202             /* can go on any PMC; find a free one */
0203             for (pmc = 0; pmc < 4; ++pmc)
0204                 if (!(pmc_inuse & (1 << pmc)))
0205                     break;
0206             if (pmc >= 4)
0207                 return -1;
0208             pmc_inuse |= 1 << pmc;
0209         }
0210         hwc[i] = pmc;
0211         psel = ev & PM_PMCSEL_MSK;
0212         if (ev & PM_BUSEVENT_MSK) {
0213             /* this event uses the event bus */
0214             b = (ev >> PM_BYTE_SH) & PM_BYTE_MSK;
0215             u = (ev >> PM_UNIT_SH) & PM_UNIT_MSK;
0216             /* check for conflict on this byte of event bus */
0217             if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
0218                 return -1;
0219             mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
0220             ttmset |= 1 << b;
0221             if (u == 5) {
0222                 /* Nest events have a further mux */
0223                 s = (ev >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
0224                 if ((ttmset & 0x10) &&
0225                     MMCR1_NESTSEL(mmcr1) != s)
0226                     return -1;
0227                 ttmset |= 0x10;
0228                 mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
0229             }
0230             if (0x30 <= psel && psel <= 0x3d) {
0231                 /* these need the PMCx_ADDR_SEL bits */
0232                 if (b >= 2)
0233                     mmcr1 |= MMCR1_PMC1_ADDR_SEL >> pmc;
0234             }
0235             /* bus select values are different for PMC3/4 */
0236             if (pmc >= 2 && (psel & 0x90) == 0x80)
0237                 psel ^= 0x20;
0238         }
0239         if (ev & PM_LLA) {
0240             mmcr1 |= MMCR1_PMC1_LLA >> pmc;
0241             if (ev & PM_LLAV)
0242                 mmcr1 |= MMCR1_PMC1_LLA_VALUE >> pmc;
0243         }
0244         if (power6_marked_instr_event(event[i]))
0245             mmcra |= MMCRA_SAMPLE_ENABLE;
0246         if (pmc < 4)
0247             mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
0248     }
0249     mmcr->mmcr0 = 0;
0250     if (pmc_inuse & 1)
0251         mmcr->mmcr0 = MMCR0_PMC1CE;
0252     if (pmc_inuse & 0xe)
0253         mmcr->mmcr0 |= MMCR0_PMCjCE;
0254     mmcr->mmcr1 = mmcr1;
0255     mmcr->mmcra = mmcra;
0256     return 0;
0257 }
0258
0259 /*
0260  * Layout of constraint bits:
0261  *
0262  *  0-1 add field: number of uses of PMC1 (max 1)
0263  *  2-3, 4-5, 6-7, 8-9, 10-11: ditto for PMC2, 3, 4, 5, 6
0264  *  12-15   add field: number of uses of PMC1-4 (max 4)
0265  *  16-19   select field: unit on byte 0 of event bus
0266  *  20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
0267  *  32-34   select field: nest (subunit) event selector
0268  */
0269 static int p6_get_constraint(u64 event, unsigned long *maskp,
0270                  unsigned long *valp, u64 event_config1 __maybe_unused)
0271 {
0272     int pmc, byte, sh, subunit;
0273     unsigned long mask = 0, value = 0;
0274
0275     pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
0276     if (pmc) {
0277         if (pmc > 4 && !(event == 0x500009 || event == 0x600005))
0278             return -1;
0279         sh = (pmc - 1) * 2;
0280         mask |= 2 << sh;
0281         value |= 1 << sh;
0282     }
0283     if (event & PM_BUSEVENT_MSK) {
0284         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
0285         sh = byte * 4 + (16 - PM_UNIT_SH);
0286         mask |= PM_UNIT_MSKS << sh;
0287         value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
0288         if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
0289             subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
0290             mask  |= (unsigned long)PM_SUBUNIT_MSK << 32;
0291             value |= (unsigned long)subunit << 32;
0292         }
0293     }
0294     if (pmc <= 4) {
0295         mask  |= 0x8000;    /* add field for count of PMC1-4 uses */
0296         value |= 0x1000;
0297     }
0298     *maskp = mask;
0299     *valp = value;
0300     return 0;
0301 }
0302
0303 static int p6_limited_pmc_event(u64 event)
0304 {
0305     int pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
0306
0307     return pmc == 5 || pmc == 6;
0308 }
0309
0310 #define MAX_ALT 4   /* at most 4 alternatives for any event */
0311
0312 static const unsigned int event_alternatives[][MAX_ALT] = {
0313     { 0x0130e8, 0x2000f6, 0x3000fc },   /* PM_PTEG_RELOAD_VALID */
0314     { 0x080080, 0x10000d, 0x30000c, 0x4000f0 }, /* PM_LD_MISS_L1 */
0315     { 0x080088, 0x200054, 0x3000f0 },   /* PM_ST_MISS_L1 */
0316     { 0x10000a, 0x2000f4, 0x600005 },   /* PM_RUN_CYC */
0317     { 0x10000b, 0x2000f5 },         /* PM_RUN_COUNT */
0318     { 0x10000e, 0x400010 },         /* PM_PURR */
0319     { 0x100010, 0x4000f8 },         /* PM_FLUSH */
0320     { 0x10001a, 0x200010 },         /* PM_MRK_INST_DISP */
0321     { 0x100026, 0x3000f8 },         /* PM_TB_BIT_TRANS */
0322     { 0x100054, 0x2000f0 },         /* PM_ST_FIN */
0323     { 0x100056, 0x2000fc },         /* PM_L1_ICACHE_MISS */
0324     { 0x1000f0, 0x40000a },         /* PM_INST_IMC_MATCH_CMPL */
0325     { 0x1000f8, 0x200008 },         /* PM_GCT_EMPTY_CYC */
0326     { 0x1000fc, 0x400006 },         /* PM_LSU_DERAT_MISS_CYC */
0327     { 0x20000e, 0x400007 },         /* PM_LSU_DERAT_MISS */
0328     { 0x200012, 0x300012 },         /* PM_INST_DISP */
0329     { 0x2000f2, 0x3000f2 },         /* PM_INST_DISP */
0330     { 0x2000f8, 0x300010 },         /* PM_EXT_INT */
0331     { 0x2000fe, 0x300056 },         /* PM_DATA_FROM_L2MISS */
0332     { 0x2d0030, 0x30001a },         /* PM_MRK_FPU_FIN */
0333     { 0x30000a, 0x400018 },         /* PM_MRK_INST_FIN */
0334     { 0x3000f6, 0x40000e },         /* PM_L1_DCACHE_RELOAD_VALID */
0335     { 0x3000fe, 0x400056 },         /* PM_DATA_FROM_L3MISS */
0336 };
0337
0338 /*
0339  * This could be made more efficient with a binary search on
0340  * a presorted list, if necessary
0341  */
0342 static int find_alternatives_list(u64 event)
0343 {
0344     int i, j;
0345     unsigned int alt;
0346
0347     for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
0348         if (event < event_alternatives[i][0])
0349             return -1;
0350         for (j = 0; j < MAX_ALT; ++j) {
0351             alt = event_alternatives[i][j];
0352             if (!alt || event < alt)
0353                 break;
0354             if (event == alt)
0355                 return i;
0356         }
0357     }
0358     return -1;
0359 }
0360
0361 static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
0362 {
0363     int i, j, nlim;
0364     unsigned int psel, pmc;
0365     unsigned int nalt = 1;
0366     u64 aevent;
0367
0368     alt[0] = event;
0369     nlim = p6_limited_pmc_event(event);
0370
0371     /* check the alternatives table */
0372     i = find_alternatives_list(event);
0373     if (i >= 0) {
0374         /* copy out alternatives from list */
0375         for (j = 0; j < MAX_ALT; ++j) {
0376             aevent = event_alternatives[i][j];
0377             if (!aevent)
0378                 break;
0379             if (aevent != event)
0380                 alt[nalt++] = aevent;
0381             nlim += p6_limited_pmc_event(aevent);
0382         }
0383
0384     } else {
0385         /* Check for alternative ways of computing sum events */
0386         /* PMCSEL 0x32 counter N == PMCSEL 0x34 counter 5-N */
0387         psel = event & (PM_PMCSEL_MSK & ~1);    /* ignore edge bit */
0388         pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
0389         if (pmc && (psel == 0x32 || psel == 0x34))
0390             alt[nalt++] = ((event ^ 0x6) & ~PM_PMC_MSKS) |
0391                 ((5 - pmc) << PM_PMC_SH);
0392
0393         /* PMCSEL 0x38 counter N == PMCSEL 0x3a counter N+/-2 */
0394         if (pmc && (psel == 0x38 || psel == 0x3a))
0395             alt[nalt++] = ((event ^ 0x2) & ~PM_PMC_MSKS) |
0396                 ((pmc > 2? pmc - 2: pmc + 2) << PM_PMC_SH);
0397     }
0398
0399     if (flags & PPMU_ONLY_COUNT_RUN) {
0400         /*
0401          * We're only counting in RUN state,
0402          * so PM_CYC is equivalent to PM_RUN_CYC,
0403          * PM_INST_CMPL === PM_RUN_INST_CMPL, PM_PURR === PM_RUN_PURR.
0404          * This doesn't include alternatives that don't provide
0405          * any extra flexibility in assigning PMCs (e.g.
0406          * 0x10000a for PM_RUN_CYC vs. 0x1e for PM_CYC).
0407          * Note that even with these additional alternatives
0408          * we never end up with more than 4 alternatives for any event.
0409          */
0410         j = nalt;
0411         for (i = 0; i < nalt; ++i) {
0412             switch (alt[i]) {
0413             case 0x1e:  /* PM_CYC */
0414                 alt[j++] = 0x600005;    /* PM_RUN_CYC */
0415                 ++nlim;
0416                 break;
0417             case 0x10000a:  /* PM_RUN_CYC */
0418                 alt[j++] = 0x1e;    /* PM_CYC */
0419                 break;
0420             case 2:     /* PM_INST_CMPL */
0421                 alt[j++] = 0x500009;    /* PM_RUN_INST_CMPL */
0422                 ++nlim;
0423                 break;
0424             case 0x500009:  /* PM_RUN_INST_CMPL */
0425                 alt[j++] = 2;       /* PM_INST_CMPL */
0426                 break;
0427             case 0x10000e:  /* PM_PURR */
0428                 alt[j++] = 0x4000f4;    /* PM_RUN_PURR */
0429                 break;
0430             case 0x4000f4:  /* PM_RUN_PURR */
0431                 alt[j++] = 0x10000e;    /* PM_PURR */
0432                 break;
0433             }
0434         }
0435         nalt = j;
0436     }
0437
0438     if (!(flags & PPMU_LIMITED_PMC_OK) && nlim) {
0439         /* remove the limited PMC events */
0440         j = 0;
0441         for (i = 0; i < nalt; ++i) {
0442             if (!p6_limited_pmc_event(alt[i])) {
0443                 alt[j] = alt[i];
0444                 ++j;
0445             }
0446         }
0447         nalt = j;
0448     } else if ((flags & PPMU_LIMITED_PMC_REQD) && nlim < nalt) {
0449         /* remove all but the limited PMC events */
0450         j = 0;
0451         for (i = 0; i < nalt; ++i) {
0452             if (p6_limited_pmc_event(alt[i])) {
0453                 alt[j] = alt[i];
0454                 ++j;
0455             }
0456         }
0457         nalt = j;
0458     }
0459
0460     return nalt;
0461 }
0462
0463 static void p6_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
0464 {
0465     /* Set PMCxSEL to 0 to disable PMCx */
0466     if (pmc <= 3)
0467         mmcr->mmcr1 &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
0468 }
0469
0470 static int power6_generic_events[] = {
0471     [PERF_COUNT_HW_CPU_CYCLES]      = 0x1e,
0472     [PERF_COUNT_HW_INSTRUCTIONS]        = 2,
0473     [PERF_COUNT_HW_CACHE_REFERENCES]    = 0x280030, /* LD_REF_L1 */
0474     [PERF_COUNT_HW_CACHE_MISSES]        = 0x30000c, /* LD_MISS_L1 */
0475     [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x410a0,  /* BR_PRED */
0476     [PERF_COUNT_HW_BRANCH_MISSES]       = 0x400052, /* BR_MPRED */
0477 };
0478
0479 #define C(x)    PERF_COUNT_HW_CACHE_##x
0480
0481 /*
0482  * Table of generalized cache-related events.
0483  * 0 means not supported, -1 means nonsensical, other values
0484  * are event codes.
0485  * The "DTLB" and "ITLB" events relate to the DERAT and IERAT.
0486  */
0487 static u64 power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
0488     [C(L1D)] = {        /*  RESULT_ACCESS   RESULT_MISS */
0489         [C(OP_READ)] = {    0x280030,   0x80080     },
0490         [C(OP_WRITE)] = {   0x180032,   0x80088     },
0491         [C(OP_PREFETCH)] = {    0x810a4,    0       },
0492     },
0493     [C(L1I)] = {        /*  RESULT_ACCESS   RESULT_MISS */
0494         [C(OP_READ)] = {    0,      0x100056    },
0495         [C(OP_WRITE)] = {   -1,     -1      },
0496         [C(OP_PREFETCH)] = {    0x4008c,    0       },
0497     },
0498     [C(LL)] = {     /*  RESULT_ACCESS   RESULT_MISS */
0499         [C(OP_READ)] = {    0x150730,   0x250532    },
0500         [C(OP_WRITE)] = {   0x250432,   0x150432    },
0501         [C(OP_PREFETCH)] = {    0x810a6,    0       },
0502     },
0503     [C(DTLB)] = {       /*  RESULT_ACCESS   RESULT_MISS */
0504         [C(OP_READ)] = {    0,      0x20000e    },
0505         [C(OP_WRITE)] = {   -1,     -1      },
0506         [C(OP_PREFETCH)] = {    -1,     -1      },
0507     },
0508     [C(ITLB)] = {       /*  RESULT_ACCESS   RESULT_MISS */
0509         [C(OP_READ)] = {    0,      0x420ce     },
0510         [C(OP_WRITE)] = {   -1,     -1      },
0511         [C(OP_PREFETCH)] = {    -1,     -1      },
0512     },
0513     [C(BPU)] = {        /*  RESULT_ACCESS   RESULT_MISS */
0514         [C(OP_READ)] = {    0x430e6,    0x400052    },
0515         [C(OP_WRITE)] = {   -1,     -1      },
0516         [C(OP_PREFETCH)] = {    -1,     -1      },
0517     },
0518     [C(NODE)] = {       /*  RESULT_ACCESS   RESULT_MISS */
0519         [C(OP_READ)] = {    -1,     -1      },
0520         [C(OP_WRITE)] = {   -1,     -1      },
0521         [C(OP_PREFETCH)] = {    -1,     -1      },
0522     },
0523 };
0524
0525 static struct power_pmu power6_pmu = {
0526     .name           = "POWER6",
0527     .n_counter      = 6,
0528     .max_alternatives   = MAX_ALT,
0529     .add_fields     = 0x1555,
0530     .test_adder     = 0x3000,
0531     .compute_mmcr       = p6_compute_mmcr,
0532     .get_constraint     = p6_get_constraint,
0533     .get_alternatives   = p6_get_alternatives,
0534     .disable_pmc        = p6_disable_pmc,
0535     .limited_pmc_event  = p6_limited_pmc_event,
0536     .flags          = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
0537     .n_generic      = ARRAY_SIZE(power6_generic_events),
0538     .generic_events     = power6_generic_events,
0539     .cache_events       = &power6_cache_events,
0540 };
0541
0542 int __init init_power6_pmu(void)
0543 {
0544     unsigned int pvr = mfspr(SPRN_PVR);
0545
0546     if (PVR_VER(pvr) != PVR_POWER6)
0547         return -ENODEV;
0548
0549     return register_power_pmu(&power6_pmu);
0550 }