Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Performance counter support for POWER5 (not POWER5++) processors.
0004  *
0005  * Copyright 2009 Paul Mackerras, IBM Corporation.
0006  */
0007 #include <linux/kernel.h>
0008 #include <linux/perf_event.h>
0009 #include <linux/string.h>
0010 #include <asm/reg.h>
0011 #include <asm/cputable.h>
0012 
0013 #include "internal.h"
0014 
0015 /*
0016  * Bits in event code for POWER5 (not POWER5++)
0017  */
0018 #define PM_PMC_SH   20  /* PMC number (1-based) for direct events */
0019 #define PM_PMC_MSK  0xf
0020 #define PM_PMC_MSKS (PM_PMC_MSK << PM_PMC_SH)
0021 #define PM_UNIT_SH  16  /* TTMMUX number and setting - unit select */
0022 #define PM_UNIT_MSK 0xf
0023 #define PM_BYTE_SH  12  /* Byte number of event bus to use */
0024 #define PM_BYTE_MSK 7
0025 #define PM_GRS_SH   8   /* Storage subsystem mux select */
0026 #define PM_GRS_MSK  7
0027 #define PM_BUSEVENT_MSK 0x80    /* Set if event uses event bus */
0028 #define PM_PMCSEL_MSK   0x7f
0029 
0030 /* Values in PM_UNIT field */
0031 #define PM_FPU      0
0032 #define PM_ISU0     1
0033 #define PM_IFU      2
0034 #define PM_ISU1     3
0035 #define PM_IDU      4
0036 #define PM_ISU0_ALT 6
0037 #define PM_GRS      7
0038 #define PM_LSU0     8
0039 #define PM_LSU1     0xc
0040 #define PM_LASTUNIT 0xc
0041 
0042 /*
0043  * Bits in MMCR1 for POWER5
0044  */
0045 #define MMCR1_TTM0SEL_SH    62
0046 #define MMCR1_TTM1SEL_SH    60
0047 #define MMCR1_TTM2SEL_SH    58
0048 #define MMCR1_TTM3SEL_SH    56
0049 #define MMCR1_TTMSEL_MSK    3
0050 #define MMCR1_TD_CP_DBG0SEL_SH  54
0051 #define MMCR1_TD_CP_DBG1SEL_SH  52
0052 #define MMCR1_TD_CP_DBG2SEL_SH  50
0053 #define MMCR1_TD_CP_DBG3SEL_SH  48
0054 #define MMCR1_GRS_L2SEL_SH  46
0055 #define MMCR1_GRS_L2SEL_MSK 3
0056 #define MMCR1_GRS_L3SEL_SH  44
0057 #define MMCR1_GRS_L3SEL_MSK 3
0058 #define MMCR1_GRS_MCSEL_SH  41
0059 #define MMCR1_GRS_MCSEL_MSK 7
0060 #define MMCR1_GRS_FABSEL_SH 39
0061 #define MMCR1_GRS_FABSEL_MSK    3
0062 #define MMCR1_PMC1_ADDER_SEL_SH 35
0063 #define MMCR1_PMC2_ADDER_SEL_SH 34
0064 #define MMCR1_PMC3_ADDER_SEL_SH 33
0065 #define MMCR1_PMC4_ADDER_SEL_SH 32
0066 #define MMCR1_PMC1SEL_SH    25
0067 #define MMCR1_PMC2SEL_SH    17
0068 #define MMCR1_PMC3SEL_SH    9
0069 #define MMCR1_PMC4SEL_SH    1
0070 #define MMCR1_PMCSEL_SH(n)  (MMCR1_PMC1SEL_SH - (n) * 8)
0071 #define MMCR1_PMCSEL_MSK    0x7f
0072 
0073 /*
0074  * Layout of constraint bits:
0075  * 6666555555555544444444443333333333222222222211111111110000000000
0076  * 3210987654321098765432109876543210987654321098765432109876543210
0077  *         <><>[  ><><>< ><> [  >[ >[ ><  ><  ><  ><  ><><><><><><>
0078  *         T0T1 NC G0G1G2 G3  UC PS1PS2 B0  B1  B2  B3 P6P5P4P3P2P1
0079  *
0080  * T0 - TTM0 constraint
0081  *     54-55: TTM0SEL value (0=FPU, 2=IFU, 3=ISU1) 0xc0_0000_0000_0000
0082  *
0083  * T1 - TTM1 constraint
0084  *     52-53: TTM1SEL value (0=IDU, 3=GRS) 0x30_0000_0000_0000
0085  *
0086  * NC - number of counters
0087  *     51: NC error 0x0008_0000_0000_0000
0088  *     48-50: number of events needing PMC1-4 0x0007_0000_0000_0000
0089  *
0090  * G0..G3 - GRS mux constraints
0091  *     46-47: GRS_L2SEL value
0092  *     44-45: GRS_L3SEL value
0093  *     41-44: GRS_MCSEL value
0094  *     39-40: GRS_FABSEL value
0095  *  Note that these match up with their bit positions in MMCR1
0096  *
0097  * UC - unit constraint: can't have all three of FPU|IFU|ISU1, ISU0, IDU|GRS
0098  *     37: UC3 error 0x20_0000_0000
0099  *     36: FPU|IFU|ISU1 events needed 0x10_0000_0000
0100  *     35: ISU0 events needed 0x08_0000_0000
0101  *     34: IDU|GRS events needed 0x04_0000_0000
0102  *
0103  * PS1
0104  *     33: PS1 error 0x2_0000_0000
0105  *     31-32: count of events needing PMC1/2 0x1_8000_0000
0106  *
0107  * PS2
0108  *     30: PS2 error 0x4000_0000
0109  *     28-29: count of events needing PMC3/4 0x3000_0000
0110  *
0111  * B0
0112  *     24-27: Byte 0 event source 0x0f00_0000
0113  *        Encoding as for the event code
0114  *
0115  * B1, B2, B3
0116  *     20-23, 16-19, 12-15: Byte 1, 2, 3 event sources
0117  *
0118  * P1..P6
0119  *     0-11: Count of events needing PMC1..PMC6
0120  */
0121 
0122 static const int grsel_shift[8] = {
0123     MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH, MMCR1_GRS_L2SEL_SH,
0124     MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH, MMCR1_GRS_L3SEL_SH,
0125     MMCR1_GRS_MCSEL_SH, MMCR1_GRS_FABSEL_SH
0126 };
0127 
0128 /* Masks and values for using events from the various units */
0129 static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
0130     [PM_FPU] =   { 0xc0002000000000ul, 0x00001000000000ul },
0131     [PM_ISU0] =  { 0x00002000000000ul, 0x00000800000000ul },
0132     [PM_ISU1] =  { 0xc0002000000000ul, 0xc0001000000000ul },
0133     [PM_IFU] =   { 0xc0002000000000ul, 0x80001000000000ul },
0134     [PM_IDU] =   { 0x30002000000000ul, 0x00000400000000ul },
0135     [PM_GRS] =   { 0x30002000000000ul, 0x30000400000000ul },
0136 };
0137 
0138 static int power5_get_constraint(u64 event, unsigned long *maskp,
0139                  unsigned long *valp, u64 event_config1 __maybe_unused)
0140 {
0141     int pmc, byte, unit, sh;
0142     int bit, fmask;
0143     unsigned long mask = 0, value = 0;
0144     int grp = -1;
0145 
0146     pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
0147     if (pmc) {
0148         if (pmc > 6)
0149             return -1;
0150         sh = (pmc - 1) * 2;
0151         mask |= 2 << sh;
0152         value |= 1 << sh;
0153         if (pmc <= 4)
0154             grp = (pmc - 1) >> 1;
0155         else if (event != 0x500009 && event != 0x600005)
0156             return -1;
0157     }
0158     if (event & PM_BUSEVENT_MSK) {
0159         unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
0160         if (unit > PM_LASTUNIT)
0161             return -1;
0162         if (unit == PM_ISU0_ALT)
0163             unit = PM_ISU0;
0164         mask |= unit_cons[unit][0];
0165         value |= unit_cons[unit][1];
0166         byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
0167         if (byte >= 4) {
0168             if (unit != PM_LSU1)
0169                 return -1;
0170             /* Map LSU1 low word (bytes 4-7) to unit LSU1+1 */
0171             ++unit;
0172             byte &= 3;
0173         }
0174         if (unit == PM_GRS) {
0175             bit = event & 7;
0176             fmask = (bit == 6)? 7: 3;
0177             sh = grsel_shift[bit];
0178             mask |= (unsigned long)fmask << sh;
0179             value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
0180                 << sh;
0181         }
0182         /*
0183          * Bus events on bytes 0 and 2 can be counted
0184          * on PMC1/2; bytes 1 and 3 on PMC3/4.
0185          */
0186         if (!pmc)
0187             grp = byte & 1;
0188         /* Set byte lane select field */
0189         mask  |= 0xfUL << (24 - 4 * byte);
0190         value |= (unsigned long)unit << (24 - 4 * byte);
0191     }
0192     if (grp == 0) {
0193         /* increment PMC1/2 field */
0194         mask  |= 0x200000000ul;
0195         value |= 0x080000000ul;
0196     } else if (grp == 1) {
0197         /* increment PMC3/4 field */
0198         mask  |= 0x40000000ul;
0199         value |= 0x10000000ul;
0200     }
0201     if (pmc < 5) {
0202         /* need a counter from PMC1-4 set */
0203         mask  |= 0x8000000000000ul;
0204         value |= 0x1000000000000ul;
0205     }
0206     *maskp = mask;
0207     *valp = value;
0208     return 0;
0209 }
0210 
0211 #define MAX_ALT 3   /* at most 3 alternatives for any event */
0212 
0213 static const unsigned int event_alternatives[][MAX_ALT] = {
0214     { 0x120e4,  0x400002 },         /* PM_GRP_DISP_REJECT */
0215     { 0x410c7,  0x441084 },         /* PM_THRD_L2MISS_BOTH_CYC */
0216     { 0x100005, 0x600005 },         /* PM_RUN_CYC */
0217     { 0x100009, 0x200009, 0x500009 },   /* PM_INST_CMPL */
0218     { 0x300009, 0x400009 },         /* PM_INST_DISP */
0219 };
0220 
0221 /*
0222  * Scan the alternatives table for a match and return the
0223  * index into the alternatives table if found, else -1.
0224  */
0225 static int find_alternative(u64 event)
0226 {
0227     int i, j;
0228 
0229     for (i = 0; i < ARRAY_SIZE(event_alternatives); ++i) {
0230         if (event < event_alternatives[i][0])
0231             break;
0232         for (j = 0; j < MAX_ALT && event_alternatives[i][j]; ++j)
0233             if (event == event_alternatives[i][j])
0234                 return i;
0235     }
0236     return -1;
0237 }
0238 
0239 static const unsigned char bytedecode_alternatives[4][4] = {
0240     /* PMC 1 */ { 0x21, 0x23, 0x25, 0x27 },
0241     /* PMC 2 */ { 0x07, 0x17, 0x0e, 0x1e },
0242     /* PMC 3 */ { 0x20, 0x22, 0x24, 0x26 },
0243     /* PMC 4 */ { 0x07, 0x17, 0x0e, 0x1e }
0244 };
0245 
0246 /*
0247  * Some direct events for decodes of event bus byte 3 have alternative
0248  * PMCSEL values on other counters.  This returns the alternative
0249  * event code for those that do, or -1 otherwise.
0250  */
0251 static s64 find_alternative_bdecode(u64 event)
0252 {
0253     int pmc, altpmc, pp, j;
0254 
0255     pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
0256     if (pmc == 0 || pmc > 4)
0257         return -1;
0258     altpmc = 5 - pmc;   /* 1 <-> 4, 2 <-> 3 */
0259     pp = event & PM_PMCSEL_MSK;
0260     for (j = 0; j < 4; ++j) {
0261         if (bytedecode_alternatives[pmc - 1][j] == pp) {
0262             return (event & ~(PM_PMC_MSKS | PM_PMCSEL_MSK)) |
0263                 (altpmc << PM_PMC_SH) |
0264                 bytedecode_alternatives[altpmc - 1][j];
0265         }
0266     }
0267     return -1;
0268 }
0269 
0270 static int power5_get_alternatives(u64 event, unsigned int flags, u64 alt[])
0271 {
0272     int i, j, nalt = 1;
0273     s64 ae;
0274 
0275     alt[0] = event;
0276     nalt = 1;
0277     i = find_alternative(event);
0278     if (i >= 0) {
0279         for (j = 0; j < MAX_ALT; ++j) {
0280             ae = event_alternatives[i][j];
0281             if (ae && ae != event)
0282                 alt[nalt++] = ae;
0283         }
0284     } else {
0285         ae = find_alternative_bdecode(event);
0286         if (ae > 0)
0287             alt[nalt++] = ae;
0288     }
0289     return nalt;
0290 }
0291 
0292 /*
0293  * Map of which direct events on which PMCs are marked instruction events.
0294  * Indexed by PMCSEL value, bit i (LE) set if PMC i is a marked event.
0295  * Bit 0 is set if it is marked for all PMCs.
0296  * The 0x80 bit indicates a byte decode PMCSEL value.
0297  */
0298 static unsigned char direct_event_is_marked[0x28] = {
0299     0,  /* 00 */
0300     0x1f,   /* 01 PM_IOPS_CMPL */
0301     0x2,    /* 02 PM_MRK_GRP_DISP */
0302     0xe,    /* 03 PM_MRK_ST_CMPL, PM_MRK_ST_GPS, PM_MRK_ST_CMPL_INT */
0303     0,  /* 04 */
0304     0x1c,   /* 05 PM_MRK_BRU_FIN, PM_MRK_INST_FIN, PM_MRK_CRU_FIN */
0305     0x80,   /* 06 */
0306     0x80,   /* 07 */
0307     0, 0, 0,/* 08 - 0a */
0308     0x18,   /* 0b PM_THRESH_TIMEO, PM_MRK_GRP_TIMEO */
0309     0,  /* 0c */
0310     0x80,   /* 0d */
0311     0x80,   /* 0e */
0312     0,  /* 0f */
0313     0,  /* 10 */
0314     0x14,   /* 11 PM_MRK_GRP_BR_REDIR, PM_MRK_GRP_IC_MISS */
0315     0,  /* 12 */
0316     0x10,   /* 13 PM_MRK_GRP_CMPL */
0317     0x1f,   /* 14 PM_GRP_MRK, PM_MRK_{FXU,FPU,LSU}_FIN */
0318     0x2,    /* 15 PM_MRK_GRP_ISSUED */
0319     0x80,   /* 16 */
0320     0x80,   /* 17 */
0321     0, 0, 0, 0, 0,
0322     0x80,   /* 1d */
0323     0x80,   /* 1e */
0324     0,  /* 1f */
0325     0x80,   /* 20 */
0326     0x80,   /* 21 */
0327     0x80,   /* 22 */
0328     0x80,   /* 23 */
0329     0x80,   /* 24 */
0330     0x80,   /* 25 */
0331     0x80,   /* 26 */
0332     0x80,   /* 27 */
0333 };
0334 
0335 /*
0336  * Returns 1 if event counts things relating to marked instructions
0337  * and thus needs the MMCRA_SAMPLE_ENABLE bit set, or 0 if not.
0338  */
0339 static int power5_marked_instr_event(u64 event)
0340 {
0341     int pmc, psel;
0342     int bit, byte, unit;
0343     u32 mask;
0344 
0345     pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
0346     psel = event & PM_PMCSEL_MSK;
0347     if (pmc >= 5)
0348         return 0;
0349 
0350     bit = -1;
0351     if (psel < sizeof(direct_event_is_marked)) {
0352         if (direct_event_is_marked[psel] & (1 << pmc))
0353             return 1;
0354         if (direct_event_is_marked[psel] & 0x80)
0355             bit = 4;
0356         else if (psel == 0x08)
0357             bit = pmc - 1;
0358         else if (psel == 0x10)
0359             bit = 4 - pmc;
0360         else if (psel == 0x1b && (pmc == 1 || pmc == 3))
0361             bit = 4;
0362     } else if ((psel & 0x58) == 0x40)
0363         bit = psel & 7;
0364 
0365     if (!(event & PM_BUSEVENT_MSK))
0366         return 0;
0367 
0368     byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
0369     unit = (event >> PM_UNIT_SH) & PM_UNIT_MSK;
0370     if (unit == PM_LSU0) {
0371         /* byte 1 bits 0-7, byte 2 bits 0,2-4,6 */
0372         mask = 0x5dff00;
0373     } else if (unit == PM_LSU1 && byte >= 4) {
0374         byte -= 4;
0375         /* byte 4 bits 1,3,5,7, byte 5 bits 6-7, byte 7 bits 0-4,6 */
0376         mask = 0x5f00c0aa;
0377     } else
0378         return 0;
0379 
0380     return (mask >> (byte * 8 + bit)) & 1;
0381 }
0382 
0383 static int power5_compute_mmcr(u64 event[], int n_ev,
0384                    unsigned int hwc[], struct mmcr_regs *mmcr,
0385                    struct perf_event *pevents[],
0386                    u32 flags __maybe_unused)
0387 {
0388     unsigned long mmcr1 = 0;
0389     unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;
0390     unsigned int pmc, unit, byte, psel;
0391     unsigned int ttm, grp;
0392     int i, isbus, bit, grsel;
0393     unsigned int pmc_inuse = 0;
0394     unsigned int pmc_grp_use[2];
0395     unsigned char busbyte[4];
0396     unsigned char unituse[16];
0397     int ttmuse;
0398 
0399     if (n_ev > 6)
0400         return -1;
0401 
0402     /* First pass to count resource use */
0403     pmc_grp_use[0] = pmc_grp_use[1] = 0;
0404     memset(busbyte, 0, sizeof(busbyte));
0405     memset(unituse, 0, sizeof(unituse));
0406     for (i = 0; i < n_ev; ++i) {
0407         pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
0408         if (pmc) {
0409             if (pmc > 6)
0410                 return -1;
0411             if (pmc_inuse & (1 << (pmc - 1)))
0412                 return -1;
0413             pmc_inuse |= 1 << (pmc - 1);
0414             /* count 1/2 vs 3/4 use */
0415             if (pmc <= 4)
0416                 ++pmc_grp_use[(pmc - 1) >> 1];
0417         }
0418         if (event[i] & PM_BUSEVENT_MSK) {
0419             unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
0420             byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
0421             if (unit > PM_LASTUNIT)
0422                 return -1;
0423             if (unit == PM_ISU0_ALT)
0424                 unit = PM_ISU0;
0425             if (byte >= 4) {
0426                 if (unit != PM_LSU1)
0427                     return -1;
0428                 ++unit;
0429                 byte &= 3;
0430             }
0431             if (!pmc)
0432                 ++pmc_grp_use[byte & 1];
0433             if (busbyte[byte] && busbyte[byte] != unit)
0434                 return -1;
0435             busbyte[byte] = unit;
0436             unituse[unit] = 1;
0437         }
0438     }
0439     if (pmc_grp_use[0] > 2 || pmc_grp_use[1] > 2)
0440         return -1;
0441 
0442     /*
0443      * Assign resources and set multiplexer selects.
0444      *
0445      * PM_ISU0 can go either on TTM0 or TTM1, but that's the only
0446      * choice we have to deal with.
0447      */
0448     if (unituse[PM_ISU0] &
0449         (unituse[PM_FPU] | unituse[PM_IFU] | unituse[PM_ISU1])) {
0450         unituse[PM_ISU0_ALT] = 1;   /* move ISU to TTM1 */
0451         unituse[PM_ISU0] = 0;
0452     }
0453     /* Set TTM[01]SEL fields. */
0454     ttmuse = 0;
0455     for (i = PM_FPU; i <= PM_ISU1; ++i) {
0456         if (!unituse[i])
0457             continue;
0458         if (ttmuse++)
0459             return -1;
0460         mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
0461     }
0462     ttmuse = 0;
0463     for (; i <= PM_GRS; ++i) {
0464         if (!unituse[i])
0465             continue;
0466         if (ttmuse++)
0467             return -1;
0468         mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
0469     }
0470     if (ttmuse > 1)
0471         return -1;
0472 
0473     /* Set byte lane select fields, TTM[23]SEL and GRS_*SEL. */
0474     for (byte = 0; byte < 4; ++byte) {
0475         unit = busbyte[byte];
0476         if (!unit)
0477             continue;
0478         if (unit == PM_ISU0 && unituse[PM_ISU0_ALT]) {
0479             /* get ISU0 through TTM1 rather than TTM0 */
0480             unit = PM_ISU0_ALT;
0481         } else if (unit == PM_LSU1 + 1) {
0482             /* select lower word of LSU1 for this byte */
0483             mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
0484         }
0485         ttm = unit >> 2;
0486         mmcr1 |= (unsigned long)ttm
0487             << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
0488     }
0489 
0490     /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
0491     for (i = 0; i < n_ev; ++i) {
0492         pmc = (event[i] >> PM_PMC_SH) & PM_PMC_MSK;
0493         unit = (event[i] >> PM_UNIT_SH) & PM_UNIT_MSK;
0494         byte = (event[i] >> PM_BYTE_SH) & PM_BYTE_MSK;
0495         psel = event[i] & PM_PMCSEL_MSK;
0496         isbus = event[i] & PM_BUSEVENT_MSK;
0497         if (!pmc) {
0498             /* Bus event or any-PMC direct event */
0499             for (pmc = 0; pmc < 4; ++pmc) {
0500                 if (pmc_inuse & (1 << pmc))
0501                     continue;
0502                 grp = (pmc >> 1) & 1;
0503                 if (isbus) {
0504                     if (grp == (byte & 1))
0505                         break;
0506                 } else if (pmc_grp_use[grp] < 2) {
0507                     ++pmc_grp_use[grp];
0508                     break;
0509                 }
0510             }
0511             pmc_inuse |= 1 << pmc;
0512         } else if (pmc <= 4) {
0513             /* Direct event */
0514             --pmc;
0515             if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
0516                 /* add events on higher-numbered bus */
0517                 mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
0518         } else {
0519             /* Instructions or run cycles on PMC5/6 */
0520             --pmc;
0521         }
0522         if (isbus && unit == PM_GRS) {
0523             bit = psel & 7;
0524             grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
0525             mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
0526         }
0527         if (power5_marked_instr_event(event[i]))
0528             mmcra |= MMCRA_SAMPLE_ENABLE;
0529         if (pmc <= 3)
0530             mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
0531         hwc[i] = pmc;
0532     }
0533 
0534     /* Return MMCRx values */
0535     mmcr->mmcr0 = 0;
0536     if (pmc_inuse & 1)
0537         mmcr->mmcr0 = MMCR0_PMC1CE;
0538     if (pmc_inuse & 0x3e)
0539         mmcr->mmcr0 |= MMCR0_PMCjCE;
0540     mmcr->mmcr1 = mmcr1;
0541     mmcr->mmcra = mmcra;
0542     return 0;
0543 }
0544 
0545 static void power5_disable_pmc(unsigned int pmc, struct mmcr_regs *mmcr)
0546 {
0547     if (pmc <= 3)
0548         mmcr->mmcr1 &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
0549 }
0550 
0551 static int power5_generic_events[] = {
0552     [PERF_COUNT_HW_CPU_CYCLES]      = 0xf,
0553     [PERF_COUNT_HW_INSTRUCTIONS]        = 0x100009,
0554     [PERF_COUNT_HW_CACHE_REFERENCES]    = 0x4c1090, /* LD_REF_L1 */
0555     [PERF_COUNT_HW_CACHE_MISSES]        = 0x3c1088, /* LD_MISS_L1 */
0556     [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x230e4,  /* BR_ISSUED */
0557     [PERF_COUNT_HW_BRANCH_MISSES]       = 0x230e5,  /* BR_MPRED_CR */
0558 };
0559 
0560 #define C(x)    PERF_COUNT_HW_CACHE_##x
0561 
0562 /*
0563  * Table of generalized cache-related events.
0564  * 0 means not supported, -1 means nonsensical, other values
0565  * are event codes.
0566  */
0567 static u64 power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
0568     [C(L1D)] = {        /*  RESULT_ACCESS   RESULT_MISS */
0569         [C(OP_READ)] = {    0x4c1090,   0x3c1088    },
0570         [C(OP_WRITE)] = {   0x3c1090,   0xc10c3     },
0571         [C(OP_PREFETCH)] = {    0xc70e7,    0       },
0572     },
0573     [C(L1I)] = {        /*  RESULT_ACCESS   RESULT_MISS */
0574         [C(OP_READ)] = {    0,      0       },
0575         [C(OP_WRITE)] = {   -1,     -1      },
0576         [C(OP_PREFETCH)] = {    0,      0       },
0577     },
0578     [C(LL)] = {     /*  RESULT_ACCESS   RESULT_MISS */
0579         [C(OP_READ)] = {    0,      0x3c309b    },
0580         [C(OP_WRITE)] = {   0,      0       },
0581         [C(OP_PREFETCH)] = {    0xc50c3,    0       },
0582     },
0583     [C(DTLB)] = {       /*  RESULT_ACCESS   RESULT_MISS */
0584         [C(OP_READ)] = {    0x2c4090,   0x800c4     },
0585         [C(OP_WRITE)] = {   -1,     -1      },
0586         [C(OP_PREFETCH)] = {    -1,     -1      },
0587     },
0588     [C(ITLB)] = {       /*  RESULT_ACCESS   RESULT_MISS */
0589         [C(OP_READ)] = {    0,      0x800c0     },
0590         [C(OP_WRITE)] = {   -1,     -1      },
0591         [C(OP_PREFETCH)] = {    -1,     -1      },
0592     },
0593     [C(BPU)] = {        /*  RESULT_ACCESS   RESULT_MISS */
0594         [C(OP_READ)] = {    0x230e4,    0x230e5     },
0595         [C(OP_WRITE)] = {   -1,     -1      },
0596         [C(OP_PREFETCH)] = {    -1,     -1      },
0597     },
0598     [C(NODE)] = {       /*  RESULT_ACCESS   RESULT_MISS */
0599         [C(OP_READ)] = {    -1,     -1      },
0600         [C(OP_WRITE)] = {   -1,     -1      },
0601         [C(OP_PREFETCH)] = {    -1,     -1      },
0602     },
0603 };
0604 
0605 static struct power_pmu power5_pmu = {
0606     .name           = "POWER5",
0607     .n_counter      = 6,
0608     .max_alternatives   = MAX_ALT,
0609     .add_fields     = 0x7000090000555ul,
0610     .test_adder     = 0x3000490000000ul,
0611     .compute_mmcr       = power5_compute_mmcr,
0612     .get_constraint     = power5_get_constraint,
0613     .get_alternatives   = power5_get_alternatives,
0614     .disable_pmc        = power5_disable_pmc,
0615     .n_generic      = ARRAY_SIZE(power5_generic_events),
0616     .generic_events     = power5_generic_events,
0617     .cache_events       = &power5_cache_events,
0618     .flags          = PPMU_HAS_SSLOT,
0619 };
0620 
0621 int __init init_power5_pmu(void)
0622 {
0623     unsigned int pvr = mfspr(SPRN_PVR);
0624 
0625     if (PVR_VER(pvr) != PVR_POWER5)
0626         return -ENODEV;
0627 
0628     return register_power_pmu(&power5_pmu);
0629 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!