powerpc/perf/power10-pmu.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Performance counter support for POWER10 processors.
0004  *
0005  * Copyright 2020 Madhavan Srinivasan, IBM Corporation.
0006  * Copyright 2020 Athira Rajeev, IBM Corporation.
0007  */
0008
0009 #define pr_fmt(fmt) "power10-pmu: " fmt
0010
0011 #include "isa207-common.h"
0012
0013 /*
0014  * Raw event encoding for Power10:
0015  *
0016  *        60        56        52        48        44        40        36        32
0017  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
0018  *   | | [ ]   [ src_match ] [  src_mask ]   | [ ] [ l2l3_sel ]  [  thresh_ctl   ]
0019  *   | |  |                                  |  |                         |
0020  *   | |  *- IFM (Linux)                     |  |        thresh start/stop -*
0021  *   | *- BHRB (Linux)                       |  src_sel
0022  *   *- EBB (Linux)                          *invert_bit
0023  *
0024  *        28        24        20        16        12         8         4         0
0025  * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
0026  *   [   ] [  sample ]   [ ] [ ]   [ pmc ]   [unit ]   [ ] |  m   [    pmcxsel    ]
0027  *     |        |        |    |                        |   |  |
0028  *     |        |        |    |                        |   |  *- mark
0029  *     |        |        |    *- L1/L2/L3 cache_sel    |   |*-radix_scope_qual
0030  *     |        |        sdar_mode                     |
0031  *     |        *- sampling mode for marked events     *- combine
0032  *     |
0033  *     *- thresh_sel
0034  *
0035  * Below uses IBM bit numbering.
0036  *
0037  * MMCR1[x:y] = unit    (PMCxUNIT)
0038  * MMCR1[24]   = pmc1combine[0]
0039  * MMCR1[25]   = pmc1combine[1]
0040  * MMCR1[26]   = pmc2combine[0]
0041  * MMCR1[27]   = pmc2combine[1]
0042  * MMCR1[28]   = pmc3combine[0]
0043  * MMCR1[29]   = pmc3combine[1]
0044  * MMCR1[30]   = pmc4combine[0]
0045  * MMCR1[31]   = pmc4combine[1]
0046  *
0047  * if pmc == 3 and unit == 0 and pmcxsel[0:6] == 0b0101011
0048  *  MMCR1[20:27] = thresh_ctl
0049  * else if pmc == 4 and unit == 0xf and pmcxsel[0:6] == 0b0101001
0050  *  MMCR1[20:27] = thresh_ctl
0051  * else
0052  *  MMCRA[48:55] = thresh_ctl   (THRESH START/END)
0053  *
0054  * if thresh_sel:
0055  *  MMCRA[45:47] = thresh_sel
0056  *
0057  * if l2l3_sel:
0058  * MMCR2[56:60] = l2l3_sel[0:4]
0059  *
0060  * MMCR1[16] = cache_sel[0]
0061  * MMCR1[17] = cache_sel[1]
0062  * MMCR1[18] = radix_scope_qual
0063  *
0064  * if mark:
0065  *  MMCRA[63]    = 1        (SAMPLE_ENABLE)
0066  *  MMCRA[57:59] = sample[0:2]  (RAND_SAMP_ELIG)
0067  *  MMCRA[61:62] = sample[3:4]  (RAND_SAMP_MODE)
0068  *
0069  * if EBB and BHRB:
0070  *  MMCRA[32:33] = IFM
0071  *
0072  * MMCRA[SDAR_MODE]  = sdar_mode[0:1]
0073  */
0074
0075 /*
0076  * Some power10 event codes.
0077  */
0078 #define EVENT(_name, _code)     enum{_name = _code}
0079
0080 #include "power10-events-list.h"
0081
0082 #undef EVENT
0083
0084 /* MMCRA IFM bits - POWER10 */
0085 #define POWER10_MMCRA_IFM1      0x0000000040000000UL
0086 #define POWER10_MMCRA_IFM2      0x0000000080000000UL
0087 #define POWER10_MMCRA_IFM3      0x00000000C0000000UL
0088 #define POWER10_MMCRA_BHRB_MASK     0x00000000C0000000UL
0089
0090 extern u64 PERF_REG_EXTENDED_MASK;
0091
0092 /* Table of alternatives, sorted by column 0 */
0093 static const unsigned int power10_event_alternatives[][MAX_ALT] = {
0094     { PM_INST_CMPL_ALT,     PM_INST_CMPL },
0095     { PM_CYC_ALT,           PM_CYC },
0096 };
0097
0098 static int power10_get_alternatives(u64 event, unsigned int flags, u64 alt[])
0099 {
0100     int num_alt = 0;
0101
0102     num_alt = isa207_get_alternatives(event, alt,
0103                       ARRAY_SIZE(power10_event_alternatives), flags,
0104                       power10_event_alternatives);
0105
0106     return num_alt;
0107 }
0108
0109 static int power10_check_attr_config(struct perf_event *ev)
0110 {
0111     u64 val;
0112     u64 event = ev->attr.config;
0113
0114     val = (event >> EVENT_SAMPLE_SHIFT) & EVENT_SAMPLE_MASK;
0115     if (val == 0x10 || isa3XX_check_attr_config(ev))
0116         return -EINVAL;
0117
0118     return 0;
0119 }
0120
0121 GENERIC_EVENT_ATTR(cpu-cycles,          PM_CYC);
0122 GENERIC_EVENT_ATTR(instructions,        PM_INST_CMPL);
0123 GENERIC_EVENT_ATTR(branch-instructions,     PM_BR_CMPL);
0124 GENERIC_EVENT_ATTR(branch-misses,       PM_BR_MPRED_CMPL);
0125 GENERIC_EVENT_ATTR(cache-references,        PM_LD_REF_L1);
0126 GENERIC_EVENT_ATTR(cache-misses,        PM_LD_MISS_L1);
0127 GENERIC_EVENT_ATTR(mem-loads,           MEM_LOADS);
0128 GENERIC_EVENT_ATTR(mem-stores,          MEM_STORES);
0129 GENERIC_EVENT_ATTR(branch-instructions,     PM_BR_FIN);
0130 GENERIC_EVENT_ATTR(branch-misses,       PM_MPRED_BR_FIN);
0131 GENERIC_EVENT_ATTR(cache-misses,        PM_LD_DEMAND_MISS_L1_FIN);
0132
0133 CACHE_EVENT_ATTR(L1-dcache-load-misses,     PM_LD_MISS_L1);
0134 CACHE_EVENT_ATTR(L1-dcache-loads,       PM_LD_REF_L1);
0135 CACHE_EVENT_ATTR(L1-dcache-prefetches,      PM_LD_PREFETCH_CACHE_LINE_MISS);
0136 CACHE_EVENT_ATTR(L1-dcache-store-misses,    PM_ST_MISS_L1);
0137 CACHE_EVENT_ATTR(L1-icache-load-misses,     PM_L1_ICACHE_MISS);
0138 CACHE_EVENT_ATTR(L1-icache-loads,       PM_INST_FROM_L1);
0139 CACHE_EVENT_ATTR(L1-icache-prefetches,      PM_IC_PREF_REQ);
0140 CACHE_EVENT_ATTR(LLC-load-misses,       PM_DATA_FROM_L3MISS);
0141 CACHE_EVENT_ATTR(LLC-loads,         PM_DATA_FROM_L3);
0142 CACHE_EVENT_ATTR(LLC-prefetches,        PM_L3_PF_MISS_L3);
0143 CACHE_EVENT_ATTR(LLC-store-misses,      PM_L2_ST_MISS);
0144 CACHE_EVENT_ATTR(LLC-stores,            PM_L2_ST);
0145 CACHE_EVENT_ATTR(branch-load-misses,        PM_BR_MPRED_CMPL);
0146 CACHE_EVENT_ATTR(branch-loads,          PM_BR_CMPL);
0147 CACHE_EVENT_ATTR(dTLB-load-misses,      PM_DTLB_MISS);
0148 CACHE_EVENT_ATTR(iTLB-load-misses,      PM_ITLB_MISS);
0149
0150 static struct attribute *power10_events_attr_dd1[] = {
0151     GENERIC_EVENT_PTR(PM_CYC),
0152     GENERIC_EVENT_PTR(PM_INST_CMPL),
0153     GENERIC_EVENT_PTR(PM_BR_CMPL),
0154     GENERIC_EVENT_PTR(PM_BR_MPRED_CMPL),
0155     GENERIC_EVENT_PTR(PM_LD_REF_L1),
0156     GENERIC_EVENT_PTR(PM_LD_MISS_L1),
0157     GENERIC_EVENT_PTR(MEM_LOADS),
0158     GENERIC_EVENT_PTR(MEM_STORES),
0159     CACHE_EVENT_PTR(PM_LD_MISS_L1),
0160     CACHE_EVENT_PTR(PM_LD_REF_L1),
0161     CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
0162     CACHE_EVENT_PTR(PM_ST_MISS_L1),
0163     CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
0164     CACHE_EVENT_PTR(PM_INST_FROM_L1),
0165     CACHE_EVENT_PTR(PM_IC_PREF_REQ),
0166     CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
0167     CACHE_EVENT_PTR(PM_DATA_FROM_L3),
0168     CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
0169     CACHE_EVENT_PTR(PM_BR_CMPL),
0170     CACHE_EVENT_PTR(PM_DTLB_MISS),
0171     CACHE_EVENT_PTR(PM_ITLB_MISS),
0172     NULL
0173 };
0174
0175 static struct attribute *power10_events_attr[] = {
0176     GENERIC_EVENT_PTR(PM_CYC),
0177     GENERIC_EVENT_PTR(PM_INST_CMPL),
0178     GENERIC_EVENT_PTR(PM_BR_FIN),
0179     GENERIC_EVENT_PTR(PM_MPRED_BR_FIN),
0180     GENERIC_EVENT_PTR(PM_LD_REF_L1),
0181     GENERIC_EVENT_PTR(PM_LD_DEMAND_MISS_L1_FIN),
0182     GENERIC_EVENT_PTR(MEM_LOADS),
0183     GENERIC_EVENT_PTR(MEM_STORES),
0184     CACHE_EVENT_PTR(PM_LD_MISS_L1),
0185     CACHE_EVENT_PTR(PM_LD_REF_L1),
0186     CACHE_EVENT_PTR(PM_LD_PREFETCH_CACHE_LINE_MISS),
0187     CACHE_EVENT_PTR(PM_ST_MISS_L1),
0188     CACHE_EVENT_PTR(PM_L1_ICACHE_MISS),
0189     CACHE_EVENT_PTR(PM_INST_FROM_L1),
0190     CACHE_EVENT_PTR(PM_IC_PREF_REQ),
0191     CACHE_EVENT_PTR(PM_DATA_FROM_L3MISS),
0192     CACHE_EVENT_PTR(PM_DATA_FROM_L3),
0193     CACHE_EVENT_PTR(PM_L3_PF_MISS_L3),
0194     CACHE_EVENT_PTR(PM_L2_ST_MISS),
0195     CACHE_EVENT_PTR(PM_L2_ST),
0196     CACHE_EVENT_PTR(PM_BR_MPRED_CMPL),
0197     CACHE_EVENT_PTR(PM_BR_CMPL),
0198     CACHE_EVENT_PTR(PM_DTLB_MISS),
0199     CACHE_EVENT_PTR(PM_ITLB_MISS),
0200     NULL
0201 };
0202
0203 static const struct attribute_group power10_pmu_events_group_dd1 = {
0204     .name = "events",
0205     .attrs = power10_events_attr_dd1,
0206 };
0207
0208 static const struct attribute_group power10_pmu_events_group = {
0209     .name = "events",
0210     .attrs = power10_events_attr,
0211 };
0212
0213 PMU_FORMAT_ATTR(event,          "config:0-59");
0214 PMU_FORMAT_ATTR(pmcxsel,        "config:0-7");
0215 PMU_FORMAT_ATTR(mark,           "config:8");
0216 PMU_FORMAT_ATTR(combine,        "config:10-11");
0217 PMU_FORMAT_ATTR(unit,           "config:12-15");
0218 PMU_FORMAT_ATTR(pmc,            "config:16-19");
0219 PMU_FORMAT_ATTR(cache_sel,      "config:20-21");
0220 PMU_FORMAT_ATTR(sdar_mode,      "config:22-23");
0221 PMU_FORMAT_ATTR(sample_mode,    "config:24-28");
0222 PMU_FORMAT_ATTR(thresh_sel,     "config:29-31");
0223 PMU_FORMAT_ATTR(thresh_stop,    "config:32-35");
0224 PMU_FORMAT_ATTR(thresh_start,   "config:36-39");
0225 PMU_FORMAT_ATTR(l2l3_sel,       "config:40-44");
0226 PMU_FORMAT_ATTR(src_sel,        "config:45-46");
0227 PMU_FORMAT_ATTR(invert_bit,     "config:47");
0228 PMU_FORMAT_ATTR(src_mask,       "config:48-53");
0229 PMU_FORMAT_ATTR(src_match,      "config:54-59");
0230 PMU_FORMAT_ATTR(radix_scope,    "config:9");
0231 PMU_FORMAT_ATTR(thresh_cmp,     "config1:0-17");
0232
0233 static struct attribute *power10_pmu_format_attr[] = {
0234     &format_attr_event.attr,
0235     &format_attr_pmcxsel.attr,
0236     &format_attr_mark.attr,
0237     &format_attr_combine.attr,
0238     &format_attr_unit.attr,
0239     &format_attr_pmc.attr,
0240     &format_attr_cache_sel.attr,
0241     &format_attr_sdar_mode.attr,
0242     &format_attr_sample_mode.attr,
0243     &format_attr_thresh_sel.attr,
0244     &format_attr_thresh_stop.attr,
0245     &format_attr_thresh_start.attr,
0246     &format_attr_l2l3_sel.attr,
0247     &format_attr_src_sel.attr,
0248     &format_attr_invert_bit.attr,
0249     &format_attr_src_mask.attr,
0250     &format_attr_src_match.attr,
0251     &format_attr_radix_scope.attr,
0252     &format_attr_thresh_cmp.attr,
0253     NULL,
0254 };
0255
0256 static const struct attribute_group power10_pmu_format_group = {
0257     .name = "format",
0258     .attrs = power10_pmu_format_attr,
0259 };
0260
0261 static struct attribute *power10_pmu_caps_attrs[] = {
0262     NULL
0263 };
0264
0265 static struct attribute_group power10_pmu_caps_group = {
0266     .name  = "caps",
0267     .attrs = power10_pmu_caps_attrs,
0268 };
0269
0270 static const struct attribute_group *power10_pmu_attr_groups_dd1[] = {
0271     &power10_pmu_format_group,
0272     &power10_pmu_events_group_dd1,
0273     &power10_pmu_caps_group,
0274     NULL,
0275 };
0276
0277 static const struct attribute_group *power10_pmu_attr_groups[] = {
0278     &power10_pmu_format_group,
0279     &power10_pmu_events_group,
0280     &power10_pmu_caps_group,
0281     NULL,
0282 };
0283
0284 static int power10_generic_events_dd1[] = {
0285     [PERF_COUNT_HW_CPU_CYCLES] =            PM_CYC,
0286     [PERF_COUNT_HW_INSTRUCTIONS] =          PM_INST_CMPL,
0287     [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =       PM_BR_CMPL,
0288     [PERF_COUNT_HW_BRANCH_MISSES] =         PM_BR_MPRED_CMPL,
0289     [PERF_COUNT_HW_CACHE_REFERENCES] =      PM_LD_REF_L1,
0290     [PERF_COUNT_HW_CACHE_MISSES] =          PM_LD_MISS_L1,
0291 };
0292
0293 static int power10_generic_events[] = {
0294     [PERF_COUNT_HW_CPU_CYCLES] =            PM_CYC,
0295     [PERF_COUNT_HW_INSTRUCTIONS] =          PM_INST_CMPL,
0296     [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] =       PM_BR_FIN,
0297     [PERF_COUNT_HW_BRANCH_MISSES] =         PM_MPRED_BR_FIN,
0298     [PERF_COUNT_HW_CACHE_REFERENCES] =      PM_LD_REF_L1,
0299     [PERF_COUNT_HW_CACHE_MISSES] =          PM_LD_DEMAND_MISS_L1_FIN,
0300 };
0301
0302 static u64 power10_bhrb_filter_map(u64 branch_sample_type)
0303 {
0304     u64 pmu_bhrb_filter = 0;
0305
0306     /* BHRB and regular PMU events share the same privilege state
0307      * filter configuration. BHRB is always recorded along with a
0308      * regular PMU event. As the privilege state filter is handled
0309      * in the basic PMC configuration of the accompanying regular
0310      * PMU event, we ignore any separate BHRB specific request.
0311      */
0312
0313     /* No branch filter requested */
0314     if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY)
0315         return pmu_bhrb_filter;
0316
0317     /* Invalid branch filter options - HW does not support */
0318     if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_RETURN)
0319         return -1;
0320
0321     if (branch_sample_type & PERF_SAMPLE_BRANCH_IND_CALL) {
0322         pmu_bhrb_filter |= POWER10_MMCRA_IFM2;
0323         return pmu_bhrb_filter;
0324     }
0325
0326     if (branch_sample_type & PERF_SAMPLE_BRANCH_COND) {
0327         pmu_bhrb_filter |= POWER10_MMCRA_IFM3;
0328         return pmu_bhrb_filter;
0329     }
0330
0331     if (branch_sample_type & PERF_SAMPLE_BRANCH_CALL)
0332         return -1;
0333
0334     if (branch_sample_type & PERF_SAMPLE_BRANCH_ANY_CALL) {
0335         pmu_bhrb_filter |= POWER10_MMCRA_IFM1;
0336         return pmu_bhrb_filter;
0337     }
0338
0339     /* Every thing else is unsupported */
0340     return -1;
0341 }
0342
0343 static void power10_config_bhrb(u64 pmu_bhrb_filter)
0344 {
0345     pmu_bhrb_filter &= POWER10_MMCRA_BHRB_MASK;
0346
0347     /* Enable BHRB filter in PMU */
0348     mtspr(SPRN_MMCRA, (mfspr(SPRN_MMCRA) | pmu_bhrb_filter));
0349 }
0350
0351 #define C(x)    PERF_COUNT_HW_CACHE_##x
0352
0353 /*
0354  * Table of generalized cache-related events.
0355  * 0 means not supported, -1 means nonsensical, other values
0356  * are event codes.
0357  */
0358 static u64 power10_cache_events_dd1[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
0359     [C(L1D)] = {
0360         [C(OP_READ)] = {
0361             [C(RESULT_ACCESS)] = PM_LD_REF_L1,
0362             [C(RESULT_MISS)] = PM_LD_MISS_L1,
0363         },
0364         [C(OP_WRITE)] = {
0365             [C(RESULT_ACCESS)] = 0,
0366             [C(RESULT_MISS)] = PM_ST_MISS_L1,
0367         },
0368         [C(OP_PREFETCH)] = {
0369             [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
0370             [C(RESULT_MISS)] = 0,
0371         },
0372     },
0373     [C(L1I)] = {
0374         [C(OP_READ)] = {
0375             [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
0376             [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
0377         },
0378         [C(OP_WRITE)] = {
0379             [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
0380             [C(RESULT_MISS)] = -1,
0381         },
0382         [C(OP_PREFETCH)] = {
0383             [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
0384             [C(RESULT_MISS)] = 0,
0385         },
0386     },
0387     [C(LL)] = {
0388         [C(OP_READ)] = {
0389             [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
0390             [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
0391         },
0392         [C(OP_WRITE)] = {
0393             [C(RESULT_ACCESS)] = -1,
0394             [C(RESULT_MISS)] = -1,
0395         },
0396         [C(OP_PREFETCH)] = {
0397             [C(RESULT_ACCESS)] = -1,
0398             [C(RESULT_MISS)] = 0,
0399         },
0400     },
0401      [C(DTLB)] = {
0402         [C(OP_READ)] = {
0403             [C(RESULT_ACCESS)] = 0,
0404             [C(RESULT_MISS)] = PM_DTLB_MISS,
0405         },
0406         [C(OP_WRITE)] = {
0407             [C(RESULT_ACCESS)] = -1,
0408             [C(RESULT_MISS)] = -1,
0409         },
0410         [C(OP_PREFETCH)] = {
0411             [C(RESULT_ACCESS)] = -1,
0412             [C(RESULT_MISS)] = -1,
0413         },
0414     },
0415     [C(ITLB)] = {
0416         [C(OP_READ)] = {
0417             [C(RESULT_ACCESS)] = 0,
0418             [C(RESULT_MISS)] = PM_ITLB_MISS,
0419         },
0420         [C(OP_WRITE)] = {
0421             [C(RESULT_ACCESS)] = -1,
0422             [C(RESULT_MISS)] = -1,
0423         },
0424         [C(OP_PREFETCH)] = {
0425             [C(RESULT_ACCESS)] = -1,
0426             [C(RESULT_MISS)] = -1,
0427         },
0428     },
0429     [C(BPU)] = {
0430         [C(OP_READ)] = {
0431             [C(RESULT_ACCESS)] = PM_BR_CMPL,
0432             [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
0433         },
0434         [C(OP_WRITE)] = {
0435             [C(RESULT_ACCESS)] = -1,
0436             [C(RESULT_MISS)] = -1,
0437         },
0438         [C(OP_PREFETCH)] = {
0439             [C(RESULT_ACCESS)] = -1,
0440             [C(RESULT_MISS)] = -1,
0441         },
0442     },
0443     [C(NODE)] = {
0444         [C(OP_READ)] = {
0445             [C(RESULT_ACCESS)] = -1,
0446             [C(RESULT_MISS)] = -1,
0447         },
0448         [C(OP_WRITE)] = {
0449             [C(RESULT_ACCESS)] = -1,
0450             [C(RESULT_MISS)] = -1,
0451         },
0452         [C(OP_PREFETCH)] = {
0453             [C(RESULT_ACCESS)] = -1,
0454             [C(RESULT_MISS)] = -1,
0455         },
0456     },
0457 };
0458
0459 static u64 power10_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
0460     [C(L1D)] = {
0461         [C(OP_READ)] = {
0462             [C(RESULT_ACCESS)] = PM_LD_REF_L1,
0463             [C(RESULT_MISS)] = PM_LD_MISS_L1,
0464         },
0465         [C(OP_WRITE)] = {
0466             [C(RESULT_ACCESS)] = 0,
0467             [C(RESULT_MISS)] = PM_ST_MISS_L1,
0468         },
0469         [C(OP_PREFETCH)] = {
0470             [C(RESULT_ACCESS)] = PM_LD_PREFETCH_CACHE_LINE_MISS,
0471             [C(RESULT_MISS)] = 0,
0472         },
0473     },
0474     [C(L1I)] = {
0475         [C(OP_READ)] = {
0476             [C(RESULT_ACCESS)] = PM_INST_FROM_L1,
0477             [C(RESULT_MISS)] = PM_L1_ICACHE_MISS,
0478         },
0479         [C(OP_WRITE)] = {
0480             [C(RESULT_ACCESS)] = PM_INST_FROM_L1MISS,
0481             [C(RESULT_MISS)] = -1,
0482         },
0483         [C(OP_PREFETCH)] = {
0484             [C(RESULT_ACCESS)] = PM_IC_PREF_REQ,
0485             [C(RESULT_MISS)] = 0,
0486         },
0487     },
0488     [C(LL)] = {
0489         [C(OP_READ)] = {
0490             [C(RESULT_ACCESS)] = PM_DATA_FROM_L3,
0491             [C(RESULT_MISS)] = PM_DATA_FROM_L3MISS,
0492         },
0493         [C(OP_WRITE)] = {
0494             [C(RESULT_ACCESS)] = PM_L2_ST,
0495             [C(RESULT_MISS)] = PM_L2_ST_MISS,
0496         },
0497         [C(OP_PREFETCH)] = {
0498             [C(RESULT_ACCESS)] = PM_L3_PF_MISS_L3,
0499             [C(RESULT_MISS)] = 0,
0500         },
0501     },
0502      [C(DTLB)] = {
0503         [C(OP_READ)] = {
0504             [C(RESULT_ACCESS)] = 0,
0505             [C(RESULT_MISS)] = PM_DTLB_MISS,
0506         },
0507         [C(OP_WRITE)] = {
0508             [C(RESULT_ACCESS)] = -1,
0509             [C(RESULT_MISS)] = -1,
0510         },
0511         [C(OP_PREFETCH)] = {
0512             [C(RESULT_ACCESS)] = -1,
0513             [C(RESULT_MISS)] = -1,
0514         },
0515     },
0516     [C(ITLB)] = {
0517         [C(OP_READ)] = {
0518             [C(RESULT_ACCESS)] = 0,
0519             [C(RESULT_MISS)] = PM_ITLB_MISS,
0520         },
0521         [C(OP_WRITE)] = {
0522             [C(RESULT_ACCESS)] = -1,
0523             [C(RESULT_MISS)] = -1,
0524         },
0525         [C(OP_PREFETCH)] = {
0526             [C(RESULT_ACCESS)] = -1,
0527             [C(RESULT_MISS)] = -1,
0528         },
0529     },
0530     [C(BPU)] = {
0531         [C(OP_READ)] = {
0532             [C(RESULT_ACCESS)] = PM_BR_CMPL,
0533             [C(RESULT_MISS)] = PM_BR_MPRED_CMPL,
0534         },
0535         [C(OP_WRITE)] = {
0536             [C(RESULT_ACCESS)] = -1,
0537             [C(RESULT_MISS)] = -1,
0538         },
0539         [C(OP_PREFETCH)] = {
0540             [C(RESULT_ACCESS)] = -1,
0541             [C(RESULT_MISS)] = -1,
0542         },
0543     },
0544     [C(NODE)] = {
0545         [C(OP_READ)] = {
0546             [C(RESULT_ACCESS)] = -1,
0547             [C(RESULT_MISS)] = -1,
0548         },
0549         [C(OP_WRITE)] = {
0550             [C(RESULT_ACCESS)] = -1,
0551             [C(RESULT_MISS)] = -1,
0552         },
0553         [C(OP_PREFETCH)] = {
0554             [C(RESULT_ACCESS)] = -1,
0555             [C(RESULT_MISS)] = -1,
0556         },
0557     },
0558 };
0559
0560 #undef C
0561
0562 /*
0563  * Set the MMCR0[CC56RUN] bit to enable counting for
0564  * PMC5 and PMC6 regardless of the state of CTRL[RUN],
0565  * so that we can use counters 5 and 6 as PM_INST_CMPL and
0566  * PM_CYC.
0567  */
0568 static int power10_compute_mmcr(u64 event[], int n_ev,
0569                 unsigned int hwc[], struct mmcr_regs *mmcr,
0570                 struct perf_event *pevents[], u32 flags)
0571 {
0572     int ret;
0573
0574     ret = isa207_compute_mmcr(event, n_ev, hwc, mmcr, pevents, flags);
0575     if (!ret)
0576         mmcr->mmcr0 |= MMCR0_C56RUN;
0577     return ret;
0578 }
0579
0580 static struct power_pmu power10_pmu = {
0581     .name           = "POWER10",
0582     .n_counter      = MAX_PMU_COUNTERS,
0583     .add_fields     = ISA207_ADD_FIELDS,
0584     .test_adder     = ISA207_TEST_ADDER,
0585     .group_constraint_mask  = CNST_CACHE_PMC4_MASK,
0586     .group_constraint_val   = CNST_CACHE_PMC4_VAL,
0587     .compute_mmcr       = power10_compute_mmcr,
0588     .config_bhrb        = power10_config_bhrb,
0589     .bhrb_filter_map    = power10_bhrb_filter_map,
0590     .get_constraint     = isa207_get_constraint,
0591     .get_alternatives   = power10_get_alternatives,
0592     .get_mem_data_src   = isa207_get_mem_data_src,
0593     .get_mem_weight     = isa207_get_mem_weight,
0594     .disable_pmc        = isa207_disable_pmc,
0595     .flags          = PPMU_HAS_SIER | PPMU_ARCH_207S |
0596                   PPMU_ARCH_31 | PPMU_HAS_ATTR_CONFIG1,
0597     .n_generic      = ARRAY_SIZE(power10_generic_events),
0598     .generic_events     = power10_generic_events,
0599     .cache_events       = &power10_cache_events,
0600     .attr_groups        = power10_pmu_attr_groups,
0601     .bhrb_nr        = 32,
0602     .capabilities           = PERF_PMU_CAP_EXTENDED_REGS,
0603     .check_attr_config  = power10_check_attr_config,
0604 };
0605
0606 int __init init_power10_pmu(void)
0607 {
0608     unsigned int pvr;
0609     int rc;
0610
0611     pvr = mfspr(SPRN_PVR);
0612     if (PVR_VER(pvr) != PVR_POWER10)
0613         return -ENODEV;
0614
0615     /* Add the ppmu flag for power10 DD1 */
0616     if ((PVR_CFG(pvr) == 1))
0617         power10_pmu.flags |= PPMU_P10_DD1;
0618
0619     /* Set the PERF_REG_EXTENDED_MASK here */
0620     PERF_REG_EXTENDED_MASK = PERF_REG_PMU_MASK_31;
0621
0622     if ((PVR_CFG(pvr) == 1)) {
0623         power10_pmu.generic_events = power10_generic_events_dd1;
0624         power10_pmu.attr_groups = power10_pmu_attr_groups_dd1;
0625         power10_pmu.cache_events = &power10_cache_events_dd1;
0626     }
0627
0628     rc = register_power_pmu(&power10_pmu);
0629     if (rc)
0630         return rc;
0631
0632     /* Tell userspace that EBB is supported */
0633     cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_EBB;
0634
0635     return 0;
0636 }