powerpc/perf/power10-events-list.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Performance counter support for POWER10 processors.
0004  *
0005  * Copyright 2020 Madhavan Srinivasan, IBM Corporation.
0006  * Copyright 2020 Athira Rajeev, IBM Corporation.
0007  */
0008
0009 /*
0010  * Power10 event codes.
0011  */
0012 EVENT(PM_CYC,               0x600f4);
0013 EVENT(PM_DISP_STALL_CYC,            0x100f8);
0014 EVENT(PM_EXEC_STALL,                0x30008);
0015 EVENT(PM_INST_CMPL,             0x500fa);
0016 EVENT(PM_BR_CMPL,                               0x4d05e);
0017 EVENT(PM_BR_MPRED_CMPL,                         0x400f6);
0018 EVENT(PM_BR_FIN,                0x2f04a);
0019 EVENT(PM_MPRED_BR_FIN,              0x3e098);
0020 EVENT(PM_LD_DEMAND_MISS_L1_FIN,         0x400f0);
0021
0022 /* All L1 D cache load references counted at finish, gated by reject */
0023 EVENT(PM_LD_REF_L1,             0x100fc);
0024 /* Load Missed L1 */
0025 EVENT(PM_LD_MISS_L1,                0x3e054);
0026 /* Store Missed L1 */
0027 EVENT(PM_ST_MISS_L1,                0x300f0);
0028 /* L1 cache data prefetches */
0029 EVENT(PM_LD_PREFETCH_CACHE_LINE_MISS,       0x1002c);
0030 /* Demand iCache Miss */
0031 EVENT(PM_L1_ICACHE_MISS,            0x200fc);
0032 /* Instruction fetches from L1 */
0033 EVENT(PM_INST_FROM_L1,              0x04080);
0034 /* Instruction Demand sectors wriittent into IL1 */
0035 EVENT(PM_INST_FROM_L1MISS,          0x03f00000001c040);
0036 /* Instruction prefetch written into IL1 */
0037 EVENT(PM_IC_PREF_REQ,               0x040a0);
0038 /* The data cache was reloaded from local core's L3 due to a demand load */
0039 EVENT(PM_DATA_FROM_L3,              0x01340000001c040);
0040 /* Demand LD - L3 Miss (not L2 hit and not L3 hit) */
0041 EVENT(PM_DATA_FROM_L3MISS,          0x300fe);
0042 /* All successful D-side store dispatches for this thread */
0043 EVENT(PM_L2_ST,                 0x010000046080);
0044 /* All successful D-side store dispatches for this thread that were L2 Miss */
0045 EVENT(PM_L2_ST_MISS,                0x26880);
0046 /* Total HW L3 prefetches(Load+store) */
0047 EVENT(PM_L3_PF_MISS_L3,             0x100000016080);
0048 /* Data PTEG reload */
0049 EVENT(PM_DTLB_MISS,             0x300fc);
0050 /* ITLB Reloaded */
0051 EVENT(PM_ITLB_MISS,             0x400fc);
0052
0053 EVENT(PM_CYC_ALT,               0x0001e);
0054 EVENT(PM_INST_CMPL_ALT,             0x00002);
0055
0056 /*
0057  * Memory Access Events
0058  *
0059  * Primary PMU event used here is PM_MRK_INST_CMPL (0x401e0)
0060  * To enable capturing of memory profiling, these MMCRA bits
0061  * needs to be programmed and corresponding raw event format
0062  * encoding.
0063  *
0064  * MMCRA bits encoding needed are
0065  *     SM (Sampling Mode)
0066  *     EM (Eligibility for Random Sampling)
0067  *     TECE (Threshold Event Counter Event)
0068  *     TS (Threshold Start Event)
0069  *     TE (Threshold End Event)
0070  *
0071  * Corresponding Raw Encoding bits:
0072  *     sample [EM,SM]
0073  *     thresh_sel (TECE)
0074  *     thresh start (TS)
0075  *     thresh end (TE)
0076  */
0077
0078 EVENT(MEM_LOADS,                0x35340401e0);
0079 EVENT(MEM_STORES,               0x353c0401e0);