powerpc/mm/mmu_context.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Common implementation of switch_mm_irqs_off
0004  *
0005  *  Copyright IBM Corp. 2017
0006  */
0007
0008 #include <linux/mm.h>
0009 #include <linux/cpu.h>
0010 #include <linux/sched/mm.h>
0011
0012 #include <asm/mmu_context.h>
0013 #include <asm/pgalloc.h>
0014
0015 #if defined(CONFIG_PPC32)
0016 static inline void switch_mm_pgdir(struct task_struct *tsk,
0017                    struct mm_struct *mm)
0018 {
0019     /* 32-bit keeps track of the current PGDIR in the thread struct */
0020     tsk->thread.pgdir = mm->pgd;
0021 #ifdef CONFIG_PPC_BOOK3S_32
0022     tsk->thread.sr0 = mm->context.sr0;
0023 #endif
0024 #if defined(CONFIG_BOOKE_OR_40x) && defined(CONFIG_PPC_KUAP)
0025     tsk->thread.pid = mm->context.id;
0026 #endif
0027 }
0028 #elif defined(CONFIG_PPC_BOOK3E_64)
0029 static inline void switch_mm_pgdir(struct task_struct *tsk,
0030                    struct mm_struct *mm)
0031 {
0032     /* 64-bit Book3E keeps track of current PGD in the PACA */
0033     get_paca()->pgd = mm->pgd;
0034 #ifdef CONFIG_PPC_KUAP
0035     tsk->thread.pid = mm->context.id;
0036 #endif
0037 }
0038 #else
0039 static inline void switch_mm_pgdir(struct task_struct *tsk,
0040                    struct mm_struct *mm) { }
0041 #endif
0042
0043 void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
0044             struct task_struct *tsk)
0045 {
0046     bool new_on_cpu = false;
0047
0048     /* Mark this context has been used on the new CPU */
0049     if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
0050         cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
0051         inc_mm_active_cpus(next);
0052
0053         /*
0054          * This full barrier orders the store to the cpumask above vs
0055          * a subsequent load which allows this CPU/MMU to begin loading
0056          * translations for 'next' from page table PTEs into the TLB.
0057          *
0058          * When using the radix MMU, that operation is the load of the
0059          * MMU context id, which is then moved to SPRN_PID.
0060          *
0061          * For the hash MMU it is either the first load from slb_cache
0062          * in switch_slb() to preload the SLBs, or the load of
0063          * get_user_context which loads the context for the VSID hash
0064          * to insert a new SLB, in the SLB fault handler.
0065          *
0066          * On the other side, the barrier is in mm/tlb-radix.c for
0067          * radix which orders earlier stores to clear the PTEs before
0068          * the load of mm_cpumask to check which CPU TLBs should be
0069          * flushed. For hash, pte_xchg to clear the PTE includes the
0070          * barrier.
0071          *
0072          * This full barrier is also needed by membarrier when
0073          * switching between processes after store to rq->curr, before
0074          * user-space memory accesses.
0075          */
0076         smp_mb();
0077
0078         new_on_cpu = true;
0079     }
0080
0081     /* Some subarchs need to track the PGD elsewhere */
0082     switch_mm_pgdir(tsk, next);
0083
0084     /* Nothing else to do if we aren't actually switching */
0085     if (prev == next)
0086         return;
0087
0088     /*
0089      * We must stop all altivec streams before changing the HW
0090      * context
0091      */
0092     if (cpu_has_feature(CPU_FTR_ALTIVEC))
0093         asm volatile (PPC_DSSALL);
0094
0095     if (!new_on_cpu)
0096         membarrier_arch_switch_mm(prev, next, tsk);
0097
0098     /*
0099      * The actual HW switching method differs between the various
0100      * sub architectures. Out of line for now
0101      */
0102     switch_mmu_context(prev, next, tsk);
0103 }
0104
0105 #ifndef CONFIG_PPC_BOOK3S_64
0106 void arch_exit_mmap(struct mm_struct *mm)
0107 {
0108     void *frag = pte_frag_get(&mm->context);
0109
0110     if (frag)
0111         pte_frag_destroy(frag);
0112 }
0113 #endif