mm/book3s32/mmu.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * This file contains the routines for handling the MMU on those
0004  * PowerPC implementations where the MMU substantially follows the
0005  * architecture specification.  This includes the 6xx, 7xx, 7xxx,
0006  * and 8260 implementations but excludes the 8xx and 4xx.
0007  *  -- paulus
0008  *
0009  *  Derived from arch/ppc/mm/init.c:
0010  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
0011  *
0012  *  Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
0013  *  and Cort Dougan (PReP) (cort@cs.nmt.edu)
0014  *    Copyright (C) 1996 Paul Mackerras
0015  *
0016  *  Derived from "arch/i386/mm/init.c"
0017  *    Copyright (C) 1991, 1992, 1993, 1994  Linus Torvalds
0018  */
0019
0020 #include <linux/kernel.h>
0021 #include <linux/mm.h>
0022 #include <linux/init.h>
0023 #include <linux/highmem.h>
0024 #include <linux/memblock.h>
0025
0026 #include <asm/mmu.h>
0027 #include <asm/machdep.h>
0028 #include <asm/code-patching.h>
0029 #include <asm/sections.h>
0030
0031 #include <mm/mmu_decl.h>
0032
0033 u8 __initdata early_hash[SZ_256K] __aligned(SZ_256K) = {0};
0034
0035 static struct hash_pte __initdata *Hash = (struct hash_pte *)early_hash;
0036 static unsigned long __initdata Hash_size, Hash_mask;
0037 static unsigned int __initdata hash_mb, hash_mb2;
0038 unsigned long __initdata _SDR1;
0039
0040 struct ppc_bat BATS[8][2];  /* 8 pairs of IBAT, DBAT */
0041
0042 static struct batrange {    /* stores address ranges mapped by BATs */
0043     unsigned long start;
0044     unsigned long limit;
0045     phys_addr_t phys;
0046 } bat_addrs[8];
0047
0048 #ifdef CONFIG_SMP
0049 unsigned long mmu_hash_lock;
0050 #endif
0051
0052 /*
0053  * Return PA for this VA if it is mapped by a BAT, or 0
0054  */
0055 phys_addr_t v_block_mapped(unsigned long va)
0056 {
0057     int b;
0058     for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
0059         if (va >= bat_addrs[b].start && va < bat_addrs[b].limit)
0060             return bat_addrs[b].phys + (va - bat_addrs[b].start);
0061     return 0;
0062 }
0063
0064 /*
0065  * Return VA for a given PA or 0 if not mapped
0066  */
0067 unsigned long p_block_mapped(phys_addr_t pa)
0068 {
0069     int b;
0070     for (b = 0; b < ARRAY_SIZE(bat_addrs); ++b)
0071         if (pa >= bat_addrs[b].phys
0072                 && pa < (bat_addrs[b].limit-bat_addrs[b].start)
0073                       +bat_addrs[b].phys)
0074             return bat_addrs[b].start+(pa-bat_addrs[b].phys);
0075     return 0;
0076 }
0077
0078 int __init find_free_bat(void)
0079 {
0080     int b;
0081     int n = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
0082
0083     for (b = 0; b < n; b++) {
0084         struct ppc_bat *bat = BATS[b];
0085
0086         if (!(bat[1].batu & 3))
0087             return b;
0088     }
0089     return -1;
0090 }
0091
0092 /*
0093  * This function calculates the size of the larger block usable to map the
0094  * beginning of an area based on the start address and size of that area:
0095  * - max block size is 256 on 6xx.
0096  * - base address must be aligned to the block size. So the maximum block size
0097  *   is identified by the lowest bit set to 1 in the base address (for instance
0098  *   if base is 0x16000000, max size is 0x02000000).
0099  * - block size has to be a power of two. This is calculated by finding the
0100  *   highest bit set to 1.
0101  */
0102 unsigned int bat_block_size(unsigned long base, unsigned long top)
0103 {
0104     unsigned int max_size = SZ_256M;
0105     unsigned int base_shift = (ffs(base) - 1) & 31;
0106     unsigned int block_shift = (fls(top - base) - 1) & 31;
0107
0108     return min3(max_size, 1U << base_shift, 1U << block_shift);
0109 }
0110
0111 /*
0112  * Set up one of the IBAT (block address translation) register pairs.
0113  * The parameters are not checked; in particular size must be a power
0114  * of 2 between 128k and 256M.
0115  */
0116 static void setibat(int index, unsigned long virt, phys_addr_t phys,
0117             unsigned int size, pgprot_t prot)
0118 {
0119     unsigned int bl = (size >> 17) - 1;
0120     int wimgxpp;
0121     struct ppc_bat *bat = BATS[index];
0122     unsigned long flags = pgprot_val(prot);
0123
0124     if (!cpu_has_feature(CPU_FTR_NEED_COHERENT))
0125         flags &= ~_PAGE_COHERENT;
0126
0127     wimgxpp = (flags & _PAGE_COHERENT) | (_PAGE_EXEC ? BPP_RX : BPP_XX);
0128     bat[0].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
0129     bat[0].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
0130     if (flags & _PAGE_USER)
0131         bat[0].batu |= 1;   /* Vp = 1 */
0132 }
0133
0134 static void clearibat(int index)
0135 {
0136     struct ppc_bat *bat = BATS[index];
0137
0138     bat[0].batu = 0;
0139     bat[0].batl = 0;
0140 }
0141
0142 static unsigned long __init __mmu_mapin_ram(unsigned long base, unsigned long top)
0143 {
0144     int idx;
0145
0146     while ((idx = find_free_bat()) != -1 && base != top) {
0147         unsigned int size = bat_block_size(base, top);
0148
0149         if (size < 128 << 10)
0150             break;
0151         setbat(idx, PAGE_OFFSET + base, base, size, PAGE_KERNEL_X);
0152         base += size;
0153     }
0154
0155     return base;
0156 }
0157
0158 unsigned long __init mmu_mapin_ram(unsigned long base, unsigned long top)
0159 {
0160     unsigned long done;
0161     unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
0162     unsigned long size;
0163
0164     size = roundup_pow_of_two((unsigned long)_einittext - PAGE_OFFSET);
0165     setibat(0, PAGE_OFFSET, 0, size, PAGE_KERNEL_X);
0166
0167     if (debug_pagealloc_enabled_or_kfence()) {
0168         pr_debug_once("Read-Write memory mapped without BATs\n");
0169         if (base >= border)
0170             return base;
0171         if (top >= border)
0172             top = border;
0173     }
0174
0175     if (!strict_kernel_rwx_enabled() || base >= border || top <= border)
0176         return __mmu_mapin_ram(base, top);
0177
0178     done = __mmu_mapin_ram(base, border);
0179     if (done != border)
0180         return done;
0181
0182     return __mmu_mapin_ram(border, top);
0183 }
0184
0185 static bool is_module_segment(unsigned long addr)
0186 {
0187     if (!IS_ENABLED(CONFIG_MODULES))
0188         return false;
0189     if (addr < ALIGN_DOWN(MODULES_VADDR, SZ_256M))
0190         return false;
0191     if (addr > ALIGN(MODULES_END, SZ_256M) - 1)
0192         return false;
0193     return true;
0194 }
0195
0196 void mmu_mark_initmem_nx(void)
0197 {
0198     int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
0199     int i;
0200     unsigned long base = (unsigned long)_stext - PAGE_OFFSET;
0201     unsigned long top = ALIGN((unsigned long)_etext - PAGE_OFFSET, SZ_128K);
0202     unsigned long border = (unsigned long)__init_begin - PAGE_OFFSET;
0203     unsigned long size;
0204
0205     for (i = 0; i < nb - 1 && base < top;) {
0206         size = bat_block_size(base, top);
0207         setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
0208         base += size;
0209     }
0210     if (base < top) {
0211         size = bat_block_size(base, top);
0212         if ((top - base) > size) {
0213             size <<= 1;
0214             if (strict_kernel_rwx_enabled() && base + size > border)
0215                 pr_warn("Some RW data is getting mapped X. "
0216                     "Adjust CONFIG_DATA_SHIFT to avoid that.\n");
0217         }
0218         setibat(i++, PAGE_OFFSET + base, base, size, PAGE_KERNEL_TEXT);
0219         base += size;
0220     }
0221     for (; i < nb; i++)
0222         clearibat(i);
0223
0224     update_bats();
0225
0226     for (i = TASK_SIZE >> 28; i < 16; i++) {
0227         /* Do not set NX on VM space for modules */
0228         if (is_module_segment(i << 28))
0229             continue;
0230
0231         mtsr(mfsr(i << 28) | 0x10000000, i << 28);
0232     }
0233 }
0234
0235 void mmu_mark_rodata_ro(void)
0236 {
0237     int nb = mmu_has_feature(MMU_FTR_USE_HIGH_BATS) ? 8 : 4;
0238     int i;
0239
0240     for (i = 0; i < nb; i++) {
0241         struct ppc_bat *bat = BATS[i];
0242
0243         if (bat_addrs[i].start < (unsigned long)__init_begin)
0244             bat[1].batl = (bat[1].batl & ~BPP_RW) | BPP_RX;
0245     }
0246
0247     update_bats();
0248 }
0249
0250 /*
0251  * Set up one of the D BAT (block address translation) register pairs.
0252  * The parameters are not checked; in particular size must be a power
0253  * of 2 between 128k and 256M.
0254  */
0255 void __init setbat(int index, unsigned long virt, phys_addr_t phys,
0256            unsigned int size, pgprot_t prot)
0257 {
0258     unsigned int bl;
0259     int wimgxpp;
0260     struct ppc_bat *bat;
0261     unsigned long flags = pgprot_val(prot);
0262
0263     if (index == -1)
0264         index = find_free_bat();
0265     if (index == -1) {
0266         pr_err("%s: no BAT available for mapping 0x%llx\n", __func__,
0267                (unsigned long long)phys);
0268         return;
0269     }
0270     bat = BATS[index];
0271
0272     if ((flags & _PAGE_NO_CACHE) ||
0273         (cpu_has_feature(CPU_FTR_NEED_COHERENT) == 0))
0274         flags &= ~_PAGE_COHERENT;
0275
0276     bl = (size >> 17) - 1;
0277     /* Do DBAT first */
0278     wimgxpp = flags & (_PAGE_WRITETHRU | _PAGE_NO_CACHE
0279                | _PAGE_COHERENT | _PAGE_GUARDED);
0280     wimgxpp |= (flags & _PAGE_RW)? BPP_RW: BPP_RX;
0281     bat[1].batu = virt | (bl << 2) | 2; /* Vs=1, Vp=0 */
0282     bat[1].batl = BAT_PHYS_ADDR(phys) | wimgxpp;
0283     if (flags & _PAGE_USER)
0284         bat[1].batu |= 1;   /* Vp = 1 */
0285     if (flags & _PAGE_GUARDED) {
0286         /* G bit must be zero in IBATs */
0287         flags &= ~_PAGE_EXEC;
0288     }
0289
0290     bat_addrs[index].start = virt;
0291     bat_addrs[index].limit = virt + ((bl + 1) << 17) - 1;
0292     bat_addrs[index].phys = phys;
0293 }
0294
0295 /*
0296  * Preload a translation in the hash table
0297  */
0298 static void hash_preload(struct mm_struct *mm, unsigned long ea)
0299 {
0300     pmd_t *pmd;
0301
0302     if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
0303         return;
0304     pmd = pmd_off(mm, ea);
0305     if (!pmd_none(*pmd))
0306         add_hash_page(mm->context.id, ea, pmd_val(*pmd));
0307 }
0308
0309 /*
0310  * This is called at the end of handling a user page fault, when the
0311  * fault has been handled by updating a PTE in the linux page tables.
0312  * We use it to preload an HPTE into the hash table corresponding to
0313  * the updated linux PTE.
0314  *
0315  * This must always be called with the pte lock held.
0316  */
0317 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
0318               pte_t *ptep)
0319 {
0320     if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
0321         return;
0322     /*
0323      * We don't need to worry about _PAGE_PRESENT here because we are
0324      * called with either mm->page_table_lock held or ptl lock held
0325      */
0326
0327     /* We only want HPTEs for linux PTEs that have _PAGE_ACCESSED set */
0328     if (!pte_young(*ptep) || address >= TASK_SIZE)
0329         return;
0330
0331     /* We have to test for regs NULL since init will get here first thing at boot */
0332     if (!current->thread.regs)
0333         return;
0334
0335     /* We also avoid filling the hash if not coming from a fault */
0336     if (TRAP(current->thread.regs) != 0x300 && TRAP(current->thread.regs) != 0x400)
0337         return;
0338
0339     hash_preload(vma->vm_mm, address);
0340 }
0341
0342 /*
0343  * Initialize the hash table and patch the instructions in hashtable.S.
0344  */
0345 void __init MMU_init_hw(void)
0346 {
0347     unsigned int n_hpteg, lg_n_hpteg;
0348
0349     if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
0350         return;
0351
0352     if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
0353
0354 #define LG_HPTEG_SIZE   6       /* 64 bytes per HPTEG */
0355 #define SDR1_LOW_BITS   ((n_hpteg - 1) >> 10)
0356 #define MIN_N_HPTEG 1024        /* min 64kB hash table */
0357
0358     /*
0359      * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
0360      * This is less than the recommended amount, but then
0361      * Linux ain't AIX.
0362      */
0363     n_hpteg = total_memory / (PAGE_SIZE * 8);
0364     if (n_hpteg < MIN_N_HPTEG)
0365         n_hpteg = MIN_N_HPTEG;
0366     lg_n_hpteg = __ilog2(n_hpteg);
0367     if (n_hpteg & (n_hpteg - 1)) {
0368         ++lg_n_hpteg;       /* round up if not power of 2 */
0369         n_hpteg = 1 << lg_n_hpteg;
0370     }
0371     Hash_size = n_hpteg << LG_HPTEG_SIZE;
0372
0373     /*
0374      * Find some memory for the hash table.
0375      */
0376     if ( ppc_md.progress ) ppc_md.progress("hash:find piece", 0x322);
0377     Hash = memblock_alloc(Hash_size, Hash_size);
0378     if (!Hash)
0379         panic("%s: Failed to allocate %lu bytes align=0x%lx\n",
0380               __func__, Hash_size, Hash_size);
0381     _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
0382
0383     pr_info("Total memory = %lldMB; using %ldkB for hash table\n",
0384         (unsigned long long)(total_memory >> 20), Hash_size >> 10);
0385
0386
0387     Hash_mask = n_hpteg - 1;
0388     hash_mb2 = hash_mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
0389     if (lg_n_hpteg > 16)
0390         hash_mb2 = 16 - LG_HPTEG_SIZE;
0391 }
0392
0393 void __init MMU_init_hw_patch(void)
0394 {
0395     unsigned int hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
0396     unsigned int hash = (unsigned int)Hash - PAGE_OFFSET;
0397
0398     if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
0399         return;
0400
0401     if (ppc_md.progress)
0402         ppc_md.progress("hash:patch", 0x345);
0403     if (ppc_md.progress)
0404         ppc_md.progress("hash:done", 0x205);
0405
0406     /* WARNING: Make sure nothing can trigger a KASAN check past this point */
0407
0408     /*
0409      * Patch up the instructions in hashtable.S:create_hpte
0410      */
0411     modify_instruction_site(&patch__hash_page_A0, 0xffff, hash >> 16);
0412     modify_instruction_site(&patch__hash_page_A1, 0x7c0, hash_mb << 6);
0413     modify_instruction_site(&patch__hash_page_A2, 0x7c0, hash_mb2 << 6);
0414     modify_instruction_site(&patch__hash_page_B, 0xffff, hmask);
0415     modify_instruction_site(&patch__hash_page_C, 0xffff, hmask);
0416
0417     /*
0418      * Patch up the instructions in hashtable.S:flush_hash_page
0419      */
0420     modify_instruction_site(&patch__flush_hash_A0, 0xffff, hash >> 16);
0421     modify_instruction_site(&patch__flush_hash_A1, 0x7c0, hash_mb << 6);
0422     modify_instruction_site(&patch__flush_hash_A2, 0x7c0, hash_mb2 << 6);
0423     modify_instruction_site(&patch__flush_hash_B, 0xffff, hmask);
0424 }
0425
0426 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
0427                 phys_addr_t first_memblock_size)
0428 {
0429     /* We don't currently support the first MEMBLOCK not mapping 0
0430      * physical on those processors
0431      */
0432     BUG_ON(first_memblock_base != 0);
0433
0434     memblock_set_current_limit(min_t(u64, first_memblock_size, SZ_256M));
0435 }
0436
0437 void __init print_system_hash_info(void)
0438 {
0439     pr_info("Hash_size         = 0x%lx\n", Hash_size);
0440     if (Hash_mask)
0441         pr_info("Hash_mask         = 0x%lx\n", Hash_mask);
0442 }
0443
0444 void __init early_init_mmu(void)
0445 {
0446 }