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0010 #include <asm/ppc_asm.h>
0011 #include <asm/export.h>
0012 #include <asm/cache.h>
0013
0014 .text
0015
0016 CACHELINE_BYTES = L1_CACHE_BYTES
0017 LG_CACHELINE_BYTES = L1_CACHE_SHIFT
0018 CACHELINE_MASK = (L1_CACHE_BYTES-1)
0019
0020 _GLOBAL(__arch_clear_user)
0021
0022
0023
0024
0025
0026 cmplwi cr0, r4, 4
0027 mr r10, r3
0028 li r3, 0
0029 blt 7f
0030
0031 11: stw r3, 0(r10)
0032 beqlr
0033 andi. r0, r10, 3
0034 add r11, r0, r4
0035 subf r6, r0, r10
0036
0037 clrlwi r7, r6, 32 - LG_CACHELINE_BYTES
0038 add r8, r7, r11
0039 srwi r9, r8, LG_CACHELINE_BYTES
0040 addic. r9, r9, -1
0041 ble 2f
0042 xori r0, r7, CACHELINE_MASK & ~3
0043 srwi. r0, r0, 2
0044 beq 3f
0045 mtctr r0
0046 4: stwu r3, 4(r6)
0047 bdnz 4b
0048 3: mtctr r9
0049 li r7, 4
0050 10: dcbz r7, r6
0051 addi r6, r6, CACHELINE_BYTES
0052 bdnz 10b
0053 clrlwi r11, r8, 32 - LG_CACHELINE_BYTES
0054 addi r11, r11, 4
0055
0056 2: srwi r0 ,r11 ,2
0057 mtctr r0
0058 bdz 6f
0059 1: stwu r3, 4(r6)
0060 bdnz 1b
0061 6: andi. r11, r11, 3
0062 beqlr
0063 mtctr r11
0064 addi r6, r6, 3
0065 8: stbu r3, 1(r6)
0066 bdnz 8b
0067 blr
0068
0069 7: cmpwi cr0, r4, 0
0070 beqlr
0071 mtctr r4
0072 addi r6, r10, -1
0073 9: stbu r3, 1(r6)
0074 bdnz 9b
0075 blr
0076
0077 90: mr r3, r4
0078 blr
0079 91: add r3, r10, r4
0080 subf r3, r6, r3
0081 blr
0082
0083 EX_TABLE(11b, 90b)
0084 EX_TABLE(4b, 91b)
0085 EX_TABLE(10b, 91b)
0086 EX_TABLE(1b, 91b)
0087 EX_TABLE(8b, 91b)
0088 EX_TABLE(9b, 91b)
0089
0090 EXPORT_SYMBOL(__arch_clear_user)