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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *
0004  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
0005  *
0006  * Author: Varun Sethi <varun.sethi@freescale.com>
0007  * Author: Scott Wood <scotwood@freescale.com>
0008  * Author: Mihai Caraman <mihai.caraman@freescale.com>
0009  *
0010  * This file is derived from arch/powerpc/kvm/booke_interrupts.S
0011  */
0012 
0013 #include <asm/ppc_asm.h>
0014 #include <asm/kvm_asm.h>
0015 #include <asm/reg.h>
0016 #include <asm/page.h>
0017 #include <asm/asm-compat.h>
0018 #include <asm/asm-offsets.h>
0019 #include <asm/bitsperlong.h>
0020 
0021 #ifdef CONFIG_64BIT
0022 #include <asm/exception-64e.h>
0023 #include <asm/hw_irq.h>
0024 #include <asm/irqflags.h>
0025 #else
0026 #include "../kernel/head_booke.h" /* for THREAD_NORMSAVE() */
0027 #endif
0028 
0029 #define LONGBYTES       (BITS_PER_LONG / 8)
0030 
0031 #define VCPU_GUEST_SPRG(n)  (VCPU_GUEST_SPRGS + (n * LONGBYTES))
0032 
0033 /* The host stack layout: */
0034 #define HOST_R1         0 /* Implied by stwu. */
0035 #define HOST_CALLEE_LR  PPC_LR_STKOFF
0036 #define HOST_RUN        (HOST_CALLEE_LR + LONGBYTES)
0037 /*
0038  * r2 is special: it holds 'current', and it made nonvolatile in the
0039  * kernel with the -ffixed-r2 gcc option.
0040  */
0041 #define HOST_R2         (HOST_RUN + LONGBYTES)
0042 #define HOST_CR         (HOST_R2 + LONGBYTES)
0043 #define HOST_NV_GPRS    (HOST_CR + LONGBYTES)
0044 #define __HOST_NV_GPR(n)  (HOST_NV_GPRS + ((n - 14) * LONGBYTES))
0045 #define HOST_NV_GPR(n)  __HOST_NV_GPR(__REG_##n)
0046 #define HOST_MIN_STACK_SIZE (HOST_NV_GPR(R31) + LONGBYTES)
0047 #define HOST_STACK_SIZE ((HOST_MIN_STACK_SIZE + 15) & ~15) /* Align. */
0048 /* LR in caller stack frame. */
0049 #define HOST_STACK_LR   (HOST_STACK_SIZE + PPC_LR_STKOFF)
0050 
0051 #define NEED_EMU        0x00000001 /* emulation -- save nv regs */
0052 #define NEED_DEAR       0x00000002 /* save faulting DEAR */
0053 #define NEED_ESR        0x00000004 /* save faulting ESR */
0054 
0055 /*
0056  * On entry:
0057  * r4 = vcpu, r5 = srr0, r6 = srr1
0058  * saved in vcpu: cr, ctr, r3-r13
0059  */
0060 .macro kvm_handler_common intno, srr0, flags
0061     /* Restore host stack pointer */
0062     PPC_STL r1, VCPU_GPR(R1)(r4)
0063     PPC_STL r2, VCPU_GPR(R2)(r4)
0064     PPC_LL  r1, VCPU_HOST_STACK(r4)
0065     PPC_LL  r2, HOST_R2(r1)
0066 
0067 START_BTB_FLUSH_SECTION
0068     BTB_FLUSH(r10)
0069 END_BTB_FLUSH_SECTION
0070 
0071     mfspr   r10, SPRN_PID
0072     lwz r8, VCPU_HOST_PID(r4)
0073     PPC_LL  r11, VCPU_SHARED(r4)
0074     PPC_STL r14, VCPU_GPR(R14)(r4) /* We need a non-volatile GPR. */
0075     li  r14, \intno
0076 
0077     stw r10, VCPU_GUEST_PID(r4)
0078     mtspr   SPRN_PID, r8
0079 
0080 #ifdef CONFIG_KVM_EXIT_TIMING
0081     /* save exit time */
0082 1:  mfspr   r7, SPRN_TBRU
0083     mfspr   r8, SPRN_TBRL
0084     mfspr   r9, SPRN_TBRU
0085     cmpw    r9, r7
0086     stw r8, VCPU_TIMING_EXIT_TBL(r4)
0087     bne-    1b
0088     stw r9, VCPU_TIMING_EXIT_TBU(r4)
0089 #endif
0090 
0091     oris    r8, r6, MSR_CE@h
0092     PPC_STD(r6, VCPU_SHARED_MSR, r11)
0093     ori r8, r8, MSR_ME | MSR_RI
0094     PPC_STL r5, VCPU_PC(r4)
0095 
0096     /*
0097      * Make sure CE/ME/RI are set (if appropriate for exception type)
0098      * whether or not the guest had it set.  Since mfmsr/mtmsr are
0099      * somewhat expensive, skip in the common case where the guest
0100      * had all these bits set (and thus they're still set if
0101      * appropriate for the exception type).
0102      */
0103     cmpw    r6, r8
0104     beq 1f
0105     mfmsr   r7
0106     .if \srr0 != SPRN_MCSRR0 && \srr0 != SPRN_CSRR0
0107     oris    r7, r7, MSR_CE@h
0108     .endif
0109     .if \srr0 != SPRN_MCSRR0
0110     ori r7, r7, MSR_ME | MSR_RI
0111     .endif
0112     mtmsr   r7
0113 1:
0114 
0115     .if \flags & NEED_EMU
0116     PPC_STL r15, VCPU_GPR(R15)(r4)
0117     PPC_STL r16, VCPU_GPR(R16)(r4)
0118     PPC_STL r17, VCPU_GPR(R17)(r4)
0119     PPC_STL r18, VCPU_GPR(R18)(r4)
0120     PPC_STL r19, VCPU_GPR(R19)(r4)
0121     PPC_STL r20, VCPU_GPR(R20)(r4)
0122     PPC_STL r21, VCPU_GPR(R21)(r4)
0123     PPC_STL r22, VCPU_GPR(R22)(r4)
0124     PPC_STL r23, VCPU_GPR(R23)(r4)
0125     PPC_STL r24, VCPU_GPR(R24)(r4)
0126     PPC_STL r25, VCPU_GPR(R25)(r4)
0127     PPC_STL r26, VCPU_GPR(R26)(r4)
0128     PPC_STL r27, VCPU_GPR(R27)(r4)
0129     PPC_STL r28, VCPU_GPR(R28)(r4)
0130     PPC_STL r29, VCPU_GPR(R29)(r4)
0131     PPC_STL r30, VCPU_GPR(R30)(r4)
0132     PPC_STL r31, VCPU_GPR(R31)(r4)
0133 
0134     /*
0135      * We don't use external PID support. lwepx faults would need to be
0136      * handled by KVM and this implies aditional code in DO_KVM (for
0137      * DTB_MISS, DSI and LRAT) to check ESR[EPID] and EPLC[EGS] which
0138      * is too intrusive for the host. Get last instuction in
0139      * kvmppc_get_last_inst().
0140      */
0141     li  r9, KVM_INST_FETCH_FAILED
0142     stw r9, VCPU_LAST_INST(r4)
0143     .endif
0144 
0145     .if \flags & NEED_ESR
0146     mfspr   r8, SPRN_ESR
0147     PPC_STL r8, VCPU_FAULT_ESR(r4)
0148     .endif
0149 
0150     .if \flags & NEED_DEAR
0151     mfspr   r9, SPRN_DEAR
0152     PPC_STL r9, VCPU_FAULT_DEAR(r4)
0153     .endif
0154 
0155     b   kvmppc_resume_host
0156 .endm
0157 
0158 #ifdef CONFIG_64BIT
0159 /* Exception types */
0160 #define EX_GEN          1
0161 #define EX_GDBELL       2
0162 #define EX_DBG          3
0163 #define EX_MC           4
0164 #define EX_CRIT         5
0165 #define EX_TLB          6
0166 
0167 /*
0168  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
0169  */
0170 .macro kvm_handler intno type scratch, paca_ex, ex_r10, ex_r11, srr0, srr1, flags
0171  _GLOBAL(kvmppc_handler_\intno\()_\srr1)
0172     mr  r11, r4
0173     /*
0174      * Get vcpu from Paca: paca->__current.thread->kvm_vcpu
0175      */
0176     PPC_LL  r4, PACACURRENT(r13)
0177     PPC_LL  r4, (THREAD + THREAD_KVM_VCPU)(r4)
0178     PPC_STL r10, VCPU_CR(r4)
0179     PPC_STL r11, VCPU_GPR(R4)(r4)
0180     PPC_STL r5, VCPU_GPR(R5)(r4)
0181     PPC_STL r6, VCPU_GPR(R6)(r4)
0182     PPC_STL r8, VCPU_GPR(R8)(r4)
0183     PPC_STL r9, VCPU_GPR(R9)(r4)
0184     .if \type == EX_TLB
0185     PPC_LL  r5, EX_TLB_R13(r12)
0186     PPC_LL  r6, EX_TLB_R10(r12)
0187     PPC_LL  r8, EX_TLB_R11(r12)
0188     mfspr   r12, \scratch
0189     .else
0190     mfspr   r5, \scratch
0191     PPC_LL  r6, (\paca_ex + \ex_r10)(r13)
0192     PPC_LL  r8, (\paca_ex + \ex_r11)(r13)
0193     .endif
0194     PPC_STL r5, VCPU_GPR(R13)(r4)
0195     PPC_STL r3, VCPU_GPR(R3)(r4)
0196     PPC_STL r7, VCPU_GPR(R7)(r4)
0197     PPC_STL r12, VCPU_GPR(R12)(r4)
0198     PPC_STL r6, VCPU_GPR(R10)(r4)
0199     PPC_STL r8, VCPU_GPR(R11)(r4)
0200     mfctr   r5
0201     PPC_STL r5, VCPU_CTR(r4)
0202     mfspr   r5, \srr0
0203     mfspr   r6, \srr1
0204     kvm_handler_common \intno, \srr0, \flags
0205 .endm
0206 
0207 #define EX_PARAMS(type) \
0208     EX_##type, \
0209     SPRN_SPRG_##type##_SCRATCH, \
0210     PACA_EX##type, \
0211     EX_R10, \
0212     EX_R11
0213 
0214 #define EX_PARAMS_TLB \
0215     EX_TLB, \
0216     SPRN_SPRG_GEN_SCRATCH, \
0217     PACA_EXTLB, \
0218     EX_TLB_R10, \
0219     EX_TLB_R11
0220 
0221 kvm_handler BOOKE_INTERRUPT_CRITICAL, EX_PARAMS(CRIT), \
0222     SPRN_CSRR0, SPRN_CSRR1, 0
0223 kvm_handler BOOKE_INTERRUPT_MACHINE_CHECK, EX_PARAMS(MC), \
0224     SPRN_MCSRR0, SPRN_MCSRR1, 0
0225 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, EX_PARAMS(GEN), \
0226     SPRN_SRR0, SPRN_SRR1,(NEED_EMU | NEED_DEAR | NEED_ESR)
0227 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, EX_PARAMS(GEN), \
0228     SPRN_SRR0, SPRN_SRR1, NEED_ESR
0229 kvm_handler BOOKE_INTERRUPT_EXTERNAL, EX_PARAMS(GEN), \
0230     SPRN_SRR0, SPRN_SRR1, 0
0231 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, EX_PARAMS(GEN), \
0232     SPRN_SRR0, SPRN_SRR1,(NEED_DEAR | NEED_ESR)
0233 kvm_handler BOOKE_INTERRUPT_PROGRAM, EX_PARAMS(GEN), \
0234     SPRN_SRR0, SPRN_SRR1, (NEED_ESR | NEED_EMU)
0235 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, EX_PARAMS(GEN), \
0236     SPRN_SRR0, SPRN_SRR1, 0
0237 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, EX_PARAMS(GEN), \
0238     SPRN_SRR0, SPRN_SRR1, 0
0239 kvm_handler BOOKE_INTERRUPT_DECREMENTER, EX_PARAMS(GEN), \
0240     SPRN_SRR0, SPRN_SRR1, 0
0241 kvm_handler BOOKE_INTERRUPT_FIT, EX_PARAMS(GEN), \
0242     SPRN_SRR0, SPRN_SRR1, 0
0243 kvm_handler BOOKE_INTERRUPT_WATCHDOG, EX_PARAMS(CRIT),\
0244     SPRN_CSRR0, SPRN_CSRR1, 0
0245 /*
0246  * Only bolted TLB miss exception handlers are supported for now
0247  */
0248 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, EX_PARAMS_TLB, \
0249     SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
0250 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, EX_PARAMS_TLB, \
0251     SPRN_SRR0, SPRN_SRR1, 0
0252 kvm_handler BOOKE_INTERRUPT_ALTIVEC_UNAVAIL, EX_PARAMS(GEN), \
0253     SPRN_SRR0, SPRN_SRR1, 0
0254 kvm_handler BOOKE_INTERRUPT_ALTIVEC_ASSIST, EX_PARAMS(GEN), \
0255     SPRN_SRR0, SPRN_SRR1, 0
0256 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, EX_PARAMS(GEN), \
0257     SPRN_SRR0, SPRN_SRR1, 0
0258 kvm_handler BOOKE_INTERRUPT_DOORBELL, EX_PARAMS(GEN), \
0259     SPRN_SRR0, SPRN_SRR1, 0
0260 kvm_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, EX_PARAMS(CRIT), \
0261     SPRN_CSRR0, SPRN_CSRR1, 0
0262 kvm_handler BOOKE_INTERRUPT_HV_PRIV, EX_PARAMS(GEN), \
0263     SPRN_SRR0, SPRN_SRR1, NEED_EMU
0264 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, EX_PARAMS(GEN), \
0265     SPRN_SRR0, SPRN_SRR1, 0
0266 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, EX_PARAMS(GDBELL), \
0267     SPRN_GSRR0, SPRN_GSRR1, 0
0268 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, EX_PARAMS(CRIT), \
0269     SPRN_CSRR0, SPRN_CSRR1, 0
0270 kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(DBG), \
0271     SPRN_DSRR0, SPRN_DSRR1, 0
0272 kvm_handler BOOKE_INTERRUPT_DEBUG, EX_PARAMS(CRIT), \
0273     SPRN_CSRR0, SPRN_CSRR1, 0
0274 kvm_handler BOOKE_INTERRUPT_LRAT_ERROR, EX_PARAMS(GEN), \
0275     SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
0276 #else
0277 /*
0278  * For input register values, see arch/powerpc/include/asm/kvm_booke_hv_asm.h
0279  */
0280 .macro kvm_handler intno srr0, srr1, flags
0281 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
0282     PPC_LL  r11, THREAD_KVM_VCPU(r10)
0283     PPC_STL r3, VCPU_GPR(R3)(r11)
0284     mfspr   r3, SPRN_SPRG_RSCRATCH0
0285     PPC_STL r4, VCPU_GPR(R4)(r11)
0286     PPC_LL  r4, THREAD_NORMSAVE(0)(r10)
0287     PPC_STL r5, VCPU_GPR(R5)(r11)
0288     PPC_STL r13, VCPU_CR(r11)
0289     mfspr   r5, \srr0
0290     PPC_STL r3, VCPU_GPR(R10)(r11)
0291     PPC_LL  r3, THREAD_NORMSAVE(2)(r10)
0292     PPC_STL r6, VCPU_GPR(R6)(r11)
0293     PPC_STL r4, VCPU_GPR(R11)(r11)
0294     mfspr   r6, \srr1
0295     PPC_STL r7, VCPU_GPR(R7)(r11)
0296     PPC_STL r8, VCPU_GPR(R8)(r11)
0297     PPC_STL r9, VCPU_GPR(R9)(r11)
0298     PPC_STL r3, VCPU_GPR(R13)(r11)
0299     mfctr   r7
0300     PPC_STL r12, VCPU_GPR(R12)(r11)
0301     PPC_STL r7, VCPU_CTR(r11)
0302     mr  r4, r11
0303     kvm_handler_common \intno, \srr0, \flags
0304 .endm
0305 
0306 .macro kvm_lvl_handler intno scratch srr0, srr1, flags
0307 _GLOBAL(kvmppc_handler_\intno\()_\srr1)
0308     mfspr   r10, SPRN_SPRG_THREAD
0309     PPC_LL  r11, THREAD_KVM_VCPU(r10)
0310     PPC_STL r3, VCPU_GPR(R3)(r11)
0311     mfspr   r3, \scratch
0312     PPC_STL r4, VCPU_GPR(R4)(r11)
0313     PPC_LL  r4, GPR9(r8)
0314     PPC_STL r5, VCPU_GPR(R5)(r11)
0315     PPC_STL r9, VCPU_CR(r11)
0316     mfspr   r5, \srr0
0317     PPC_STL r3, VCPU_GPR(R8)(r11)
0318     PPC_LL  r3, GPR10(r8)
0319     PPC_STL r6, VCPU_GPR(R6)(r11)
0320     PPC_STL r4, VCPU_GPR(R9)(r11)
0321     mfspr   r6, \srr1
0322     PPC_LL  r4, GPR11(r8)
0323     PPC_STL r7, VCPU_GPR(R7)(r11)
0324     PPC_STL r3, VCPU_GPR(R10)(r11)
0325     mfctr   r7
0326     PPC_STL r12, VCPU_GPR(R12)(r11)
0327     PPC_STL r13, VCPU_GPR(R13)(r11)
0328     PPC_STL r4, VCPU_GPR(R11)(r11)
0329     PPC_STL r7, VCPU_CTR(r11)
0330     mr  r4, r11
0331     kvm_handler_common \intno, \srr0, \flags
0332 .endm
0333 
0334 kvm_lvl_handler BOOKE_INTERRUPT_CRITICAL, \
0335     SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
0336 kvm_lvl_handler BOOKE_INTERRUPT_MACHINE_CHECK, \
0337     SPRN_SPRG_RSCRATCH_MC, SPRN_MCSRR0, SPRN_MCSRR1, 0
0338 kvm_handler BOOKE_INTERRUPT_DATA_STORAGE, \
0339     SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
0340 kvm_handler BOOKE_INTERRUPT_INST_STORAGE, SPRN_SRR0, SPRN_SRR1, NEED_ESR
0341 kvm_handler BOOKE_INTERRUPT_EXTERNAL, SPRN_SRR0, SPRN_SRR1, 0
0342 kvm_handler BOOKE_INTERRUPT_ALIGNMENT, \
0343     SPRN_SRR0, SPRN_SRR1, (NEED_DEAR | NEED_ESR)
0344 kvm_handler BOOKE_INTERRUPT_PROGRAM, SPRN_SRR0, SPRN_SRR1, (NEED_ESR | NEED_EMU)
0345 kvm_handler BOOKE_INTERRUPT_FP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
0346 kvm_handler BOOKE_INTERRUPT_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
0347 kvm_handler BOOKE_INTERRUPT_AP_UNAVAIL, SPRN_SRR0, SPRN_SRR1, 0
0348 kvm_handler BOOKE_INTERRUPT_DECREMENTER, SPRN_SRR0, SPRN_SRR1, 0
0349 kvm_handler BOOKE_INTERRUPT_FIT, SPRN_SRR0, SPRN_SRR1, 0
0350 kvm_lvl_handler BOOKE_INTERRUPT_WATCHDOG, \
0351     SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
0352 kvm_handler BOOKE_INTERRUPT_DTLB_MISS, \
0353     SPRN_SRR0, SPRN_SRR1, (NEED_EMU | NEED_DEAR | NEED_ESR)
0354 kvm_handler BOOKE_INTERRUPT_ITLB_MISS, SPRN_SRR0, SPRN_SRR1, 0
0355 kvm_handler BOOKE_INTERRUPT_PERFORMANCE_MONITOR, SPRN_SRR0, SPRN_SRR1, 0
0356 kvm_handler BOOKE_INTERRUPT_DOORBELL, SPRN_SRR0, SPRN_SRR1, 0
0357 kvm_lvl_handler BOOKE_INTERRUPT_DOORBELL_CRITICAL, \
0358     SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
0359 kvm_handler BOOKE_INTERRUPT_HV_PRIV, SPRN_SRR0, SPRN_SRR1, NEED_EMU
0360 kvm_handler BOOKE_INTERRUPT_HV_SYSCALL, SPRN_SRR0, SPRN_SRR1, 0
0361 kvm_handler BOOKE_INTERRUPT_GUEST_DBELL, SPRN_GSRR0, SPRN_GSRR1, 0
0362 kvm_lvl_handler BOOKE_INTERRUPT_GUEST_DBELL_CRIT, \
0363     SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
0364 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
0365     SPRN_SPRG_RSCRATCH_CRIT, SPRN_CSRR0, SPRN_CSRR1, 0
0366 kvm_lvl_handler BOOKE_INTERRUPT_DEBUG, \
0367     SPRN_SPRG_RSCRATCH_DBG, SPRN_DSRR0, SPRN_DSRR1, 0
0368 #endif
0369 
0370 /* Registers:
0371  *  SPRG_SCRATCH0: guest r10
0372  *  r4: vcpu pointer
0373  *  r11: vcpu->arch.shared
0374  *  r14: KVM exit number
0375  */
0376 _GLOBAL(kvmppc_resume_host)
0377     /* Save remaining volatile guest register state to vcpu. */
0378     mfspr   r3, SPRN_VRSAVE
0379     PPC_STL r0, VCPU_GPR(R0)(r4)
0380     mflr    r5
0381     mfspr   r6, SPRN_SPRG4
0382     PPC_STL r5, VCPU_LR(r4)
0383     mfspr   r7, SPRN_SPRG5
0384     stw r3, VCPU_VRSAVE(r4)
0385 #ifdef CONFIG_64BIT
0386     PPC_LL  r3, PACA_SPRG_VDSO(r13)
0387 #endif
0388     mfspr   r5, SPRN_SPRG9
0389     PPC_STD(r6, VCPU_SHARED_SPRG4, r11)
0390     mfspr   r8, SPRN_SPRG6
0391     PPC_STD(r7, VCPU_SHARED_SPRG5, r11)
0392     mfspr   r9, SPRN_SPRG7
0393 #ifdef CONFIG_64BIT
0394     mtspr   SPRN_SPRG_VDSO_WRITE, r3
0395 #endif
0396     PPC_STD(r5, VCPU_SPRG9, r4)
0397     PPC_STD(r8, VCPU_SHARED_SPRG6, r11)
0398     mfxer   r3
0399     PPC_STD(r9, VCPU_SHARED_SPRG7, r11)
0400 
0401     /* save guest MAS registers and restore host mas4 & mas6 */
0402     mfspr   r5, SPRN_MAS0
0403     PPC_STL r3, VCPU_XER(r4)
0404     mfspr   r6, SPRN_MAS1
0405     stw r5, VCPU_SHARED_MAS0(r11)
0406     mfspr   r7, SPRN_MAS2
0407     stw r6, VCPU_SHARED_MAS1(r11)
0408     PPC_STD(r7, VCPU_SHARED_MAS2, r11)
0409     mfspr   r5, SPRN_MAS3
0410     mfspr   r6, SPRN_MAS4
0411     stw r5, VCPU_SHARED_MAS7_3+4(r11)
0412     mfspr   r7, SPRN_MAS6
0413     stw r6, VCPU_SHARED_MAS4(r11)
0414     mfspr   r5, SPRN_MAS7
0415     lwz r6, VCPU_HOST_MAS4(r4)
0416     stw r7, VCPU_SHARED_MAS6(r11)
0417     lwz r8, VCPU_HOST_MAS6(r4)
0418     mtspr   SPRN_MAS4, r6
0419     stw r5, VCPU_SHARED_MAS7_3+0(r11)
0420     mtspr   SPRN_MAS6, r8
0421     /* Enable MAS register updates via exception */
0422     mfspr   r3, SPRN_EPCR
0423     rlwinm  r3, r3, 0, ~SPRN_EPCR_DMIUH
0424     mtspr   SPRN_EPCR, r3
0425     isync
0426 
0427 #ifdef CONFIG_64BIT
0428     /*
0429      * We enter with interrupts disabled in hardware, but
0430      * we need to call RECONCILE_IRQ_STATE to ensure
0431      * that the software state is kept in sync.
0432      */
0433     RECONCILE_IRQ_STATE(r3,r5)
0434 #endif
0435 
0436     /* Switch to kernel stack and jump to handler. */
0437     mr  r3, r4
0438     mr  r5, r14 /* intno */
0439     mr  r14, r4 /* Save vcpu pointer. */
0440     mr  r4, r5
0441     bl  kvmppc_handle_exit
0442 
0443     /* Restore vcpu pointer and the nonvolatiles we used. */
0444     mr  r4, r14
0445     PPC_LL  r14, VCPU_GPR(R14)(r4)
0446 
0447     andi.   r5, r3, RESUME_FLAG_NV
0448     beq skip_nv_load
0449     PPC_LL  r15, VCPU_GPR(R15)(r4)
0450     PPC_LL  r16, VCPU_GPR(R16)(r4)
0451     PPC_LL  r17, VCPU_GPR(R17)(r4)
0452     PPC_LL  r18, VCPU_GPR(R18)(r4)
0453     PPC_LL  r19, VCPU_GPR(R19)(r4)
0454     PPC_LL  r20, VCPU_GPR(R20)(r4)
0455     PPC_LL  r21, VCPU_GPR(R21)(r4)
0456     PPC_LL  r22, VCPU_GPR(R22)(r4)
0457     PPC_LL  r23, VCPU_GPR(R23)(r4)
0458     PPC_LL  r24, VCPU_GPR(R24)(r4)
0459     PPC_LL  r25, VCPU_GPR(R25)(r4)
0460     PPC_LL  r26, VCPU_GPR(R26)(r4)
0461     PPC_LL  r27, VCPU_GPR(R27)(r4)
0462     PPC_LL  r28, VCPU_GPR(R28)(r4)
0463     PPC_LL  r29, VCPU_GPR(R29)(r4)
0464     PPC_LL  r30, VCPU_GPR(R30)(r4)
0465     PPC_LL  r31, VCPU_GPR(R31)(r4)
0466 skip_nv_load:
0467     /* Should we return to the guest? */
0468     andi.   r5, r3, RESUME_FLAG_HOST
0469     beq lightweight_exit
0470 
0471     srawi   r3, r3, 2 /* Shift -ERR back down. */
0472 
0473 heavyweight_exit:
0474     /* Not returning to guest. */
0475     PPC_LL  r5, HOST_STACK_LR(r1)
0476     lwz r6, HOST_CR(r1)
0477 
0478     /*
0479      * We already saved guest volatile register state; now save the
0480      * non-volatiles.
0481      */
0482 
0483     PPC_STL r15, VCPU_GPR(R15)(r4)
0484     PPC_STL r16, VCPU_GPR(R16)(r4)
0485     PPC_STL r17, VCPU_GPR(R17)(r4)
0486     PPC_STL r18, VCPU_GPR(R18)(r4)
0487     PPC_STL r19, VCPU_GPR(R19)(r4)
0488     PPC_STL r20, VCPU_GPR(R20)(r4)
0489     PPC_STL r21, VCPU_GPR(R21)(r4)
0490     PPC_STL r22, VCPU_GPR(R22)(r4)
0491     PPC_STL r23, VCPU_GPR(R23)(r4)
0492     PPC_STL r24, VCPU_GPR(R24)(r4)
0493     PPC_STL r25, VCPU_GPR(R25)(r4)
0494     PPC_STL r26, VCPU_GPR(R26)(r4)
0495     PPC_STL r27, VCPU_GPR(R27)(r4)
0496     PPC_STL r28, VCPU_GPR(R28)(r4)
0497     PPC_STL r29, VCPU_GPR(R29)(r4)
0498     PPC_STL r30, VCPU_GPR(R30)(r4)
0499     PPC_STL r31, VCPU_GPR(R31)(r4)
0500 
0501     /* Load host non-volatile register state from host stack. */
0502     PPC_LL  r14, HOST_NV_GPR(R14)(r1)
0503     PPC_LL  r15, HOST_NV_GPR(R15)(r1)
0504     PPC_LL  r16, HOST_NV_GPR(R16)(r1)
0505     PPC_LL  r17, HOST_NV_GPR(R17)(r1)
0506     PPC_LL  r18, HOST_NV_GPR(R18)(r1)
0507     PPC_LL  r19, HOST_NV_GPR(R19)(r1)
0508     PPC_LL  r20, HOST_NV_GPR(R20)(r1)
0509     PPC_LL  r21, HOST_NV_GPR(R21)(r1)
0510     PPC_LL  r22, HOST_NV_GPR(R22)(r1)
0511     PPC_LL  r23, HOST_NV_GPR(R23)(r1)
0512     PPC_LL  r24, HOST_NV_GPR(R24)(r1)
0513     PPC_LL  r25, HOST_NV_GPR(R25)(r1)
0514     PPC_LL  r26, HOST_NV_GPR(R26)(r1)
0515     PPC_LL  r27, HOST_NV_GPR(R27)(r1)
0516     PPC_LL  r28, HOST_NV_GPR(R28)(r1)
0517     PPC_LL  r29, HOST_NV_GPR(R29)(r1)
0518     PPC_LL  r30, HOST_NV_GPR(R30)(r1)
0519     PPC_LL  r31, HOST_NV_GPR(R31)(r1)
0520 
0521     /* Return to kvm_vcpu_run(). */
0522     mtlr    r5
0523     mtcr    r6
0524     addi    r1, r1, HOST_STACK_SIZE
0525     /* r3 still contains the return code from kvmppc_handle_exit(). */
0526     blr
0527 
0528 /* Registers:
0529  *  r3: vcpu pointer
0530  */
0531 _GLOBAL(__kvmppc_vcpu_run)
0532     stwu    r1, -HOST_STACK_SIZE(r1)
0533     PPC_STL r1, VCPU_HOST_STACK(r3) /* Save stack pointer to vcpu. */
0534 
0535     /* Save host state to stack. */
0536     mr  r4, r3
0537     mflr    r3
0538     mfcr    r5
0539     PPC_STL r3, HOST_STACK_LR(r1)
0540 
0541     stw r5, HOST_CR(r1)
0542 
0543     /* Save host non-volatile register state to stack. */
0544     PPC_STL r14, HOST_NV_GPR(R14)(r1)
0545     PPC_STL r15, HOST_NV_GPR(R15)(r1)
0546     PPC_STL r16, HOST_NV_GPR(R16)(r1)
0547     PPC_STL r17, HOST_NV_GPR(R17)(r1)
0548     PPC_STL r18, HOST_NV_GPR(R18)(r1)
0549     PPC_STL r19, HOST_NV_GPR(R19)(r1)
0550     PPC_STL r20, HOST_NV_GPR(R20)(r1)
0551     PPC_STL r21, HOST_NV_GPR(R21)(r1)
0552     PPC_STL r22, HOST_NV_GPR(R22)(r1)
0553     PPC_STL r23, HOST_NV_GPR(R23)(r1)
0554     PPC_STL r24, HOST_NV_GPR(R24)(r1)
0555     PPC_STL r25, HOST_NV_GPR(R25)(r1)
0556     PPC_STL r26, HOST_NV_GPR(R26)(r1)
0557     PPC_STL r27, HOST_NV_GPR(R27)(r1)
0558     PPC_STL r28, HOST_NV_GPR(R28)(r1)
0559     PPC_STL r29, HOST_NV_GPR(R29)(r1)
0560     PPC_STL r30, HOST_NV_GPR(R30)(r1)
0561     PPC_STL r31, HOST_NV_GPR(R31)(r1)
0562 
0563     /* Load guest non-volatiles. */
0564     PPC_LL  r14, VCPU_GPR(R14)(r4)
0565     PPC_LL  r15, VCPU_GPR(R15)(r4)
0566     PPC_LL  r16, VCPU_GPR(R16)(r4)
0567     PPC_LL  r17, VCPU_GPR(R17)(r4)
0568     PPC_LL  r18, VCPU_GPR(R18)(r4)
0569     PPC_LL  r19, VCPU_GPR(R19)(r4)
0570     PPC_LL  r20, VCPU_GPR(R20)(r4)
0571     PPC_LL  r21, VCPU_GPR(R21)(r4)
0572     PPC_LL  r22, VCPU_GPR(R22)(r4)
0573     PPC_LL  r23, VCPU_GPR(R23)(r4)
0574     PPC_LL  r24, VCPU_GPR(R24)(r4)
0575     PPC_LL  r25, VCPU_GPR(R25)(r4)
0576     PPC_LL  r26, VCPU_GPR(R26)(r4)
0577     PPC_LL  r27, VCPU_GPR(R27)(r4)
0578     PPC_LL  r28, VCPU_GPR(R28)(r4)
0579     PPC_LL  r29, VCPU_GPR(R29)(r4)
0580     PPC_LL  r30, VCPU_GPR(R30)(r4)
0581     PPC_LL  r31, VCPU_GPR(R31)(r4)
0582 
0583 
0584 lightweight_exit:
0585     PPC_STL r2, HOST_R2(r1)
0586 
0587     mfspr   r3, SPRN_PID
0588     stw r3, VCPU_HOST_PID(r4)
0589     lwz r3, VCPU_GUEST_PID(r4)
0590     mtspr   SPRN_PID, r3
0591 
0592     PPC_LL  r11, VCPU_SHARED(r4)
0593     /* Disable MAS register updates via exception */
0594     mfspr   r3, SPRN_EPCR
0595     oris    r3, r3, SPRN_EPCR_DMIUH@h
0596     mtspr   SPRN_EPCR, r3
0597     isync
0598     /* Save host mas4 and mas6 and load guest MAS registers */
0599     mfspr   r3, SPRN_MAS4
0600     stw r3, VCPU_HOST_MAS4(r4)
0601     mfspr   r3, SPRN_MAS6
0602     stw r3, VCPU_HOST_MAS6(r4)
0603     lwz r3, VCPU_SHARED_MAS0(r11)
0604     lwz r5, VCPU_SHARED_MAS1(r11)
0605     PPC_LD(r6, VCPU_SHARED_MAS2, r11)
0606     lwz r7, VCPU_SHARED_MAS7_3+4(r11)
0607     lwz r8, VCPU_SHARED_MAS4(r11)
0608     mtspr   SPRN_MAS0, r3
0609     mtspr   SPRN_MAS1, r5
0610     mtspr   SPRN_MAS2, r6
0611     mtspr   SPRN_MAS3, r7
0612     mtspr   SPRN_MAS4, r8
0613     lwz r3, VCPU_SHARED_MAS6(r11)
0614     lwz r5, VCPU_SHARED_MAS7_3+0(r11)
0615     mtspr   SPRN_MAS6, r3
0616     mtspr   SPRN_MAS7, r5
0617 
0618     /*
0619      * Host interrupt handlers may have clobbered these guest-readable
0620      * SPRGs, so we need to reload them here with the guest's values.
0621      */
0622     lwz r3, VCPU_VRSAVE(r4)
0623     PPC_LD(r5, VCPU_SHARED_SPRG4, r11)
0624     mtspr   SPRN_VRSAVE, r3
0625     PPC_LD(r6, VCPU_SHARED_SPRG5, r11)
0626     mtspr   SPRN_SPRG4W, r5
0627     PPC_LD(r7, VCPU_SHARED_SPRG6, r11)
0628     mtspr   SPRN_SPRG5W, r6
0629     PPC_LD(r8, VCPU_SHARED_SPRG7, r11)
0630     mtspr   SPRN_SPRG6W, r7
0631     PPC_LD(r5, VCPU_SPRG9, r4)
0632     mtspr   SPRN_SPRG7W, r8
0633     mtspr   SPRN_SPRG9, r5
0634 
0635     /* Load some guest volatiles. */
0636     PPC_LL  r3, VCPU_LR(r4)
0637     PPC_LL  r5, VCPU_XER(r4)
0638     PPC_LL  r6, VCPU_CTR(r4)
0639     PPC_LL  r7, VCPU_CR(r4)
0640     PPC_LL  r8, VCPU_PC(r4)
0641     PPC_LD(r9, VCPU_SHARED_MSR, r11)
0642     PPC_LL  r0, VCPU_GPR(R0)(r4)
0643     PPC_LL  r1, VCPU_GPR(R1)(r4)
0644     PPC_LL  r2, VCPU_GPR(R2)(r4)
0645     PPC_LL  r10, VCPU_GPR(R10)(r4)
0646     PPC_LL  r11, VCPU_GPR(R11)(r4)
0647     PPC_LL  r12, VCPU_GPR(R12)(r4)
0648     PPC_LL  r13, VCPU_GPR(R13)(r4)
0649     mtlr    r3
0650     mtxer   r5
0651     mtctr   r6
0652     mtsrr0  r8
0653     mtsrr1  r9
0654 
0655 #ifdef CONFIG_KVM_EXIT_TIMING
0656     /* save enter time */
0657 1:
0658     mfspr   r6, SPRN_TBRU
0659     mfspr   r9, SPRN_TBRL
0660     mfspr   r8, SPRN_TBRU
0661     cmpw    r8, r6
0662     stw r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
0663     bne 1b
0664     stw r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
0665 #endif
0666 
0667     /*
0668      * Don't execute any instruction which can change CR after
0669      * below instruction.
0670      */
0671     mtcr    r7
0672 
0673     /* Finish loading guest volatiles and jump to guest. */
0674     PPC_LL  r5, VCPU_GPR(R5)(r4)
0675     PPC_LL  r6, VCPU_GPR(R6)(r4)
0676     PPC_LL  r7, VCPU_GPR(R7)(r4)
0677     PPC_LL  r8, VCPU_GPR(R8)(r4)
0678     PPC_LL  r9, VCPU_GPR(R9)(r4)
0679 
0680     PPC_LL  r3, VCPU_GPR(R3)(r4)
0681     PPC_LL  r4, VCPU_GPR(R4)(r4)
0682     rfi
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