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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  * Copyright IBM Corp. 2008
0005  * Copyright 2011 Freescale Semiconductor, Inc.
0006  *
0007  * Authors: Hollis Blanchard <hollisb@us.ibm.com>
0008  */
0009 
0010 #include <linux/kvm_host.h>
0011 #include <asm/disassemble.h>
0012 
0013 #include "booke.h"
0014 
0015 #define OP_19_XOP_RFI     50
0016 #define OP_19_XOP_RFCI    51
0017 #define OP_19_XOP_RFDI    39
0018 
0019 #define OP_31_XOP_MFMSR   83
0020 #define OP_31_XOP_WRTEE   131
0021 #define OP_31_XOP_MTMSR   146
0022 #define OP_31_XOP_WRTEEI  163
0023 
0024 static void kvmppc_emul_rfi(struct kvm_vcpu *vcpu)
0025 {
0026     vcpu->arch.regs.nip = vcpu->arch.shared->srr0;
0027     kvmppc_set_msr(vcpu, vcpu->arch.shared->srr1);
0028 }
0029 
0030 static void kvmppc_emul_rfdi(struct kvm_vcpu *vcpu)
0031 {
0032     vcpu->arch.regs.nip = vcpu->arch.dsrr0;
0033     kvmppc_set_msr(vcpu, vcpu->arch.dsrr1);
0034 }
0035 
0036 static void kvmppc_emul_rfci(struct kvm_vcpu *vcpu)
0037 {
0038     vcpu->arch.regs.nip = vcpu->arch.csrr0;
0039     kvmppc_set_msr(vcpu, vcpu->arch.csrr1);
0040 }
0041 
0042 int kvmppc_booke_emulate_op(struct kvm_vcpu *vcpu,
0043                             unsigned int inst, int *advance)
0044 {
0045     int emulated = EMULATE_DONE;
0046     int rs = get_rs(inst);
0047     int rt = get_rt(inst);
0048 
0049     switch (get_op(inst)) {
0050     case 19:
0051         switch (get_xop(inst)) {
0052         case OP_19_XOP_RFI:
0053             kvmppc_emul_rfi(vcpu);
0054             kvmppc_set_exit_type(vcpu, EMULATED_RFI_EXITS);
0055             *advance = 0;
0056             break;
0057 
0058         case OP_19_XOP_RFCI:
0059             kvmppc_emul_rfci(vcpu);
0060             kvmppc_set_exit_type(vcpu, EMULATED_RFCI_EXITS);
0061             *advance = 0;
0062             break;
0063 
0064         case OP_19_XOP_RFDI:
0065             kvmppc_emul_rfdi(vcpu);
0066             kvmppc_set_exit_type(vcpu, EMULATED_RFDI_EXITS);
0067             *advance = 0;
0068             break;
0069 
0070         default:
0071             emulated = EMULATE_FAIL;
0072             break;
0073         }
0074         break;
0075 
0076     case 31:
0077         switch (get_xop(inst)) {
0078 
0079         case OP_31_XOP_MFMSR:
0080             kvmppc_set_gpr(vcpu, rt, vcpu->arch.shared->msr);
0081             kvmppc_set_exit_type(vcpu, EMULATED_MFMSR_EXITS);
0082             break;
0083 
0084         case OP_31_XOP_MTMSR:
0085             kvmppc_set_exit_type(vcpu, EMULATED_MTMSR_EXITS);
0086             kvmppc_set_msr(vcpu, kvmppc_get_gpr(vcpu, rs));
0087             break;
0088 
0089         case OP_31_XOP_WRTEE:
0090             vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
0091                     | (kvmppc_get_gpr(vcpu, rs) & MSR_EE);
0092             kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
0093             break;
0094 
0095         case OP_31_XOP_WRTEEI:
0096             vcpu->arch.shared->msr = (vcpu->arch.shared->msr & ~MSR_EE)
0097                              | (inst & MSR_EE);
0098             kvmppc_set_exit_type(vcpu, EMULATED_WRTEE_EXITS);
0099             break;
0100 
0101         default:
0102             emulated = EMULATE_FAIL;
0103         }
0104 
0105         break;
0106 
0107     default:
0108         emulated = EMULATE_FAIL;
0109     }
0110 
0111     return emulated;
0112 }
0113 
0114 /*
0115  * NOTE: some of these registers are not emulated on BOOKE_HV (GS-mode).
0116  * Their backing store is in real registers, and these functions
0117  * will return the wrong result if called for them in another context
0118  * (such as debugging).
0119  */
0120 int kvmppc_booke_emulate_mtspr(struct kvm_vcpu *vcpu, int sprn, ulong spr_val)
0121 {
0122     int emulated = EMULATE_DONE;
0123     bool debug_inst = false;
0124 
0125     switch (sprn) {
0126     case SPRN_DEAR:
0127         vcpu->arch.shared->dar = spr_val;
0128         break;
0129     case SPRN_ESR:
0130         vcpu->arch.shared->esr = spr_val;
0131         break;
0132     case SPRN_CSRR0:
0133         vcpu->arch.csrr0 = spr_val;
0134         break;
0135     case SPRN_CSRR1:
0136         vcpu->arch.csrr1 = spr_val;
0137         break;
0138     case SPRN_DSRR0:
0139         vcpu->arch.dsrr0 = spr_val;
0140         break;
0141     case SPRN_DSRR1:
0142         vcpu->arch.dsrr1 = spr_val;
0143         break;
0144     case SPRN_IAC1:
0145         /*
0146          * If userspace is debugging guest then guest
0147          * can not access debug registers.
0148          */
0149         if (vcpu->guest_debug)
0150             break;
0151 
0152         debug_inst = true;
0153         vcpu->arch.dbg_reg.iac1 = spr_val;
0154         break;
0155     case SPRN_IAC2:
0156         /*
0157          * If userspace is debugging guest then guest
0158          * can not access debug registers.
0159          */
0160         if (vcpu->guest_debug)
0161             break;
0162 
0163         debug_inst = true;
0164         vcpu->arch.dbg_reg.iac2 = spr_val;
0165         break;
0166 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
0167     case SPRN_IAC3:
0168         /*
0169          * If userspace is debugging guest then guest
0170          * can not access debug registers.
0171          */
0172         if (vcpu->guest_debug)
0173             break;
0174 
0175         debug_inst = true;
0176         vcpu->arch.dbg_reg.iac3 = spr_val;
0177         break;
0178     case SPRN_IAC4:
0179         /*
0180          * If userspace is debugging guest then guest
0181          * can not access debug registers.
0182          */
0183         if (vcpu->guest_debug)
0184             break;
0185 
0186         debug_inst = true;
0187         vcpu->arch.dbg_reg.iac4 = spr_val;
0188         break;
0189 #endif
0190     case SPRN_DAC1:
0191         /*
0192          * If userspace is debugging guest then guest
0193          * can not access debug registers.
0194          */
0195         if (vcpu->guest_debug)
0196             break;
0197 
0198         debug_inst = true;
0199         vcpu->arch.dbg_reg.dac1 = spr_val;
0200         break;
0201     case SPRN_DAC2:
0202         /*
0203          * If userspace is debugging guest then guest
0204          * can not access debug registers.
0205          */
0206         if (vcpu->guest_debug)
0207             break;
0208 
0209         debug_inst = true;
0210         vcpu->arch.dbg_reg.dac2 = spr_val;
0211         break;
0212     case SPRN_DBCR0:
0213         /*
0214          * If userspace is debugging guest then guest
0215          * can not access debug registers.
0216          */
0217         if (vcpu->guest_debug)
0218             break;
0219 
0220         debug_inst = true;
0221         spr_val &= (DBCR0_IDM | DBCR0_IC | DBCR0_BT | DBCR0_TIE |
0222             DBCR0_IAC1 | DBCR0_IAC2 | DBCR0_IAC3 | DBCR0_IAC4  |
0223             DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W);
0224 
0225         vcpu->arch.dbg_reg.dbcr0 = spr_val;
0226         break;
0227     case SPRN_DBCR1:
0228         /*
0229          * If userspace is debugging guest then guest
0230          * can not access debug registers.
0231          */
0232         if (vcpu->guest_debug)
0233             break;
0234 
0235         debug_inst = true;
0236         vcpu->arch.dbg_reg.dbcr1 = spr_val;
0237         break;
0238     case SPRN_DBCR2:
0239         /*
0240          * If userspace is debugging guest then guest
0241          * can not access debug registers.
0242          */
0243         if (vcpu->guest_debug)
0244             break;
0245 
0246         debug_inst = true;
0247         vcpu->arch.dbg_reg.dbcr2 = spr_val;
0248         break;
0249     case SPRN_DBSR:
0250         /*
0251          * If userspace is debugging guest then guest
0252          * can not access debug registers.
0253          */
0254         if (vcpu->guest_debug)
0255             break;
0256 
0257         vcpu->arch.dbsr &= ~spr_val;
0258         if (!(vcpu->arch.dbsr & ~DBSR_IDE))
0259             kvmppc_core_dequeue_debug(vcpu);
0260         break;
0261     case SPRN_TSR:
0262         kvmppc_clr_tsr_bits(vcpu, spr_val);
0263         break;
0264     case SPRN_TCR:
0265         /*
0266          * WRC is a 2-bit field that is supposed to preserve its
0267          * value once written to non-zero.
0268          */
0269         if (vcpu->arch.tcr & TCR_WRC_MASK) {
0270             spr_val &= ~TCR_WRC_MASK;
0271             spr_val |= vcpu->arch.tcr & TCR_WRC_MASK;
0272         }
0273         kvmppc_set_tcr(vcpu, spr_val);
0274         break;
0275 
0276     case SPRN_DECAR:
0277         vcpu->arch.decar = spr_val;
0278         break;
0279     /*
0280      * Note: SPRG4-7 are user-readable.
0281      * These values are loaded into the real SPRGs when resuming the
0282      * guest (PR-mode only).
0283      */
0284     case SPRN_SPRG4:
0285         kvmppc_set_sprg4(vcpu, spr_val);
0286         break;
0287     case SPRN_SPRG5:
0288         kvmppc_set_sprg5(vcpu, spr_val);
0289         break;
0290     case SPRN_SPRG6:
0291         kvmppc_set_sprg6(vcpu, spr_val);
0292         break;
0293     case SPRN_SPRG7:
0294         kvmppc_set_sprg7(vcpu, spr_val);
0295         break;
0296 
0297     case SPRN_IVPR:
0298         vcpu->arch.ivpr = spr_val;
0299 #ifdef CONFIG_KVM_BOOKE_HV
0300         mtspr(SPRN_GIVPR, spr_val);
0301 #endif
0302         break;
0303     case SPRN_IVOR0:
0304         vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL] = spr_val;
0305         break;
0306     case SPRN_IVOR1:
0307         vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK] = spr_val;
0308         break;
0309     case SPRN_IVOR2:
0310         vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE] = spr_val;
0311 #ifdef CONFIG_KVM_BOOKE_HV
0312         mtspr(SPRN_GIVOR2, spr_val);
0313 #endif
0314         break;
0315     case SPRN_IVOR3:
0316         vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE] = spr_val;
0317         break;
0318     case SPRN_IVOR4:
0319         vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL] = spr_val;
0320         break;
0321     case SPRN_IVOR5:
0322         vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT] = spr_val;
0323         break;
0324     case SPRN_IVOR6:
0325         vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM] = spr_val;
0326         break;
0327     case SPRN_IVOR7:
0328         vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL] = spr_val;
0329         break;
0330     case SPRN_IVOR8:
0331         vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL] = spr_val;
0332 #ifdef CONFIG_KVM_BOOKE_HV
0333         mtspr(SPRN_GIVOR8, spr_val);
0334 #endif
0335         break;
0336     case SPRN_IVOR9:
0337         vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL] = spr_val;
0338         break;
0339     case SPRN_IVOR10:
0340         vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER] = spr_val;
0341         break;
0342     case SPRN_IVOR11:
0343         vcpu->arch.ivor[BOOKE_IRQPRIO_FIT] = spr_val;
0344         break;
0345     case SPRN_IVOR12:
0346         vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG] = spr_val;
0347         break;
0348     case SPRN_IVOR13:
0349         vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS] = spr_val;
0350         break;
0351     case SPRN_IVOR14:
0352         vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS] = spr_val;
0353         break;
0354     case SPRN_IVOR15:
0355         vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG] = spr_val;
0356         break;
0357     case SPRN_MCSR:
0358         vcpu->arch.mcsr &= ~spr_val;
0359         break;
0360 #if defined(CONFIG_64BIT)
0361     case SPRN_EPCR:
0362         kvmppc_set_epcr(vcpu, spr_val);
0363 #ifdef CONFIG_KVM_BOOKE_HV
0364         mtspr(SPRN_EPCR, vcpu->arch.shadow_epcr);
0365 #endif
0366         break;
0367 #endif
0368     default:
0369         emulated = EMULATE_FAIL;
0370     }
0371 
0372     if (debug_inst) {
0373         current->thread.debug = vcpu->arch.dbg_reg;
0374         switch_booke_debug_regs(&vcpu->arch.dbg_reg);
0375     }
0376     return emulated;
0377 }
0378 
0379 int kvmppc_booke_emulate_mfspr(struct kvm_vcpu *vcpu, int sprn, ulong *spr_val)
0380 {
0381     int emulated = EMULATE_DONE;
0382 
0383     switch (sprn) {
0384     case SPRN_IVPR:
0385         *spr_val = vcpu->arch.ivpr;
0386         break;
0387     case SPRN_DEAR:
0388         *spr_val = vcpu->arch.shared->dar;
0389         break;
0390     case SPRN_ESR:
0391         *spr_val = vcpu->arch.shared->esr;
0392         break;
0393     case SPRN_EPR:
0394         *spr_val = vcpu->arch.epr;
0395         break;
0396     case SPRN_CSRR0:
0397         *spr_val = vcpu->arch.csrr0;
0398         break;
0399     case SPRN_CSRR1:
0400         *spr_val = vcpu->arch.csrr1;
0401         break;
0402     case SPRN_DSRR0:
0403         *spr_val = vcpu->arch.dsrr0;
0404         break;
0405     case SPRN_DSRR1:
0406         *spr_val = vcpu->arch.dsrr1;
0407         break;
0408     case SPRN_IAC1:
0409         *spr_val = vcpu->arch.dbg_reg.iac1;
0410         break;
0411     case SPRN_IAC2:
0412         *spr_val = vcpu->arch.dbg_reg.iac2;
0413         break;
0414 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
0415     case SPRN_IAC3:
0416         *spr_val = vcpu->arch.dbg_reg.iac3;
0417         break;
0418     case SPRN_IAC4:
0419         *spr_val = vcpu->arch.dbg_reg.iac4;
0420         break;
0421 #endif
0422     case SPRN_DAC1:
0423         *spr_val = vcpu->arch.dbg_reg.dac1;
0424         break;
0425     case SPRN_DAC2:
0426         *spr_val = vcpu->arch.dbg_reg.dac2;
0427         break;
0428     case SPRN_DBCR0:
0429         *spr_val = vcpu->arch.dbg_reg.dbcr0;
0430         if (vcpu->guest_debug)
0431             *spr_val = *spr_val | DBCR0_EDM;
0432         break;
0433     case SPRN_DBCR1:
0434         *spr_val = vcpu->arch.dbg_reg.dbcr1;
0435         break;
0436     case SPRN_DBCR2:
0437         *spr_val = vcpu->arch.dbg_reg.dbcr2;
0438         break;
0439     case SPRN_DBSR:
0440         *spr_val = vcpu->arch.dbsr;
0441         break;
0442     case SPRN_TSR:
0443         *spr_val = vcpu->arch.tsr;
0444         break;
0445     case SPRN_TCR:
0446         *spr_val = vcpu->arch.tcr;
0447         break;
0448 
0449     case SPRN_IVOR0:
0450         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_CRITICAL];
0451         break;
0452     case SPRN_IVOR1:
0453         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_MACHINE_CHECK];
0454         break;
0455     case SPRN_IVOR2:
0456         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DATA_STORAGE];
0457         break;
0458     case SPRN_IVOR3:
0459         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_INST_STORAGE];
0460         break;
0461     case SPRN_IVOR4:
0462         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_EXTERNAL];
0463         break;
0464     case SPRN_IVOR5:
0465         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ALIGNMENT];
0466         break;
0467     case SPRN_IVOR6:
0468         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_PROGRAM];
0469         break;
0470     case SPRN_IVOR7:
0471         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FP_UNAVAIL];
0472         break;
0473     case SPRN_IVOR8:
0474         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_SYSCALL];
0475         break;
0476     case SPRN_IVOR9:
0477         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_AP_UNAVAIL];
0478         break;
0479     case SPRN_IVOR10:
0480         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DECREMENTER];
0481         break;
0482     case SPRN_IVOR11:
0483         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_FIT];
0484         break;
0485     case SPRN_IVOR12:
0486         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_WATCHDOG];
0487         break;
0488     case SPRN_IVOR13:
0489         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DTLB_MISS];
0490         break;
0491     case SPRN_IVOR14:
0492         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_ITLB_MISS];
0493         break;
0494     case SPRN_IVOR15:
0495         *spr_val = vcpu->arch.ivor[BOOKE_IRQPRIO_DEBUG];
0496         break;
0497     case SPRN_MCSR:
0498         *spr_val = vcpu->arch.mcsr;
0499         break;
0500 #if defined(CONFIG_64BIT)
0501     case SPRN_EPCR:
0502         *spr_val = vcpu->arch.epcr;
0503         break;
0504 #endif
0505 
0506     default:
0507         emulated = EMULATE_FAIL;
0508     }
0509 
0510     return emulated;
0511 }
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