powerpc/kvm/book3s_hv_tm_builtin.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright 2017 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
0004  */
0005
0006 #include <linux/kvm_host.h>
0007
0008 #include <asm/kvm_ppc.h>
0009 #include <asm/kvm_book3s.h>
0010 #include <asm/kvm_book3s_64.h>
0011 #include <asm/reg.h>
0012 #include <asm/ppc-opcode.h>
0013
0014 /*
0015  * This handles the cases where the guest is in real suspend mode
0016  * and we want to get back to the guest without dooming the transaction.
0017  * The caller has checked that the guest is in real-suspend mode
0018  * (MSR[TS] = S and the fake-suspend flag is not set).
0019  */
0020 int kvmhv_p9_tm_emulation_early(struct kvm_vcpu *vcpu)
0021 {
0022     u32 instr = vcpu->arch.emul_inst;
0023     u64 newmsr, msr, bescr;
0024     int rs;
0025
0026     /*
0027      * rfid, rfebb, and mtmsrd encode bit 31 = 0 since it's a reserved bit
0028      * in these instructions, so masking bit 31 out doesn't change these
0029      * instructions. For the tsr. instruction if bit 31 = 0 then it is per
0030      * ISA an invalid form, however P9 UM, in section 4.6.10 Book II Invalid
0031      * Forms, informs specifically that ignoring bit 31 is an acceptable way
0032      * to handle TM-related invalid forms that have bit 31 = 0. Moreover,
0033      * for emulation purposes both forms (w/ and wo/ bit 31 set) can
0034      * generate a softpatch interrupt. Hence both forms are handled below
0035      * for tsr. to make them behave the same way.
0036      */
0037     switch (instr & PO_XOP_OPCODE_MASK) {
0038     case PPC_INST_RFID:
0039         /* XXX do we need to check for PR=0 here? */
0040         newmsr = vcpu->arch.shregs.srr1;
0041         /* should only get here for Sx -> T1 transition */
0042         if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM)))
0043             return 0;
0044         newmsr = sanitize_msr(newmsr);
0045         vcpu->arch.shregs.msr = newmsr;
0046         vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
0047         vcpu->arch.regs.nip = vcpu->arch.shregs.srr0;
0048         return 1;
0049
0050     case PPC_INST_RFEBB:
0051         /* check for PR=1 and arch 2.06 bit set in PCR */
0052         msr = vcpu->arch.shregs.msr;
0053         if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206))
0054             return 0;
0055         /* check EBB facility is available */
0056         if (!(vcpu->arch.hfscr & HFSCR_EBB) ||
0057             ((msr & MSR_PR) && !(mfspr(SPRN_FSCR) & FSCR_EBB)))
0058             return 0;
0059         bescr = mfspr(SPRN_BESCR);
0060         /* expect to see a S->T transition requested */
0061         if (((bescr >> 30) & 3) != 2)
0062             return 0;
0063         bescr &= ~BESCR_GE;
0064         if (instr & (1 << 11))
0065             bescr |= BESCR_GE;
0066         mtspr(SPRN_BESCR, bescr);
0067         msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
0068         vcpu->arch.shregs.msr = msr;
0069         vcpu->arch.cfar = vcpu->arch.regs.nip - 4;
0070         vcpu->arch.regs.nip = mfspr(SPRN_EBBRR);
0071         return 1;
0072
0073     case PPC_INST_MTMSRD:
0074         /* XXX do we need to check for PR=0 here? */
0075         rs = (instr >> 21) & 0x1f;
0076         newmsr = kvmppc_get_gpr(vcpu, rs);
0077         msr = vcpu->arch.shregs.msr;
0078         /* check this is a Sx -> T1 transition */
0079         if (!(MSR_TM_TRANSACTIONAL(newmsr) && (newmsr & MSR_TM)))
0080             return 0;
0081         /* mtmsrd doesn't change LE */
0082         newmsr = (newmsr & ~MSR_LE) | (msr & MSR_LE);
0083         newmsr = sanitize_msr(newmsr);
0084         vcpu->arch.shregs.msr = newmsr;
0085         return 1;
0086
0087     /* ignore bit 31, see comment above */
0088     case (PPC_INST_TSR & PO_XOP_OPCODE_MASK):
0089         /* we know the MSR has the TS field = S (0b01) here */
0090         msr = vcpu->arch.shregs.msr;
0091         /* check for PR=1 and arch 2.06 bit set in PCR */
0092         if ((msr & MSR_PR) && (vcpu->arch.vcore->pcr & PCR_ARCH_206))
0093             return 0;
0094         /* check for TM disabled in the HFSCR or MSR */
0095         if (!(vcpu->arch.hfscr & HFSCR_TM) || !(msr & MSR_TM))
0096             return 0;
0097         /* L=1 => tresume => set TS to T (0b10) */
0098         if (instr & (1 << 21))
0099             vcpu->arch.shregs.msr = (msr & ~MSR_TS_MASK) | MSR_TS_T;
0100         /* Set CR0 to 0b0010 */
0101         vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) |
0102             0x20000000;
0103         return 1;
0104     }
0105
0106     return 0;
0107 }
0108
0109 /*
0110  * This is called when we are returning to a guest in TM transactional
0111  * state.  We roll the guest state back to the checkpointed state.
0112  */
0113 void kvmhv_emulate_tm_rollback(struct kvm_vcpu *vcpu)
0114 {
0115     vcpu->arch.shregs.msr &= ~MSR_TS_MASK;  /* go to N state */
0116     vcpu->arch.regs.nip = vcpu->arch.tfhar;
0117     copy_from_checkpoint(vcpu);
0118     vcpu->arch.regs.ccr = (vcpu->arch.regs.ccr & 0x0fffffff) | 0xa0000000;
0119 }