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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Signal trampoline for 64 bits processes in a ppc64 kernel for
0004  * use in the vDSO
0005  *
0006  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
0007  * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
0008  */
0009 #include <asm/cache.h>      /* IFETCH_ALIGN_BYTES */
0010 #include <asm/processor.h>
0011 #include <asm/ppc_asm.h>
0012 #include <asm/unistd.h>
0013 #include <asm/vdso.h>
0014 #include <asm/ptrace.h>     /* XXX for __SIGNAL_FRAMESIZE */
0015 
0016     .text
0017 
0018 /*
0019  * __kernel_start_sigtramp_rt64 and __kernel_sigtramp_rt64 together
0020  * are one function split in two parts. The kernel jumps to the former
0021  * and the signal handler indirectly (by blr) returns to the latter.
0022  * __kernel_sigtramp_rt64 needs to point to the return address so
0023  * glibc can correctly identify the trampoline stack frame.
0024  */
0025     .balign 8
0026     .balign IFETCH_ALIGN_BYTES
0027 V_FUNCTION_BEGIN(__kernel_start_sigtramp_rt64)
0028 .Lsigrt_start:
0029     bctrl   /* call the handler */
0030 V_FUNCTION_END(__kernel_start_sigtramp_rt64)
0031 V_FUNCTION_BEGIN(__kernel_sigtramp_rt64)
0032     addi    r1, r1, __SIGNAL_FRAMESIZE
0033     li  r0,__NR_rt_sigreturn
0034     sc
0035 .Lsigrt_end:
0036 V_FUNCTION_END(__kernel_sigtramp_rt64)
0037 /* The .balign 8 above and the following zeros mimic the old stack
0038    trampoline layout.  The last magic value is the ucontext pointer,
0039    chosen in such a way that older libgcc unwind code returns a zero
0040    for a sigcontext pointer.  */
0041     .long 0,0,0
0042     .quad 0,-21*8
0043 
0044 /* Register r1 can be found at offset 8 of a pt_regs structure.
0045    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
0046 #define cfa_save \
0047   .byte 0x0f;           /* DW_CFA_def_cfa_expression */     \
0048   .uleb128 9f - 1f;     /*   length */              \
0049 1:                                  \
0050   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0051   .byte 0x06;           /*     DW_OP_deref */           \
0052   .byte 0x23; .uleb128 RSIZE;   /*     DW_OP_plus_uconst */     \
0053   .byte 0x06;           /*     DW_OP_deref */           \
0054 9:
0055 
0056 /* Register REGNO can be found at offset OFS of a pt_regs structure.
0057    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
0058 #define rsave(regno, ofs) \
0059   .byte 0x10;           /* DW_CFA_expression */         \
0060   .uleb128 regno;       /*   regno */               \
0061   .uleb128 9f - 1f;     /*   length */              \
0062 1:                                  \
0063   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0064   .byte 0x06;           /*     DW_OP_deref */           \
0065   .ifne ofs;                                \
0066     .byte 0x23; .uleb128 ofs;   /*     DW_OP_plus_uconst */     \
0067   .endif;                               \
0068 9:
0069 
0070 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
0071    of the VMX reg struct.  A pointer to the VMX reg struct is at VREGS in
0072    the pt_regs struct.  This macro is for REGNO == 0, and contains
0073    'subroutines' that the other macros jump to.  */
0074 #define vsave_msr0(regno) \
0075   .byte 0x10;           /* DW_CFA_expression */         \
0076   .uleb128 regno + 77;      /*   regno */               \
0077   .uleb128 9f - 1f;     /*   length */              \
0078 1:                                  \
0079   .byte 0x30 + regno;       /*     DW_OP_lit0 */            \
0080 2:                                  \
0081   .byte 0x40;           /*     DW_OP_lit16 */           \
0082   .byte 0x1e;           /*     DW_OP_mul */         \
0083 3:                                  \
0084   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0085   .byte 0x06;           /*     DW_OP_deref */           \
0086   .byte 0x12;           /*     DW_OP_dup */         \
0087   .byte 0x23;           /*     DW_OP_plus_uconst */     \
0088     .uleb128 33*RSIZE;      /*       msr offset */          \
0089   .byte 0x06;           /*     DW_OP_deref */           \
0090   .byte 0x0c; .long 1 << 25;    /*     DW_OP_const4u */         \
0091   .byte 0x1a;           /*     DW_OP_and */         \
0092   .byte 0x12;           /*     DW_OP_dup, ret 0 if bra taken */ \
0093   .byte 0x30;           /*     DW_OP_lit0 */            \
0094   .byte 0x29;           /*     DW_OP_eq */          \
0095   .byte 0x28; .short 0x7fff;    /*     DW_OP_bra to end */      \
0096   .byte 0x13;           /*     DW_OP_drop, pop the 0 */     \
0097   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */     \
0098   .byte 0x06;           /*     DW_OP_deref */           \
0099   .byte 0x22;           /*     DW_OP_plus */            \
0100   .byte 0x2f; .short 0x7fff;    /*     DW_OP_skip to end */     \
0101 9:
0102 
0103 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
0104    of the VMX reg struct.  REGNO is 1 thru 31.  */
0105 #define vsave_msr1(regno) \
0106   .byte 0x10;           /* DW_CFA_expression */         \
0107   .uleb128 regno + 77;      /*   regno */               \
0108   .uleb128 9f - 1f;     /*   length */              \
0109 1:                                  \
0110   .byte 0x30 + regno;       /*     DW_OP_lit n */           \
0111   .byte 0x2f; .short 2b - 9f;   /*     DW_OP_skip */            \
0112 9:
0113 
0114 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
0115    the VMX save block.  */
0116 #define vsave_msr2(regno, ofs) \
0117   .byte 0x10;           /* DW_CFA_expression */         \
0118   .uleb128 regno + 77;      /*   regno */               \
0119   .uleb128 9f - 1f;     /*   length */              \
0120 1:                                  \
0121   .byte 0x0a; .short ofs;   /*     DW_OP_const2u */         \
0122   .byte 0x2f; .short 3b - 9f;   /*     DW_OP_skip */            \
0123 9:
0124 
0125 /* VMX register REGNO is at offset OFS of the VMX save area.  */
0126 #define vsave(regno, ofs) \
0127   .byte 0x10;           /* DW_CFA_expression */         \
0128   .uleb128 regno + 77;      /*   regno */               \
0129   .uleb128 9f - 1f;     /*   length */              \
0130 1:                                  \
0131   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0132   .byte 0x06;           /*     DW_OP_deref */           \
0133   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */     \
0134   .byte 0x06;           /*     DW_OP_deref */           \
0135   .byte 0x23; .uleb128 ofs; /*     DW_OP_plus_uconst */     \
0136 9:
0137 
0138 /* This is where the pt_regs pointer can be found on the stack.  */
0139 #define PTREGS  128+168+56
0140 
0141 /* Size of regs.  */
0142 #define RSIZE   8
0143 
0144 /* Size of CR reg in DWARF unwind info. */
0145 #define CRSIZE  4
0146 
0147 /* Offset of CR reg within a full word. */
0148 #ifdef __LITTLE_ENDIAN__
0149 #define CROFF 0
0150 #else
0151 #define CROFF (RSIZE - CRSIZE)
0152 #endif
0153 
0154 /* This is the offset of the VMX reg pointer.  */
0155 #define VREGS   48*RSIZE+33*8
0156 
0157 /* Describe where general purpose regs are saved.  */
0158 #define EH_FRAME_GEN \
0159   cfa_save;                             \
0160   rsave ( 0,  0*RSIZE);                         \
0161   rsave ( 2,  2*RSIZE);                         \
0162   rsave ( 3,  3*RSIZE);                         \
0163   rsave ( 4,  4*RSIZE);                         \
0164   rsave ( 5,  5*RSIZE);                         \
0165   rsave ( 6,  6*RSIZE);                         \
0166   rsave ( 7,  7*RSIZE);                         \
0167   rsave ( 8,  8*RSIZE);                         \
0168   rsave ( 9,  9*RSIZE);                         \
0169   rsave (10, 10*RSIZE);                         \
0170   rsave (11, 11*RSIZE);                         \
0171   rsave (12, 12*RSIZE);                         \
0172   rsave (13, 13*RSIZE);                         \
0173   rsave (14, 14*RSIZE);                         \
0174   rsave (15, 15*RSIZE);                         \
0175   rsave (16, 16*RSIZE);                         \
0176   rsave (17, 17*RSIZE);                         \
0177   rsave (18, 18*RSIZE);                         \
0178   rsave (19, 19*RSIZE);                         \
0179   rsave (20, 20*RSIZE);                         \
0180   rsave (21, 21*RSIZE);                         \
0181   rsave (22, 22*RSIZE);                         \
0182   rsave (23, 23*RSIZE);                         \
0183   rsave (24, 24*RSIZE);                         \
0184   rsave (25, 25*RSIZE);                         \
0185   rsave (26, 26*RSIZE);                         \
0186   rsave (27, 27*RSIZE);                         \
0187   rsave (28, 28*RSIZE);                         \
0188   rsave (29, 29*RSIZE);                         \
0189   rsave (30, 30*RSIZE);                         \
0190   rsave (31, 31*RSIZE);                         \
0191   rsave (67, 32*RSIZE);     /* ap, used as temp for nip */      \
0192   rsave (65, 36*RSIZE);     /* lr */                \
0193   rsave (68, 38*RSIZE + CROFF); /* cr fields */             \
0194   rsave (69, 38*RSIZE + CROFF);                     \
0195   rsave (70, 38*RSIZE + CROFF);                     \
0196   rsave (71, 38*RSIZE + CROFF);                     \
0197   rsave (72, 38*RSIZE + CROFF);                     \
0198   rsave (73, 38*RSIZE + CROFF);                     \
0199   rsave (74, 38*RSIZE + CROFF);                     \
0200   rsave (75, 38*RSIZE + CROFF)
0201 
0202 /* Describe where the FP regs are saved.  */
0203 #define EH_FRAME_FP \
0204   rsave (32, 48*RSIZE +  0*8);                      \
0205   rsave (33, 48*RSIZE +  1*8);                      \
0206   rsave (34, 48*RSIZE +  2*8);                      \
0207   rsave (35, 48*RSIZE +  3*8);                      \
0208   rsave (36, 48*RSIZE +  4*8);                      \
0209   rsave (37, 48*RSIZE +  5*8);                      \
0210   rsave (38, 48*RSIZE +  6*8);                      \
0211   rsave (39, 48*RSIZE +  7*8);                      \
0212   rsave (40, 48*RSIZE +  8*8);                      \
0213   rsave (41, 48*RSIZE +  9*8);                      \
0214   rsave (42, 48*RSIZE + 10*8);                      \
0215   rsave (43, 48*RSIZE + 11*8);                      \
0216   rsave (44, 48*RSIZE + 12*8);                      \
0217   rsave (45, 48*RSIZE + 13*8);                      \
0218   rsave (46, 48*RSIZE + 14*8);                      \
0219   rsave (47, 48*RSIZE + 15*8);                      \
0220   rsave (48, 48*RSIZE + 16*8);                      \
0221   rsave (49, 48*RSIZE + 17*8);                      \
0222   rsave (50, 48*RSIZE + 18*8);                      \
0223   rsave (51, 48*RSIZE + 19*8);                      \
0224   rsave (52, 48*RSIZE + 20*8);                      \
0225   rsave (53, 48*RSIZE + 21*8);                      \
0226   rsave (54, 48*RSIZE + 22*8);                      \
0227   rsave (55, 48*RSIZE + 23*8);                      \
0228   rsave (56, 48*RSIZE + 24*8);                      \
0229   rsave (57, 48*RSIZE + 25*8);                      \
0230   rsave (58, 48*RSIZE + 26*8);                      \
0231   rsave (59, 48*RSIZE + 27*8);                      \
0232   rsave (60, 48*RSIZE + 28*8);                      \
0233   rsave (61, 48*RSIZE + 29*8);                      \
0234   rsave (62, 48*RSIZE + 30*8);                      \
0235   rsave (63, 48*RSIZE + 31*8)
0236 
0237 /* Describe where the VMX regs are saved.  */
0238 #ifdef CONFIG_ALTIVEC
0239 #define EH_FRAME_VMX \
0240   vsave_msr0 ( 0);                          \
0241   vsave_msr1 ( 1);                          \
0242   vsave_msr1 ( 2);                          \
0243   vsave_msr1 ( 3);                          \
0244   vsave_msr1 ( 4);                          \
0245   vsave_msr1 ( 5);                          \
0246   vsave_msr1 ( 6);                          \
0247   vsave_msr1 ( 7);                          \
0248   vsave_msr1 ( 8);                          \
0249   vsave_msr1 ( 9);                          \
0250   vsave_msr1 (10);                          \
0251   vsave_msr1 (11);                          \
0252   vsave_msr1 (12);                          \
0253   vsave_msr1 (13);                          \
0254   vsave_msr1 (14);                          \
0255   vsave_msr1 (15);                          \
0256   vsave_msr1 (16);                          \
0257   vsave_msr1 (17);                          \
0258   vsave_msr1 (18);                          \
0259   vsave_msr1 (19);                          \
0260   vsave_msr1 (20);                          \
0261   vsave_msr1 (21);                          \
0262   vsave_msr1 (22);                          \
0263   vsave_msr1 (23);                          \
0264   vsave_msr1 (24);                          \
0265   vsave_msr1 (25);                          \
0266   vsave_msr1 (26);                          \
0267   vsave_msr1 (27);                          \
0268   vsave_msr1 (28);                          \
0269   vsave_msr1 (29);                          \
0270   vsave_msr1 (30);                          \
0271   vsave_msr1 (31);                          \
0272   vsave_msr2 (33, 32*16+12);                        \
0273   vsave      (32, 33*16)
0274 #else
0275 #define EH_FRAME_VMX
0276 #endif
0277 
0278     .section .eh_frame,"a",@progbits
0279 .Lcie:
0280     .long .Lcie_end - .Lcie_start
0281 .Lcie_start:
0282     .long 0         /* CIE ID */
0283     .byte 1         /* Version number */
0284     .string "zRS"       /* NUL-terminated augmentation string */
0285     .uleb128 4      /* Code alignment factor */
0286     .sleb128 -8     /* Data alignment factor */
0287     .byte 67        /* Return address register column, ap */
0288     .uleb128 1      /* Augmentation value length */
0289     .byte 0x14      /* DW_EH_PE_pcrel | DW_EH_PE_udata8. */
0290     .byte 0x0c,1,0      /* DW_CFA_def_cfa: r1 ofs 0 */
0291     .balign 8
0292 .Lcie_end:
0293 
0294     .long .Lfde0_end - .Lfde0_start
0295 .Lfde0_start:
0296     .long .Lfde0_start - .Lcie  /* CIE pointer. */
0297     .quad .Lsigrt_start - .     /* PC start, length */
0298     .quad .Lsigrt_end - .Lsigrt_start
0299     .uleb128 0          /* Augmentation */
0300     EH_FRAME_GEN
0301     EH_FRAME_FP
0302     EH_FRAME_VMX
0303 # Do we really need to describe the frame at this point?  ie. will
0304 # we ever have some call chain that returns somewhere past the addi?
0305 # I don't think so, since gcc doesn't support async signals.
0306 #   .byte 0x41      /* DW_CFA_advance_loc 1*4 */
0307 #undef PTREGS
0308 #define PTREGS 168+56
0309 #   EH_FRAME_GEN
0310 #   EH_FRAME_FP
0311 #   EH_FRAME_VMX
0312     .balign 8
0313 .Lfde0_end:
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