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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Signal trampolines for 32 bits processes in a ppc64 kernel for
0004  * use in the vDSO
0005  *
0006  * Copyright (C) 2004 Benjamin Herrenschmuidt (benh@kernel.crashing.org), IBM Corp.
0007  * Copyright (C) 2004 Alan Modra (amodra@au.ibm.com)), IBM Corp.
0008  */
0009 #include <asm/processor.h>
0010 #include <asm/ppc_asm.h>
0011 #include <asm/unistd.h>
0012 #include <asm/vdso.h>
0013 
0014     .text
0015 
0016 /* The nop here is a hack.  The dwarf2 unwind routines subtract 1 from
0017    the return address to get an address in the middle of the presumed
0018    call instruction.  Since we don't have a call here, we artificially
0019    extend the range covered by the unwind info by adding a nop before
0020    the real start.  */
0021     nop
0022 V_FUNCTION_BEGIN(__kernel_sigtramp32)
0023 .Lsig_start = . - 4
0024     li  r0,__NR_sigreturn
0025     sc
0026 .Lsig_end:
0027 V_FUNCTION_END(__kernel_sigtramp32)
0028 
0029 .Lsigrt_start:
0030     nop
0031 V_FUNCTION_BEGIN(__kernel_sigtramp_rt32)
0032     li  r0,__NR_rt_sigreturn
0033     sc
0034 .Lsigrt_end:
0035 V_FUNCTION_END(__kernel_sigtramp_rt32)
0036 
0037     .section .eh_frame,"a",@progbits
0038 
0039 /* Register r1 can be found at offset 4 of a pt_regs structure.
0040    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
0041 #define cfa_save \
0042   .byte 0x0f;           /* DW_CFA_def_cfa_expression */     \
0043   .uleb128 9f - 1f;     /*   length */              \
0044 1:                                  \
0045   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0046   .byte 0x06;           /*     DW_OP_deref */           \
0047   .byte 0x23; .uleb128 RSIZE;   /*     DW_OP_plus_uconst */     \
0048   .byte 0x06;           /*     DW_OP_deref */           \
0049 9:
0050 
0051 /* Register REGNO can be found at offset OFS of a pt_regs structure.
0052    A pointer to the pt_regs is stored in memory at the old sp plus PTREGS.  */
0053 #define rsave(regno, ofs) \
0054   .byte 0x10;           /* DW_CFA_expression */         \
0055   .uleb128 regno;       /*   regno */               \
0056   .uleb128 9f - 1f;     /*   length */              \
0057 1:                                  \
0058   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0059   .byte 0x06;           /*     DW_OP_deref */           \
0060   .ifne ofs;                                \
0061     .byte 0x23; .uleb128 ofs;   /*     DW_OP_plus_uconst */     \
0062   .endif;                               \
0063 9:
0064 
0065 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
0066    of the VMX reg struct.  The VMX reg struct is at offset VREGS of
0067    the pt_regs struct.  This macro is for REGNO == 0, and contains
0068    'subroutines' that the other macros jump to.  */
0069 #define vsave_msr0(regno) \
0070   .byte 0x10;           /* DW_CFA_expression */         \
0071   .uleb128 regno + 77;      /*   regno */               \
0072   .uleb128 9f - 1f;     /*   length */              \
0073 1:                                  \
0074   .byte 0x30 + regno;       /*     DW_OP_lit0 */            \
0075 2:                                  \
0076   .byte 0x40;           /*     DW_OP_lit16 */           \
0077   .byte 0x1e;           /*     DW_OP_mul */         \
0078 3:                                  \
0079   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0080   .byte 0x06;           /*     DW_OP_deref */           \
0081   .byte 0x12;           /*     DW_OP_dup */         \
0082   .byte 0x23;           /*     DW_OP_plus_uconst */     \
0083     .uleb128 33*RSIZE;      /*       msr offset */          \
0084   .byte 0x06;           /*     DW_OP_deref */           \
0085   .byte 0x0c; .long 1 << 25;    /*     DW_OP_const4u */         \
0086   .byte 0x1a;           /*     DW_OP_and */         \
0087   .byte 0x12;           /*     DW_OP_dup, ret 0 if bra taken */ \
0088   .byte 0x30;           /*     DW_OP_lit0 */            \
0089   .byte 0x29;           /*     DW_OP_eq */          \
0090   .byte 0x28; .short 0x7fff;    /*     DW_OP_bra to end */      \
0091   .byte 0x13;           /*     DW_OP_drop, pop the 0 */     \
0092   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */     \
0093   .byte 0x22;           /*     DW_OP_plus */            \
0094   .byte 0x2f; .short 0x7fff;    /*     DW_OP_skip to end */     \
0095 9:
0096 
0097 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset REGNO*16
0098    of the VMX reg struct.  REGNO is 1 thru 31.  */
0099 #define vsave_msr1(regno) \
0100   .byte 0x10;           /* DW_CFA_expression */         \
0101   .uleb128 regno + 77;      /*   regno */               \
0102   .uleb128 9f - 1f;     /*   length */              \
0103 1:                                  \
0104   .byte 0x30 + regno;       /*     DW_OP_lit n */           \
0105   .byte 0x2f; .short 2b - 9f;   /*     DW_OP_skip */            \
0106 9:
0107 
0108 /* If msr bit 1<<25 is set, then VMX register REGNO is at offset OFS of
0109    the VMX save block.  */
0110 #define vsave_msr2(regno, ofs) \
0111   .byte 0x10;           /* DW_CFA_expression */         \
0112   .uleb128 regno + 77;      /*   regno */               \
0113   .uleb128 9f - 1f;     /*   length */              \
0114 1:                                  \
0115   .byte 0x0a; .short ofs;   /*     DW_OP_const2u */         \
0116   .byte 0x2f; .short 3b - 9f;   /*     DW_OP_skip */            \
0117 9:
0118 
0119 /* VMX register REGNO is at offset OFS of the VMX save area.  */
0120 #define vsave(regno, ofs) \
0121   .byte 0x10;           /* DW_CFA_expression */         \
0122   .uleb128 regno + 77;      /*   regno */               \
0123   .uleb128 9f - 1f;     /*   length */              \
0124 1:                                  \
0125   .byte 0x71; .sleb128 PTREGS;  /*     DW_OP_breg1 */           \
0126   .byte 0x06;           /*     DW_OP_deref */           \
0127   .byte 0x23; .uleb128 VREGS;   /*     DW_OP_plus_uconst */     \
0128   .byte 0x23; .uleb128 ofs; /*     DW_OP_plus_uconst */     \
0129 9:
0130 
0131 /* This is where the pt_regs pointer can be found on the stack.  */
0132 #define PTREGS 64+28
0133 
0134 /* Size of regs.  */
0135 #define RSIZE 4
0136 
0137 /* This is the offset of the VMX regs.  */
0138 #define VREGS 48*RSIZE+34*8
0139 
0140 /* Describe where general purpose regs are saved.  */
0141 #define EH_FRAME_GEN \
0142   cfa_save;                             \
0143   rsave ( 0,  0*RSIZE);                         \
0144   rsave ( 2,  2*RSIZE);                         \
0145   rsave ( 3,  3*RSIZE);                         \
0146   rsave ( 4,  4*RSIZE);                         \
0147   rsave ( 5,  5*RSIZE);                         \
0148   rsave ( 6,  6*RSIZE);                         \
0149   rsave ( 7,  7*RSIZE);                         \
0150   rsave ( 8,  8*RSIZE);                         \
0151   rsave ( 9,  9*RSIZE);                         \
0152   rsave (10, 10*RSIZE);                         \
0153   rsave (11, 11*RSIZE);                         \
0154   rsave (12, 12*RSIZE);                         \
0155   rsave (13, 13*RSIZE);                         \
0156   rsave (14, 14*RSIZE);                         \
0157   rsave (15, 15*RSIZE);                         \
0158   rsave (16, 16*RSIZE);                         \
0159   rsave (17, 17*RSIZE);                         \
0160   rsave (18, 18*RSIZE);                         \
0161   rsave (19, 19*RSIZE);                         \
0162   rsave (20, 20*RSIZE);                         \
0163   rsave (21, 21*RSIZE);                         \
0164   rsave (22, 22*RSIZE);                         \
0165   rsave (23, 23*RSIZE);                         \
0166   rsave (24, 24*RSIZE);                         \
0167   rsave (25, 25*RSIZE);                         \
0168   rsave (26, 26*RSIZE);                         \
0169   rsave (27, 27*RSIZE);                         \
0170   rsave (28, 28*RSIZE);                         \
0171   rsave (29, 29*RSIZE);                         \
0172   rsave (30, 30*RSIZE);                         \
0173   rsave (31, 31*RSIZE);                         \
0174   rsave (67, 32*RSIZE);     /* ap, used as temp for nip */      \
0175   rsave (65, 36*RSIZE);     /* lr */                \
0176   rsave (70, 38*RSIZE)      /* cr */
0177 
0178 /* Describe where the FP regs are saved.  */
0179 #define EH_FRAME_FP \
0180   rsave (32, 48*RSIZE +  0*8);                      \
0181   rsave (33, 48*RSIZE +  1*8);                      \
0182   rsave (34, 48*RSIZE +  2*8);                      \
0183   rsave (35, 48*RSIZE +  3*8);                      \
0184   rsave (36, 48*RSIZE +  4*8);                      \
0185   rsave (37, 48*RSIZE +  5*8);                      \
0186   rsave (38, 48*RSIZE +  6*8);                      \
0187   rsave (39, 48*RSIZE +  7*8);                      \
0188   rsave (40, 48*RSIZE +  8*8);                      \
0189   rsave (41, 48*RSIZE +  9*8);                      \
0190   rsave (42, 48*RSIZE + 10*8);                      \
0191   rsave (43, 48*RSIZE + 11*8);                      \
0192   rsave (44, 48*RSIZE + 12*8);                      \
0193   rsave (45, 48*RSIZE + 13*8);                      \
0194   rsave (46, 48*RSIZE + 14*8);                      \
0195   rsave (47, 48*RSIZE + 15*8);                      \
0196   rsave (48, 48*RSIZE + 16*8);                      \
0197   rsave (49, 48*RSIZE + 17*8);                      \
0198   rsave (50, 48*RSIZE + 18*8);                      \
0199   rsave (51, 48*RSIZE + 19*8);                      \
0200   rsave (52, 48*RSIZE + 20*8);                      \
0201   rsave (53, 48*RSIZE + 21*8);                      \
0202   rsave (54, 48*RSIZE + 22*8);                      \
0203   rsave (55, 48*RSIZE + 23*8);                      \
0204   rsave (56, 48*RSIZE + 24*8);                      \
0205   rsave (57, 48*RSIZE + 25*8);                      \
0206   rsave (58, 48*RSIZE + 26*8);                      \
0207   rsave (59, 48*RSIZE + 27*8);                      \
0208   rsave (60, 48*RSIZE + 28*8);                      \
0209   rsave (61, 48*RSIZE + 29*8);                      \
0210   rsave (62, 48*RSIZE + 30*8);                      \
0211   rsave (63, 48*RSIZE + 31*8)
0212 
0213 /* Describe where the VMX regs are saved.  */
0214 #ifdef CONFIG_ALTIVEC
0215 #define EH_FRAME_VMX \
0216   vsave_msr0 ( 0);                          \
0217   vsave_msr1 ( 1);                          \
0218   vsave_msr1 ( 2);                          \
0219   vsave_msr1 ( 3);                          \
0220   vsave_msr1 ( 4);                          \
0221   vsave_msr1 ( 5);                          \
0222   vsave_msr1 ( 6);                          \
0223   vsave_msr1 ( 7);                          \
0224   vsave_msr1 ( 8);                          \
0225   vsave_msr1 ( 9);                          \
0226   vsave_msr1 (10);                          \
0227   vsave_msr1 (11);                          \
0228   vsave_msr1 (12);                          \
0229   vsave_msr1 (13);                          \
0230   vsave_msr1 (14);                          \
0231   vsave_msr1 (15);                          \
0232   vsave_msr1 (16);                          \
0233   vsave_msr1 (17);                          \
0234   vsave_msr1 (18);                          \
0235   vsave_msr1 (19);                          \
0236   vsave_msr1 (20);                          \
0237   vsave_msr1 (21);                          \
0238   vsave_msr1 (22);                          \
0239   vsave_msr1 (23);                          \
0240   vsave_msr1 (24);                          \
0241   vsave_msr1 (25);                          \
0242   vsave_msr1 (26);                          \
0243   vsave_msr1 (27);                          \
0244   vsave_msr1 (28);                          \
0245   vsave_msr1 (29);                          \
0246   vsave_msr1 (30);                          \
0247   vsave_msr1 (31);                          \
0248   vsave_msr2 (33, 32*16+12);                        \
0249   vsave      (32, 32*16)
0250 #else
0251 #define EH_FRAME_VMX
0252 #endif
0253 
0254 .Lcie:
0255     .long .Lcie_end - .Lcie_start
0256 .Lcie_start:
0257     .long 0         /* CIE ID */
0258     .byte 1         /* Version number */
0259     .string "zRS"       /* NUL-terminated augmentation string */
0260     .uleb128 4      /* Code alignment factor */
0261     .sleb128 -4     /* Data alignment factor */
0262     .byte 67        /* Return address register column, ap */
0263     .uleb128 1      /* Augmentation value length */
0264     .byte 0x1b      /* DW_EH_PE_pcrel | DW_EH_PE_sdata4. */
0265     .byte 0x0c,1,0      /* DW_CFA_def_cfa: r1 ofs 0 */
0266     .balign 4
0267 .Lcie_end:
0268 
0269     .long .Lfde0_end - .Lfde0_start
0270 .Lfde0_start:
0271     .long .Lfde0_start - .Lcie  /* CIE pointer. */
0272     .long .Lsig_start - .       /* PC start, length */
0273     .long .Lsig_end - .Lsig_start
0274     .uleb128 0          /* Augmentation */
0275     EH_FRAME_GEN
0276     EH_FRAME_FP
0277     EH_FRAME_VMX
0278     .balign 4
0279 .Lfde0_end:
0280 
0281 /* We have a different stack layout for rt_sigreturn.  */
0282 #undef PTREGS
0283 #define PTREGS 64+16+128+20+28
0284 
0285     .long .Lfde1_end - .Lfde1_start
0286 .Lfde1_start:
0287     .long .Lfde1_start - .Lcie  /* CIE pointer. */
0288     .long .Lsigrt_start - .     /* PC start, length */
0289     .long .Lsigrt_end - .Lsigrt_start
0290     .uleb128 0          /* Augmentation */
0291     EH_FRAME_GEN
0292     EH_FRAME_FP
0293     EH_FRAME_VMX
0294     .balign 4
0295 .Lfde1_end:
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