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0008 #include <asm/processor.h>
0009 #include <asm/ppc_asm.h>
0010 #include <asm/vdso.h>
0011 #include <asm/vdso_datapage.h>
0012 #include <asm/asm-offsets.h>
0013 #include <asm/cache.h>
0014
0015 .text
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0025 V_FUNCTION_BEGIN(__kernel_sync_dicache)
0026 .cfi_startproc
0027 BEGIN_FTR_SECTION
0028 b 3f
0029 END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE)
0030 #ifdef CONFIG_PPC64
0031 mflr r12
0032 .cfi_register lr,r12
0033 get_datapage r10
0034 mtlr r12
0035 .cfi_restore lr
0036 #endif
0037
0038 #ifdef CONFIG_PPC64
0039 lwz r7,CFG_DCACHE_BLOCKSZ(r10)
0040 addi r5,r7,-1
0041 #else
0042 li r5, L1_CACHE_BYTES - 1
0043 #endif
0044 andc r6,r3,r5
0045 subf r8,r6,r4
0046 add r8,r8,r5
0047 #ifdef CONFIG_PPC64
0048 lwz r9,CFG_DCACHE_LOGBLOCKSZ(r10)
0049 PPC_SRL. r8,r8,r9
0050 #else
0051 srwi. r8, r8, L1_CACHE_SHIFT
0052 mr r7, r6
0053 #endif
0054 crclr cr0*4+so
0055 beqlr
0056 mtctr r8
0057 1: dcbst 0,r6
0058 #ifdef CONFIG_PPC64
0059 add r6,r6,r7
0060 #else
0061 addi r6, r6, L1_CACHE_BYTES
0062 #endif
0063 bdnz 1b
0064 sync
0065
0066
0067
0068 #ifdef CONFIG_PPC64
0069 lwz r7,CFG_ICACHE_BLOCKSZ(r10)
0070 addi r5,r7,-1
0071 andc r6,r3,r5
0072 subf r8,r6,r4
0073 add r8,r8,r5
0074 lwz r9,CFG_ICACHE_LOGBLOCKSZ(r10)
0075 PPC_SRL. r8,r8,r9
0076 crclr cr0*4+so
0077 beqlr
0078 #endif
0079 mtctr r8
0080 #ifdef CONFIG_PPC64
0081 2: icbi 0,r6
0082 add r6,r6,r7
0083 #else
0084 2: icbi 0, r7
0085 addi r7, r7, L1_CACHE_BYTES
0086 #endif
0087 bdnz 2b
0088 isync
0089 li r3,0
0090 blr
0091 3:
0092 crclr cr0*4+so
0093 sync
0094 icbi 0,r1
0095 isync
0096 li r3,0
0097 blr
0098 .cfi_endproc
0099 V_FUNCTION_END(__kernel_sync_dicache)