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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 #include <linux/device.h>
0003 #include <linux/cpu.h>
0004 #include <linux/smp.h>
0005 #include <linux/percpu.h>
0006 #include <linux/init.h>
0007 #include <linux/sched.h>
0008 #include <linux/export.h>
0009 #include <linux/nodemask.h>
0010 #include <linux/cpumask.h>
0011 #include <linux/notifier.h>
0012 #include <linux/of.h>
0013 
0014 #include <asm/current.h>
0015 #include <asm/processor.h>
0016 #include <asm/cputable.h>
0017 #include <asm/hvcall.h>
0018 #include <asm/machdep.h>
0019 #include <asm/smp.h>
0020 #include <asm/pmc.h>
0021 #include <asm/firmware.h>
0022 #include <asm/idle.h>
0023 #include <asm/svm.h>
0024 
0025 #include "cacheinfo.h"
0026 #include "setup.h"
0027 
0028 #ifdef CONFIG_PPC64
0029 #include <asm/paca.h>
0030 #include <asm/lppaca.h>
0031 #endif
0032 
0033 static DEFINE_PER_CPU(struct cpu, cpu_devices);
0034 
0035 #ifdef CONFIG_PPC64
0036 
0037 /*
0038  * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
0039  * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
0040  * 2014:
0041  *
0042  *  "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
0043  *  up the kernel code."
0044  *
0045  * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
0046  * code should be removed.
0047  */
0048 
0049 static ssize_t store_smt_snooze_delay(struct device *dev,
0050                       struct device_attribute *attr,
0051                       const char *buf,
0052                       size_t count)
0053 {
0054     pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
0055              current->comm, current->pid);
0056     return count;
0057 }
0058 
0059 static ssize_t show_smt_snooze_delay(struct device *dev,
0060                      struct device_attribute *attr,
0061                      char *buf)
0062 {
0063     pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
0064              current->comm, current->pid);
0065     return sprintf(buf, "100\n");
0066 }
0067 
0068 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
0069            store_smt_snooze_delay);
0070 
0071 static int __init setup_smt_snooze_delay(char *str)
0072 {
0073     if (!cpu_has_feature(CPU_FTR_SMT))
0074         return 1;
0075 
0076     pr_warn("smt-snooze-delay command line option has no effect\n");
0077     return 1;
0078 }
0079 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
0080 
0081 #endif /* CONFIG_PPC64 */
0082 
0083 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
0084 static void read_##NAME(void *val) \
0085 { \
0086     *(unsigned long *)val = mfspr(ADDRESS); \
0087 } \
0088 static void write_##NAME(void *val) \
0089 { \
0090     EXTRA; \
0091     mtspr(ADDRESS, *(unsigned long *)val);  \
0092 }
0093 
0094 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
0095 static ssize_t show_##NAME(struct device *dev, \
0096             struct device_attribute *attr, \
0097             char *buf) \
0098 { \
0099     struct cpu *cpu = container_of(dev, struct cpu, dev); \
0100     unsigned long val; \
0101     smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
0102     return sprintf(buf, "%lx\n", val); \
0103 } \
0104 static ssize_t __used \
0105     store_##NAME(struct device *dev, struct device_attribute *attr, \
0106             const char *buf, size_t count) \
0107 { \
0108     struct cpu *cpu = container_of(dev, struct cpu, dev); \
0109     unsigned long val; \
0110     int ret = sscanf(buf, "%lx", &val); \
0111     if (ret != 1) \
0112         return -EINVAL; \
0113     smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
0114     return count; \
0115 }
0116 
0117 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
0118     __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
0119     __SYSFS_SPRSETUP_SHOW_STORE(NAME)
0120 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
0121     __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
0122     __SYSFS_SPRSETUP_SHOW_STORE(NAME)
0123 
0124 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
0125     __SYSFS_SPRSETUP_SHOW_STORE(NAME)
0126 
0127 #ifdef CONFIG_PPC64
0128 
0129 /*
0130  * This is the system wide DSCR register default value. Any
0131  * change to this default value through the sysfs interface
0132  * will update all per cpu DSCR default values across the
0133  * system stored in their respective PACA structures.
0134  */
0135 static unsigned long dscr_default;
0136 
0137 /**
0138  * read_dscr() - Fetch the cpu specific DSCR default
0139  * @val:    Returned cpu specific DSCR default value
0140  *
0141  * This function returns the per cpu DSCR default value
0142  * for any cpu which is contained in it's PACA structure.
0143  */
0144 static void read_dscr(void *val)
0145 {
0146     *(unsigned long *)val = get_paca()->dscr_default;
0147 }
0148 
0149 
0150 /**
0151  * write_dscr() - Update the cpu specific DSCR default
0152  * @val:    New cpu specific DSCR default value to update
0153  *
0154  * This function updates the per cpu DSCR default value
0155  * for any cpu which is contained in it's PACA structure.
0156  */
0157 static void write_dscr(void *val)
0158 {
0159     get_paca()->dscr_default = *(unsigned long *)val;
0160     if (!current->thread.dscr_inherit) {
0161         current->thread.dscr = *(unsigned long *)val;
0162         mtspr(SPRN_DSCR, *(unsigned long *)val);
0163     }
0164 }
0165 
0166 SYSFS_SPRSETUP_SHOW_STORE(dscr);
0167 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
0168 
0169 static void add_write_permission_dev_attr(struct device_attribute *attr)
0170 {
0171     attr->attr.mode |= 0200;
0172 }
0173 
0174 /**
0175  * show_dscr_default() - Fetch the system wide DSCR default
0176  * @dev:    Device structure
0177  * @attr:   Device attribute structure
0178  * @buf:    Interface buffer
0179  *
0180  * This function returns the system wide DSCR default value.
0181  */
0182 static ssize_t show_dscr_default(struct device *dev,
0183         struct device_attribute *attr, char *buf)
0184 {
0185     return sprintf(buf, "%lx\n", dscr_default);
0186 }
0187 
0188 /**
0189  * store_dscr_default() - Update the system wide DSCR default
0190  * @dev:    Device structure
0191  * @attr:   Device attribute structure
0192  * @buf:    Interface buffer
0193  * @count:  Size of the update
0194  *
0195  * This function updates the system wide DSCR default value.
0196  */
0197 static ssize_t __used store_dscr_default(struct device *dev,
0198         struct device_attribute *attr, const char *buf,
0199         size_t count)
0200 {
0201     unsigned long val;
0202     int ret = 0;
0203 
0204     ret = sscanf(buf, "%lx", &val);
0205     if (ret != 1)
0206         return -EINVAL;
0207     dscr_default = val;
0208 
0209     on_each_cpu(write_dscr, &val, 1);
0210 
0211     return count;
0212 }
0213 
0214 static DEVICE_ATTR(dscr_default, 0600,
0215         show_dscr_default, store_dscr_default);
0216 
0217 static void __init sysfs_create_dscr_default(void)
0218 {
0219     if (cpu_has_feature(CPU_FTR_DSCR)) {
0220         int cpu;
0221 
0222         dscr_default = spr_default_dscr;
0223         for_each_possible_cpu(cpu)
0224             paca_ptrs[cpu]->dscr_default = dscr_default;
0225 
0226         device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
0227     }
0228 }
0229 #endif /* CONFIG_PPC64 */
0230 
0231 #ifdef CONFIG_PPC_FSL_BOOK3E
0232 #define MAX_BIT             63
0233 
0234 static u64 pw20_wt;
0235 static u64 altivec_idle_wt;
0236 
0237 static unsigned int get_idle_ticks_bit(u64 ns)
0238 {
0239     u64 cycle;
0240 
0241     if (ns >= 10000)
0242         cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
0243     else
0244         cycle = div_u64(ns * tb_ticks_per_usec, 1000);
0245 
0246     if (!cycle)
0247         return 0;
0248 
0249     return ilog2(cycle);
0250 }
0251 
0252 static void do_show_pwrmgtcr0(void *val)
0253 {
0254     u32 *value = val;
0255 
0256     *value = mfspr(SPRN_PWRMGTCR0);
0257 }
0258 
0259 static ssize_t show_pw20_state(struct device *dev,
0260                 struct device_attribute *attr, char *buf)
0261 {
0262     u32 value;
0263     unsigned int cpu = dev->id;
0264 
0265     smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
0266 
0267     value &= PWRMGTCR0_PW20_WAIT;
0268 
0269     return sprintf(buf, "%u\n", value ? 1 : 0);
0270 }
0271 
0272 static void do_store_pw20_state(void *val)
0273 {
0274     u32 *value = val;
0275     u32 pw20_state;
0276 
0277     pw20_state = mfspr(SPRN_PWRMGTCR0);
0278 
0279     if (*value)
0280         pw20_state |= PWRMGTCR0_PW20_WAIT;
0281     else
0282         pw20_state &= ~PWRMGTCR0_PW20_WAIT;
0283 
0284     mtspr(SPRN_PWRMGTCR0, pw20_state);
0285 }
0286 
0287 static ssize_t store_pw20_state(struct device *dev,
0288                 struct device_attribute *attr,
0289                 const char *buf, size_t count)
0290 {
0291     u32 value;
0292     unsigned int cpu = dev->id;
0293 
0294     if (kstrtou32(buf, 0, &value))
0295         return -EINVAL;
0296 
0297     if (value > 1)
0298         return -EINVAL;
0299 
0300     smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
0301 
0302     return count;
0303 }
0304 
0305 static ssize_t show_pw20_wait_time(struct device *dev,
0306                 struct device_attribute *attr, char *buf)
0307 {
0308     u32 value;
0309     u64 tb_cycle = 1;
0310     u64 time;
0311 
0312     unsigned int cpu = dev->id;
0313 
0314     if (!pw20_wt) {
0315         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
0316         value = (value & PWRMGTCR0_PW20_ENT) >>
0317                     PWRMGTCR0_PW20_ENT_SHIFT;
0318 
0319         tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
0320         /* convert ms to ns */
0321         if (tb_ticks_per_usec > 1000) {
0322             time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
0323         } else {
0324             u32 rem_us;
0325 
0326             time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
0327                         &rem_us);
0328             time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
0329         }
0330     } else {
0331         time = pw20_wt;
0332     }
0333 
0334     return sprintf(buf, "%llu\n", time > 0 ? time : 0);
0335 }
0336 
0337 static void set_pw20_wait_entry_bit(void *val)
0338 {
0339     u32 *value = val;
0340     u32 pw20_idle;
0341 
0342     pw20_idle = mfspr(SPRN_PWRMGTCR0);
0343 
0344     /* Set Automatic PW20 Core Idle Count */
0345     /* clear count */
0346     pw20_idle &= ~PWRMGTCR0_PW20_ENT;
0347 
0348     /* set count */
0349     pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
0350 
0351     mtspr(SPRN_PWRMGTCR0, pw20_idle);
0352 }
0353 
0354 static ssize_t store_pw20_wait_time(struct device *dev,
0355                 struct device_attribute *attr,
0356                 const char *buf, size_t count)
0357 {
0358     u32 entry_bit;
0359     u64 value;
0360 
0361     unsigned int cpu = dev->id;
0362 
0363     if (kstrtou64(buf, 0, &value))
0364         return -EINVAL;
0365 
0366     if (!value)
0367         return -EINVAL;
0368 
0369     entry_bit = get_idle_ticks_bit(value);
0370     if (entry_bit > MAX_BIT)
0371         return -EINVAL;
0372 
0373     pw20_wt = value;
0374 
0375     smp_call_function_single(cpu, set_pw20_wait_entry_bit,
0376                 &entry_bit, 1);
0377 
0378     return count;
0379 }
0380 
0381 static ssize_t show_altivec_idle(struct device *dev,
0382                 struct device_attribute *attr, char *buf)
0383 {
0384     u32 value;
0385     unsigned int cpu = dev->id;
0386 
0387     smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
0388 
0389     value &= PWRMGTCR0_AV_IDLE_PD_EN;
0390 
0391     return sprintf(buf, "%u\n", value ? 1 : 0);
0392 }
0393 
0394 static void do_store_altivec_idle(void *val)
0395 {
0396     u32 *value = val;
0397     u32 altivec_idle;
0398 
0399     altivec_idle = mfspr(SPRN_PWRMGTCR0);
0400 
0401     if (*value)
0402         altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
0403     else
0404         altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
0405 
0406     mtspr(SPRN_PWRMGTCR0, altivec_idle);
0407 }
0408 
0409 static ssize_t store_altivec_idle(struct device *dev,
0410                 struct device_attribute *attr,
0411                 const char *buf, size_t count)
0412 {
0413     u32 value;
0414     unsigned int cpu = dev->id;
0415 
0416     if (kstrtou32(buf, 0, &value))
0417         return -EINVAL;
0418 
0419     if (value > 1)
0420         return -EINVAL;
0421 
0422     smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
0423 
0424     return count;
0425 }
0426 
0427 static ssize_t show_altivec_idle_wait_time(struct device *dev,
0428                 struct device_attribute *attr, char *buf)
0429 {
0430     u32 value;
0431     u64 tb_cycle = 1;
0432     u64 time;
0433 
0434     unsigned int cpu = dev->id;
0435 
0436     if (!altivec_idle_wt) {
0437         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
0438         value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
0439                     PWRMGTCR0_AV_IDLE_CNT_SHIFT;
0440 
0441         tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
0442         /* convert ms to ns */
0443         if (tb_ticks_per_usec > 1000) {
0444             time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
0445         } else {
0446             u32 rem_us;
0447 
0448             time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
0449                         &rem_us);
0450             time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
0451         }
0452     } else {
0453         time = altivec_idle_wt;
0454     }
0455 
0456     return sprintf(buf, "%llu\n", time > 0 ? time : 0);
0457 }
0458 
0459 static void set_altivec_idle_wait_entry_bit(void *val)
0460 {
0461     u32 *value = val;
0462     u32 altivec_idle;
0463 
0464     altivec_idle = mfspr(SPRN_PWRMGTCR0);
0465 
0466     /* Set Automatic AltiVec Idle Count */
0467     /* clear count */
0468     altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
0469 
0470     /* set count */
0471     altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
0472 
0473     mtspr(SPRN_PWRMGTCR0, altivec_idle);
0474 }
0475 
0476 static ssize_t store_altivec_idle_wait_time(struct device *dev,
0477                 struct device_attribute *attr,
0478                 const char *buf, size_t count)
0479 {
0480     u32 entry_bit;
0481     u64 value;
0482 
0483     unsigned int cpu = dev->id;
0484 
0485     if (kstrtou64(buf, 0, &value))
0486         return -EINVAL;
0487 
0488     if (!value)
0489         return -EINVAL;
0490 
0491     entry_bit = get_idle_ticks_bit(value);
0492     if (entry_bit > MAX_BIT)
0493         return -EINVAL;
0494 
0495     altivec_idle_wt = value;
0496 
0497     smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
0498                 &entry_bit, 1);
0499 
0500     return count;
0501 }
0502 
0503 /*
0504  * Enable/Disable interface:
0505  * 0, disable. 1, enable.
0506  */
0507 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
0508 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
0509 
0510 /*
0511  * Set wait time interface:(Nanosecond)
0512  * Example: Base on TBfreq is 41MHZ.
0513  * 1~48(ns): TB[63]
0514  * 49~97(ns): TB[62]
0515  * 98~195(ns): TB[61]
0516  * 196~390(ns): TB[60]
0517  * 391~780(ns): TB[59]
0518  * 781~1560(ns): TB[58]
0519  * ...
0520  */
0521 static DEVICE_ATTR(pw20_wait_time, 0600,
0522             show_pw20_wait_time,
0523             store_pw20_wait_time);
0524 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
0525             show_altivec_idle_wait_time,
0526             store_altivec_idle_wait_time);
0527 #endif
0528 
0529 /*
0530  * Enabling PMCs will slow partition context switch times so we only do
0531  * it the first time we write to the PMCs.
0532  */
0533 
0534 static DEFINE_PER_CPU(char, pmcs_enabled);
0535 
0536 void ppc_enable_pmcs(void)
0537 {
0538     ppc_set_pmu_inuse(1);
0539 
0540     /* Only need to enable them once */
0541     if (__this_cpu_read(pmcs_enabled))
0542         return;
0543 
0544     __this_cpu_write(pmcs_enabled, 1);
0545 
0546     if (ppc_md.enable_pmcs)
0547         ppc_md.enable_pmcs();
0548 }
0549 EXPORT_SYMBOL(ppc_enable_pmcs);
0550 
0551 
0552 
0553 /* Let's define all possible registers, we'll only hook up the ones
0554  * that are implemented on the current processor
0555  */
0556 
0557 #ifdef CONFIG_PMU_SYSFS
0558 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
0559 #define HAS_PPC_PMC_CLASSIC 1
0560 #define HAS_PPC_PMC_IBM     1
0561 #endif
0562 
0563 #ifdef CONFIG_PPC64
0564 #define HAS_PPC_PMC_PA6T    1
0565 #define HAS_PPC_PMC56          1
0566 #endif
0567 
0568 #ifdef CONFIG_PPC_BOOK3S_32
0569 #define HAS_PPC_PMC_G4      1
0570 #endif
0571 #endif /* CONFIG_PMU_SYSFS */
0572 
0573 #if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC)
0574 #define HAS_PPC_PA6T
0575 #endif
0576 /*
0577  * SPRs which are not related to PMU.
0578  */
0579 #ifdef CONFIG_PPC64
0580 SYSFS_SPRSETUP(purr, SPRN_PURR);
0581 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
0582 SYSFS_SPRSETUP(pir, SPRN_PIR);
0583 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
0584 
0585 /*
0586   Lets only enable read for phyp resources and
0587   enable write when needed with a separate function.
0588   Lets be conservative and default to pseries.
0589 */
0590 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
0591 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
0592 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
0593 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
0594 #endif /* CONFIG_PPC64 */
0595 
0596 #ifdef HAS_PPC_PMC_CLASSIC
0597 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
0598 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
0599 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
0600 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
0601 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
0602 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
0603 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
0604 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
0605 #endif
0606 
0607 #ifdef HAS_PPC_PMC_G4
0608 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
0609 #endif
0610 
0611 #ifdef HAS_PPC_PMC56
0612 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
0613 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
0614 
0615 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
0616 SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3);
0617 
0618 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
0619 static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3);
0620 #endif /* HAS_PPC_PMC56 */
0621 
0622 
0623 
0624 
0625 #ifdef HAS_PPC_PMC_PA6T
0626 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
0627 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
0628 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
0629 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
0630 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
0631 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
0632 #endif
0633 
0634 #ifdef HAS_PPC_PA6T
0635 SYSFS_SPRSETUP(hid0, SPRN_HID0);
0636 SYSFS_SPRSETUP(hid1, SPRN_HID1);
0637 SYSFS_SPRSETUP(hid4, SPRN_HID4);
0638 SYSFS_SPRSETUP(hid5, SPRN_HID5);
0639 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
0640 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
0641 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
0642 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
0643 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
0644 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
0645 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
0646 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
0647 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
0648 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
0649 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
0650 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
0651 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
0652 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
0653 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
0654 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
0655 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
0656 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
0657 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
0658 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
0659 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
0660 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
0661 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
0662 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
0663 #endif /* HAS_PPC_PA6T */
0664 
0665 #ifdef HAS_PPC_PMC_IBM
0666 static struct device_attribute ibm_common_attrs[] = {
0667     __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
0668     __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
0669 };
0670 #endif /* HAS_PPC_PMC_IBM */
0671 
0672 #ifdef HAS_PPC_PMC_G4
0673 static struct device_attribute g4_common_attrs[] = {
0674     __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
0675     __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
0676     __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
0677 };
0678 #endif /* HAS_PPC_PMC_G4 */
0679 
0680 #ifdef HAS_PPC_PMC_CLASSIC
0681 static struct device_attribute classic_pmc_attrs[] = {
0682     __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
0683     __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
0684     __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
0685     __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
0686     __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
0687     __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
0688 #ifdef HAS_PPC_PMC56
0689     __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
0690     __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
0691 #endif
0692 };
0693 #endif
0694 
0695 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
0696 static struct device_attribute pa6t_attrs[] = {
0697 #ifdef HAS_PPC_PMC_PA6T
0698     __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
0699     __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
0700     __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
0701     __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
0702     __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
0703     __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
0704     __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
0705     __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
0706 #endif
0707 #ifdef HAS_PPC_PA6T
0708     __ATTR(hid0, 0600, show_hid0, store_hid0),
0709     __ATTR(hid1, 0600, show_hid1, store_hid1),
0710     __ATTR(hid4, 0600, show_hid4, store_hid4),
0711     __ATTR(hid5, 0600, show_hid5, store_hid5),
0712     __ATTR(ima0, 0600, show_ima0, store_ima0),
0713     __ATTR(ima1, 0600, show_ima1, store_ima1),
0714     __ATTR(ima2, 0600, show_ima2, store_ima2),
0715     __ATTR(ima3, 0600, show_ima3, store_ima3),
0716     __ATTR(ima4, 0600, show_ima4, store_ima4),
0717     __ATTR(ima5, 0600, show_ima5, store_ima5),
0718     __ATTR(ima6, 0600, show_ima6, store_ima6),
0719     __ATTR(ima7, 0600, show_ima7, store_ima7),
0720     __ATTR(ima8, 0600, show_ima8, store_ima8),
0721     __ATTR(ima9, 0600, show_ima9, store_ima9),
0722     __ATTR(imaat, 0600, show_imaat, store_imaat),
0723     __ATTR(btcr, 0600, show_btcr, store_btcr),
0724     __ATTR(pccr, 0600, show_pccr, store_pccr),
0725     __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
0726     __ATTR(der, 0600, show_der, store_der),
0727     __ATTR(mer, 0600, show_mer, store_mer),
0728     __ATTR(ber, 0600, show_ber, store_ber),
0729     __ATTR(ier, 0600, show_ier, store_ier),
0730     __ATTR(sier, 0600, show_sier, store_sier),
0731     __ATTR(siar, 0600, show_siar, store_siar),
0732     __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
0733     __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
0734     __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
0735     __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
0736 #endif /* HAS_PPC_PA6T */
0737 };
0738 #endif
0739 
0740 #ifdef CONFIG_PPC_SVM
0741 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf)
0742 {
0743     return sprintf(buf, "%u\n", is_secure_guest());
0744 }
0745 static DEVICE_ATTR(svm, 0444, show_svm, NULL);
0746 
0747 static void __init create_svm_file(void)
0748 {
0749     device_create_file(cpu_subsys.dev_root, &dev_attr_svm);
0750 }
0751 #else
0752 static void __init create_svm_file(void)
0753 {
0754 }
0755 #endif /* CONFIG_PPC_SVM */
0756 
0757 #ifdef CONFIG_PPC_PSERIES
0758 static void read_idle_purr(void *val)
0759 {
0760     u64 *ret = val;
0761 
0762     *ret = read_this_idle_purr();
0763 }
0764 
0765 static ssize_t idle_purr_show(struct device *dev,
0766                   struct device_attribute *attr, char *buf)
0767 {
0768     struct cpu *cpu = container_of(dev, struct cpu, dev);
0769     u64 val;
0770 
0771     smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1);
0772     return sprintf(buf, "%llx\n", val);
0773 }
0774 static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL);
0775 
0776 static void create_idle_purr_file(struct device *s)
0777 {
0778     if (firmware_has_feature(FW_FEATURE_LPAR))
0779         device_create_file(s, &dev_attr_idle_purr);
0780 }
0781 
0782 static void remove_idle_purr_file(struct device *s)
0783 {
0784     if (firmware_has_feature(FW_FEATURE_LPAR))
0785         device_remove_file(s, &dev_attr_idle_purr);
0786 }
0787 
0788 static void read_idle_spurr(void *val)
0789 {
0790     u64 *ret = val;
0791 
0792     *ret = read_this_idle_spurr();
0793 }
0794 
0795 static ssize_t idle_spurr_show(struct device *dev,
0796                    struct device_attribute *attr, char *buf)
0797 {
0798     struct cpu *cpu = container_of(dev, struct cpu, dev);
0799     u64 val;
0800 
0801     smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1);
0802     return sprintf(buf, "%llx\n", val);
0803 }
0804 static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL);
0805 
0806 static void create_idle_spurr_file(struct device *s)
0807 {
0808     if (firmware_has_feature(FW_FEATURE_LPAR))
0809         device_create_file(s, &dev_attr_idle_spurr);
0810 }
0811 
0812 static void remove_idle_spurr_file(struct device *s)
0813 {
0814     if (firmware_has_feature(FW_FEATURE_LPAR))
0815         device_remove_file(s, &dev_attr_idle_spurr);
0816 }
0817 
0818 #else /* CONFIG_PPC_PSERIES */
0819 #define create_idle_purr_file(s)
0820 #define remove_idle_purr_file(s)
0821 #define create_idle_spurr_file(s)
0822 #define remove_idle_spurr_file(s)
0823 #endif /* CONFIG_PPC_PSERIES */
0824 
0825 static int register_cpu_online(unsigned int cpu)
0826 {
0827     struct cpu *c = &per_cpu(cpu_devices, cpu);
0828     struct device *s = &c->dev;
0829     struct device_attribute *attrs, *pmc_attrs;
0830     int i, nattrs;
0831 
0832     /* For cpus present at boot a reference was already grabbed in register_cpu() */
0833     if (!s->of_node)
0834         s->of_node = of_get_cpu_node(cpu, NULL);
0835 
0836 #ifdef CONFIG_PPC64
0837     if (cpu_has_feature(CPU_FTR_SMT))
0838         device_create_file(s, &dev_attr_smt_snooze_delay);
0839 #endif
0840 
0841     /* PMC stuff */
0842     switch (cur_cpu_spec->pmc_type) {
0843 #ifdef HAS_PPC_PMC_IBM
0844     case PPC_PMC_IBM:
0845         attrs = ibm_common_attrs;
0846         nattrs = ARRAY_SIZE(ibm_common_attrs);
0847         pmc_attrs = classic_pmc_attrs;
0848         break;
0849 #endif /* HAS_PPC_PMC_IBM */
0850 #ifdef HAS_PPC_PMC_G4
0851     case PPC_PMC_G4:
0852         attrs = g4_common_attrs;
0853         nattrs = ARRAY_SIZE(g4_common_attrs);
0854         pmc_attrs = classic_pmc_attrs;
0855         break;
0856 #endif /* HAS_PPC_PMC_G4 */
0857 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
0858     case PPC_PMC_PA6T:
0859         /* PA Semi starts counting at PMC0 */
0860         attrs = pa6t_attrs;
0861         nattrs = ARRAY_SIZE(pa6t_attrs);
0862         pmc_attrs = NULL;
0863         break;
0864 #endif
0865     default:
0866         attrs = NULL;
0867         nattrs = 0;
0868         pmc_attrs = NULL;
0869     }
0870 
0871     for (i = 0; i < nattrs; i++)
0872         device_create_file(s, &attrs[i]);
0873 
0874     if (pmc_attrs)
0875         for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
0876             device_create_file(s, &pmc_attrs[i]);
0877 
0878 #ifdef CONFIG_PPC64
0879 #ifdef  CONFIG_PMU_SYSFS
0880     if (cpu_has_feature(CPU_FTR_MMCRA))
0881         device_create_file(s, &dev_attr_mmcra);
0882 
0883     if (cpu_has_feature(CPU_FTR_ARCH_31))
0884         device_create_file(s, &dev_attr_mmcr3);
0885 #endif /* CONFIG_PMU_SYSFS */
0886 
0887     if (cpu_has_feature(CPU_FTR_PURR)) {
0888         if (!firmware_has_feature(FW_FEATURE_LPAR))
0889             add_write_permission_dev_attr(&dev_attr_purr);
0890         device_create_file(s, &dev_attr_purr);
0891         create_idle_purr_file(s);
0892     }
0893 
0894     if (cpu_has_feature(CPU_FTR_SPURR)) {
0895         device_create_file(s, &dev_attr_spurr);
0896         create_idle_spurr_file(s);
0897     }
0898 
0899     if (cpu_has_feature(CPU_FTR_DSCR))
0900         device_create_file(s, &dev_attr_dscr);
0901 
0902     if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
0903         device_create_file(s, &dev_attr_pir);
0904 
0905     if (cpu_has_feature(CPU_FTR_ARCH_206) &&
0906         !firmware_has_feature(FW_FEATURE_LPAR))
0907         device_create_file(s, &dev_attr_tscr);
0908 #endif /* CONFIG_PPC64 */
0909 
0910 #ifdef CONFIG_PPC_FSL_BOOK3E
0911     if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
0912         device_create_file(s, &dev_attr_pw20_state);
0913         device_create_file(s, &dev_attr_pw20_wait_time);
0914 
0915         device_create_file(s, &dev_attr_altivec_idle);
0916         device_create_file(s, &dev_attr_altivec_idle_wait_time);
0917     }
0918 #endif
0919     cacheinfo_cpu_online(cpu);
0920     return 0;
0921 }
0922 
0923 #ifdef CONFIG_HOTPLUG_CPU
0924 static int unregister_cpu_online(unsigned int cpu)
0925 {
0926     struct cpu *c = &per_cpu(cpu_devices, cpu);
0927     struct device *s = &c->dev;
0928     struct device_attribute *attrs, *pmc_attrs;
0929     int i, nattrs;
0930 
0931     if (WARN_RATELIMIT(!c->hotpluggable, "cpu %d can't be offlined\n", cpu))
0932         return -EBUSY;
0933 
0934 #ifdef CONFIG_PPC64
0935     if (cpu_has_feature(CPU_FTR_SMT))
0936         device_remove_file(s, &dev_attr_smt_snooze_delay);
0937 #endif
0938 
0939     /* PMC stuff */
0940     switch (cur_cpu_spec->pmc_type) {
0941 #ifdef HAS_PPC_PMC_IBM
0942     case PPC_PMC_IBM:
0943         attrs = ibm_common_attrs;
0944         nattrs = ARRAY_SIZE(ibm_common_attrs);
0945         pmc_attrs = classic_pmc_attrs;
0946         break;
0947 #endif /* HAS_PPC_PMC_IBM */
0948 #ifdef HAS_PPC_PMC_G4
0949     case PPC_PMC_G4:
0950         attrs = g4_common_attrs;
0951         nattrs = ARRAY_SIZE(g4_common_attrs);
0952         pmc_attrs = classic_pmc_attrs;
0953         break;
0954 #endif /* HAS_PPC_PMC_G4 */
0955 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
0956     case PPC_PMC_PA6T:
0957         /* PA Semi starts counting at PMC0 */
0958         attrs = pa6t_attrs;
0959         nattrs = ARRAY_SIZE(pa6t_attrs);
0960         pmc_attrs = NULL;
0961         break;
0962 #endif
0963     default:
0964         attrs = NULL;
0965         nattrs = 0;
0966         pmc_attrs = NULL;
0967     }
0968 
0969     for (i = 0; i < nattrs; i++)
0970         device_remove_file(s, &attrs[i]);
0971 
0972     if (pmc_attrs)
0973         for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
0974             device_remove_file(s, &pmc_attrs[i]);
0975 
0976 #ifdef CONFIG_PPC64
0977 #ifdef CONFIG_PMU_SYSFS
0978     if (cpu_has_feature(CPU_FTR_MMCRA))
0979         device_remove_file(s, &dev_attr_mmcra);
0980 
0981     if (cpu_has_feature(CPU_FTR_ARCH_31))
0982         device_remove_file(s, &dev_attr_mmcr3);
0983 #endif /* CONFIG_PMU_SYSFS */
0984 
0985     if (cpu_has_feature(CPU_FTR_PURR)) {
0986         device_remove_file(s, &dev_attr_purr);
0987         remove_idle_purr_file(s);
0988     }
0989 
0990     if (cpu_has_feature(CPU_FTR_SPURR)) {
0991         device_remove_file(s, &dev_attr_spurr);
0992         remove_idle_spurr_file(s);
0993     }
0994 
0995     if (cpu_has_feature(CPU_FTR_DSCR))
0996         device_remove_file(s, &dev_attr_dscr);
0997 
0998     if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
0999         device_remove_file(s, &dev_attr_pir);
1000 
1001     if (cpu_has_feature(CPU_FTR_ARCH_206) &&
1002         !firmware_has_feature(FW_FEATURE_LPAR))
1003         device_remove_file(s, &dev_attr_tscr);
1004 #endif /* CONFIG_PPC64 */
1005 
1006 #ifdef CONFIG_PPC_FSL_BOOK3E
1007     if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
1008         device_remove_file(s, &dev_attr_pw20_state);
1009         device_remove_file(s, &dev_attr_pw20_wait_time);
1010 
1011         device_remove_file(s, &dev_attr_altivec_idle);
1012         device_remove_file(s, &dev_attr_altivec_idle_wait_time);
1013     }
1014 #endif
1015     cacheinfo_cpu_offline(cpu);
1016     of_node_put(s->of_node);
1017     s->of_node = NULL;
1018     return 0;
1019 }
1020 #else /* !CONFIG_HOTPLUG_CPU */
1021 #define unregister_cpu_online NULL
1022 #endif
1023 
1024 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
1025 ssize_t arch_cpu_probe(const char *buf, size_t count)
1026 {
1027     if (ppc_md.cpu_probe)
1028         return ppc_md.cpu_probe(buf, count);
1029 
1030     return -EINVAL;
1031 }
1032 
1033 ssize_t arch_cpu_release(const char *buf, size_t count)
1034 {
1035     if (ppc_md.cpu_release)
1036         return ppc_md.cpu_release(buf, count);
1037 
1038     return -EINVAL;
1039 }
1040 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
1041 
1042 static DEFINE_MUTEX(cpu_mutex);
1043 
1044 int cpu_add_dev_attr(struct device_attribute *attr)
1045 {
1046     int cpu;
1047 
1048     mutex_lock(&cpu_mutex);
1049 
1050     for_each_possible_cpu(cpu) {
1051         device_create_file(get_cpu_device(cpu), attr);
1052     }
1053 
1054     mutex_unlock(&cpu_mutex);
1055     return 0;
1056 }
1057 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
1058 
1059 int cpu_add_dev_attr_group(struct attribute_group *attrs)
1060 {
1061     int cpu;
1062     struct device *dev;
1063     int ret;
1064 
1065     mutex_lock(&cpu_mutex);
1066 
1067     for_each_possible_cpu(cpu) {
1068         dev = get_cpu_device(cpu);
1069         ret = sysfs_create_group(&dev->kobj, attrs);
1070         WARN_ON(ret != 0);
1071     }
1072 
1073     mutex_unlock(&cpu_mutex);
1074     return 0;
1075 }
1076 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
1077 
1078 
1079 void cpu_remove_dev_attr(struct device_attribute *attr)
1080 {
1081     int cpu;
1082 
1083     mutex_lock(&cpu_mutex);
1084 
1085     for_each_possible_cpu(cpu) {
1086         device_remove_file(get_cpu_device(cpu), attr);
1087     }
1088 
1089     mutex_unlock(&cpu_mutex);
1090 }
1091 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
1092 
1093 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
1094 {
1095     int cpu;
1096     struct device *dev;
1097 
1098     mutex_lock(&cpu_mutex);
1099 
1100     for_each_possible_cpu(cpu) {
1101         dev = get_cpu_device(cpu);
1102         sysfs_remove_group(&dev->kobj, attrs);
1103     }
1104 
1105     mutex_unlock(&cpu_mutex);
1106 }
1107 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
1108 
1109 
1110 /* NUMA stuff */
1111 
1112 #ifdef CONFIG_NUMA
1113 int sysfs_add_device_to_node(struct device *dev, int nid)
1114 {
1115     struct node *node = node_devices[nid];
1116     return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1117             kobject_name(&dev->kobj));
1118 }
1119 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1120 
1121 void sysfs_remove_device_from_node(struct device *dev, int nid)
1122 {
1123     struct node *node = node_devices[nid];
1124     sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1125 }
1126 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1127 #endif
1128 
1129 /* Only valid if CPU is present. */
1130 static ssize_t show_physical_id(struct device *dev,
1131                 struct device_attribute *attr, char *buf)
1132 {
1133     struct cpu *cpu = container_of(dev, struct cpu, dev);
1134 
1135     return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1136 }
1137 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1138 
1139 static int __init topology_init(void)
1140 {
1141     int cpu, r;
1142 
1143     for_each_possible_cpu(cpu) {
1144         struct cpu *c = &per_cpu(cpu_devices, cpu);
1145 
1146 #ifdef CONFIG_HOTPLUG_CPU
1147         /*
1148          * For now, we just see if the system supports making
1149          * the RTAS calls for CPU hotplug.  But, there may be a
1150          * more comprehensive way to do this for an individual
1151          * CPU.  For instance, the boot cpu might never be valid
1152          * for hotplugging.
1153          */
1154         if (smp_ops && smp_ops->cpu_offline_self)
1155             c->hotpluggable = 1;
1156 #endif
1157 
1158         if (cpu_online(cpu) || c->hotpluggable) {
1159             register_cpu(c, cpu);
1160 
1161             device_create_file(&c->dev, &dev_attr_physical_id);
1162         }
1163     }
1164     r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1165                   register_cpu_online, unregister_cpu_online);
1166     WARN_ON(r < 0);
1167 #ifdef CONFIG_PPC64
1168     sysfs_create_dscr_default();
1169 #endif /* CONFIG_PPC64 */
1170 
1171     create_svm_file();
1172 
1173     return 0;
1174 }
1175 subsys_initcall(topology_init);
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