powerpc/kernel/rtas_pci.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
0004  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
0005  *
0006  * RTAS specific routines for PCI.
0007  *
0008  * Based on code from pci.c, chrp_pci.c and pSeries_pci.c
0009  */
0010
0011 #include <linux/kernel.h>
0012 #include <linux/threads.h>
0013 #include <linux/pci.h>
0014 #include <linux/string.h>
0015 #include <linux/init.h>
0016 #include <linux/pgtable.h>
0017 #include <linux/of_address.h>
0018 #include <linux/of_fdt.h>
0019
0020 #include <asm/io.h>
0021 #include <asm/irq.h>
0022 #include <asm/machdep.h>
0023 #include <asm/pci-bridge.h>
0024 #include <asm/iommu.h>
0025 #include <asm/rtas.h>
0026 #include <asm/mpic.h>
0027 #include <asm/ppc-pci.h>
0028 #include <asm/eeh.h>
0029
0030 /* RTAS tokens */
0031 static int read_pci_config;
0032 static int write_pci_config;
0033 static int ibm_read_pci_config;
0034 static int ibm_write_pci_config;
0035
0036 static inline int config_access_valid(struct pci_dn *dn, int where)
0037 {
0038     if (where < 256)
0039         return 1;
0040     if (where < 4096 && dn->pci_ext_config_space)
0041         return 1;
0042
0043     return 0;
0044 }
0045
0046 int rtas_read_config(struct pci_dn *pdn, int where, int size, u32 *val)
0047 {
0048     int returnval = -1;
0049     unsigned long buid, addr;
0050     int ret;
0051
0052     if (!pdn)
0053         return PCIBIOS_DEVICE_NOT_FOUND;
0054     if (!config_access_valid(pdn, where))
0055         return PCIBIOS_BAD_REGISTER_NUMBER;
0056 #ifdef CONFIG_EEH
0057     if (pdn->edev && pdn->edev->pe &&
0058         (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
0059         return PCIBIOS_SET_FAILED;
0060 #endif
0061
0062     addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
0063     buid = pdn->phb->buid;
0064     if (buid) {
0065         ret = rtas_call(ibm_read_pci_config, 4, 2, &returnval,
0066                 addr, BUID_HI(buid), BUID_LO(buid), size);
0067     } else {
0068         ret = rtas_call(read_pci_config, 2, 2, &returnval, addr, size);
0069     }
0070     *val = returnval;
0071
0072     if (ret)
0073         return PCIBIOS_DEVICE_NOT_FOUND;
0074
0075     return PCIBIOS_SUCCESSFUL;
0076 }
0077
0078 static int rtas_pci_read_config(struct pci_bus *bus,
0079                 unsigned int devfn,
0080                 int where, int size, u32 *val)
0081 {
0082     struct pci_dn *pdn;
0083     int ret;
0084
0085     *val = 0xFFFFFFFF;
0086
0087     pdn = pci_get_pdn_by_devfn(bus, devfn);
0088
0089     /* Validity of pdn is checked in here */
0090     ret = rtas_read_config(pdn, where, size, val);
0091     if (*val == EEH_IO_ERROR_VALUE(size) &&
0092         eeh_dev_check_failure(pdn_to_eeh_dev(pdn)))
0093         return PCIBIOS_DEVICE_NOT_FOUND;
0094
0095     return ret;
0096 }
0097
0098 int rtas_write_config(struct pci_dn *pdn, int where, int size, u32 val)
0099 {
0100     unsigned long buid, addr;
0101     int ret;
0102
0103     if (!pdn)
0104         return PCIBIOS_DEVICE_NOT_FOUND;
0105     if (!config_access_valid(pdn, where))
0106         return PCIBIOS_BAD_REGISTER_NUMBER;
0107 #ifdef CONFIG_EEH
0108     if (pdn->edev && pdn->edev->pe &&
0109         (pdn->edev->pe->state & EEH_PE_CFG_BLOCKED))
0110         return PCIBIOS_SET_FAILED;
0111 #endif
0112
0113     addr = rtas_config_addr(pdn->busno, pdn->devfn, where);
0114     buid = pdn->phb->buid;
0115     if (buid) {
0116         ret = rtas_call(ibm_write_pci_config, 5, 1, NULL, addr,
0117             BUID_HI(buid), BUID_LO(buid), size, (ulong) val);
0118     } else {
0119         ret = rtas_call(write_pci_config, 3, 1, NULL, addr, size, (ulong)val);
0120     }
0121
0122     if (ret)
0123         return PCIBIOS_DEVICE_NOT_FOUND;
0124
0125     return PCIBIOS_SUCCESSFUL;
0126 }
0127
0128 static int rtas_pci_write_config(struct pci_bus *bus,
0129                  unsigned int devfn,
0130                  int where, int size, u32 val)
0131 {
0132     struct pci_dn *pdn;
0133
0134     pdn = pci_get_pdn_by_devfn(bus, devfn);
0135
0136     /* Validity of pdn is checked in here. */
0137     return rtas_write_config(pdn, where, size, val);
0138 }
0139
0140 static struct pci_ops rtas_pci_ops = {
0141     .read = rtas_pci_read_config,
0142     .write = rtas_pci_write_config,
0143 };
0144
0145 static int is_python(struct device_node *dev)
0146 {
0147     const char *model = of_get_property(dev, "model", NULL);
0148
0149     if (model && strstr(model, "Python"))
0150         return 1;
0151
0152     return 0;
0153 }
0154
0155 static void python_countermeasures(struct device_node *dev)
0156 {
0157     struct resource registers;
0158     void __iomem *chip_regs;
0159     volatile u32 val;
0160
0161     if (of_address_to_resource(dev, 0, &registers)) {
0162         printk(KERN_ERR "Can't get address for Python workarounds !\n");
0163         return;
0164     }
0165
0166     /* Python's register file is 1 MB in size. */
0167     chip_regs = ioremap(registers.start & ~(0xfffffUL), 0x100000);
0168
0169     /*
0170      * Firmware doesn't always clear this bit which is critical
0171      * for good performance - Anton
0172      */
0173
0174 #define PRG_CL_RESET_VALID 0x00010000
0175
0176     val = in_be32(chip_regs + 0xf6030);
0177     if (val & PRG_CL_RESET_VALID) {
0178         printk(KERN_INFO "Python workaround: ");
0179         val &= ~PRG_CL_RESET_VALID;
0180         out_be32(chip_regs + 0xf6030, val);
0181         /*
0182          * We must read it back for changes to
0183          * take effect
0184          */
0185         val = in_be32(chip_regs + 0xf6030);
0186         printk("reg0: %x\n", val);
0187     }
0188
0189     iounmap(chip_regs);
0190 }
0191
0192 void __init init_pci_config_tokens(void)
0193 {
0194     read_pci_config = rtas_token("read-pci-config");
0195     write_pci_config = rtas_token("write-pci-config");
0196     ibm_read_pci_config = rtas_token("ibm,read-pci-config");
0197     ibm_write_pci_config = rtas_token("ibm,write-pci-config");
0198 }
0199
0200 unsigned long get_phb_buid(struct device_node *phb)
0201 {
0202     struct resource r;
0203
0204     if (ibm_read_pci_config == -1)
0205         return 0;
0206     if (of_address_to_resource(phb, 0, &r))
0207         return 0;
0208     return r.start;
0209 }
0210
0211 static int phb_set_bus_ranges(struct device_node *dev,
0212                   struct pci_controller *phb)
0213 {
0214     const __be32 *bus_range;
0215     unsigned int len;
0216
0217     bus_range = of_get_property(dev, "bus-range", &len);
0218     if (bus_range == NULL || len < 2 * sizeof(int)) {
0219         return 1;
0220     }
0221
0222     phb->first_busno = be32_to_cpu(bus_range[0]);
0223     phb->last_busno  = be32_to_cpu(bus_range[1]);
0224
0225     return 0;
0226 }
0227
0228 int rtas_setup_phb(struct pci_controller *phb)
0229 {
0230     struct device_node *dev = phb->dn;
0231
0232     if (is_python(dev))
0233         python_countermeasures(dev);
0234
0235     if (phb_set_bus_ranges(dev, phb))
0236         return 1;
0237
0238     phb->ops = &rtas_pci_ops;
0239     phb->buid = get_phb_buid(dev);
0240
0241     return 0;
0242 }