powerpc/kernel/pci_of_scan.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Helper routines to scan the device tree for PCI devices and busses
0004  *
0005  * Migrated out of PowerPC architecture pci_64.c file by Grant Likely
0006  * <grant.likely@secretlab.ca> so that these routines are available for
0007  * 32 bit also.
0008  *
0009  * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
0010  *   Rework, based on alpha PCI code.
0011  * Copyright (c) 2009 Secret Lab Technologies Ltd.
0012  */
0013
0014 #include <linux/pci.h>
0015 #include <linux/export.h>
0016 #include <linux/of.h>
0017 #include <asm/pci-bridge.h>
0018
0019 /**
0020  * get_int_prop - Decode a u32 from a device tree property
0021  */
0022 static u32 get_int_prop(struct device_node *np, const char *name, u32 def)
0023 {
0024     const __be32 *prop;
0025     int len;
0026
0027     prop = of_get_property(np, name, &len);
0028     if (prop && len >= 4)
0029         return of_read_number(prop, 1);
0030     return def;
0031 }
0032
0033 /**
0034  * pci_parse_of_flags - Parse the flags cell of a device tree PCI address
0035  * @addr0: value of 1st cell of a device tree PCI address.
0036  * @bridge: Set this flag if the address is from a bridge 'ranges' property
0037  *
0038  * PCI Bus Binding to IEEE Std 1275-1994
0039  *
0040  * Bit#            33222222 22221111 11111100 00000000
0041  *                 10987654 32109876 54321098 76543210
0042  * phys.hi cell:   npt000ss bbbbbbbb dddddfff rrrrrrrr
0043  * phys.mid cell:  hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
0044  * phys.lo cell:   llllllll llllllll llllllll llllllll
0045  *
0046  * where:
0047  * n        is 0 if the address is relocatable, 1 otherwise
0048  * p        is 1 if the addressable region is "prefetchable", 0 otherwise
0049  * t        is 1 if the address is aliased (for non-relocatable I/O),
0050  *          below 1 MB (for Memory),or below 64 KB (for relocatable I/O).
0051  * ss       is the space code, denoting the address space:
0052  *              00 denotes Configuration Space
0053  *              01 denotes I/O Space
0054  *              10 denotes 32-bit-address Memory Space
0055  *              11 denotes 64-bit-address Memory Space
0056  * bbbbbbbb is the 8-bit Bus Number
0057  * ddddd    is the 5-bit Device Number
0058  * fff      is the 3-bit Function Number
0059  * rrrrrrrr is the 8-bit Register Number
0060  */
0061 #define OF_PCI_ADDR0_SPACE(ss)      (((ss)&3)<<24)
0062 #define OF_PCI_ADDR0_SPACE_CFG      OF_PCI_ADDR0_SPACE(0)
0063 #define OF_PCI_ADDR0_SPACE_IO       OF_PCI_ADDR0_SPACE(1)
0064 #define OF_PCI_ADDR0_SPACE_MMIO32   OF_PCI_ADDR0_SPACE(2)
0065 #define OF_PCI_ADDR0_SPACE_MMIO64   OF_PCI_ADDR0_SPACE(3)
0066 #define OF_PCI_ADDR0_SPACE_MASK     OF_PCI_ADDR0_SPACE(3)
0067 #define OF_PCI_ADDR0_RELOC      (1UL<<31)
0068 #define OF_PCI_ADDR0_PREFETCH       (1UL<<30)
0069 #define OF_PCI_ADDR0_ALIAS      (1UL<<29)
0070 #define OF_PCI_ADDR0_BUS        0x00FF0000UL
0071 #define OF_PCI_ADDR0_DEV        0x0000F800UL
0072 #define OF_PCI_ADDR0_FN         0x00000700UL
0073 #define OF_PCI_ADDR0_BARREG     0x000000FFUL
0074
0075 unsigned int pci_parse_of_flags(u32 addr0, int bridge)
0076 {
0077     unsigned int flags = 0, as = addr0 & OF_PCI_ADDR0_SPACE_MASK;
0078
0079     if (as == OF_PCI_ADDR0_SPACE_MMIO32 || as == OF_PCI_ADDR0_SPACE_MMIO64) {
0080         flags = IORESOURCE_MEM | PCI_BASE_ADDRESS_SPACE_MEMORY;
0081
0082         if (as == OF_PCI_ADDR0_SPACE_MMIO64)
0083             flags |= PCI_BASE_ADDRESS_MEM_TYPE_64 | IORESOURCE_MEM_64;
0084
0085         if (addr0 & OF_PCI_ADDR0_ALIAS)
0086             flags |= PCI_BASE_ADDRESS_MEM_TYPE_1M;
0087
0088         if (addr0 & OF_PCI_ADDR0_PREFETCH)
0089             flags |= IORESOURCE_PREFETCH |
0090                  PCI_BASE_ADDRESS_MEM_PREFETCH;
0091
0092         /* Note: We don't know whether the ROM has been left enabled
0093          * by the firmware or not. We mark it as disabled (ie, we do
0094          * not set the IORESOURCE_ROM_ENABLE flag) for now rather than
0095          * do a config space read, it will be force-enabled if needed
0096          */
0097         if (!bridge && (addr0 & OF_PCI_ADDR0_BARREG) == PCI_ROM_ADDRESS)
0098             flags |= IORESOURCE_READONLY;
0099
0100     } else if (as == OF_PCI_ADDR0_SPACE_IO)
0101         flags = IORESOURCE_IO | PCI_BASE_ADDRESS_SPACE_IO;
0102
0103     if (flags)
0104         flags |= IORESOURCE_SIZEALIGN;
0105
0106     return flags;
0107 }
0108
0109 /**
0110  * of_pci_parse_addrs - Parse PCI addresses assigned in the device tree node
0111  * @node: device tree node for the PCI device
0112  * @dev: pci_dev structure for the device
0113  *
0114  * This function parses the 'assigned-addresses' property of a PCI devices'
0115  * device tree node and writes them into the associated pci_dev structure.
0116  */
0117 static void of_pci_parse_addrs(struct device_node *node, struct pci_dev *dev)
0118 {
0119     u64 base, size;
0120     unsigned int flags;
0121     struct pci_bus_region region;
0122     struct resource *res;
0123     const __be32 *addrs;
0124     u32 i;
0125     int proplen;
0126     bool mark_unset = false;
0127
0128     addrs = of_get_property(node, "assigned-addresses", &proplen);
0129     if (!addrs || !proplen) {
0130         addrs = of_get_property(node, "reg", &proplen);
0131         if (!addrs || !proplen)
0132             return;
0133         mark_unset = true;
0134     }
0135
0136     pr_debug("    parse addresses (%d bytes) @ %p\n", proplen, addrs);
0137     for (; proplen >= 20; proplen -= 20, addrs += 5) {
0138         flags = pci_parse_of_flags(of_read_number(addrs, 1), 0);
0139         if (!flags)
0140             continue;
0141         base = of_read_number(&addrs[1], 2);
0142         size = of_read_number(&addrs[3], 2);
0143         if (!size)
0144             continue;
0145         i = of_read_number(addrs, 1) & 0xff;
0146         pr_debug("  base: %llx, size: %llx, i: %x\n",
0147              (unsigned long long)base,
0148              (unsigned long long)size, i);
0149
0150         if (PCI_BASE_ADDRESS_0 <= i && i <= PCI_BASE_ADDRESS_5) {
0151             res = &dev->resource[(i - PCI_BASE_ADDRESS_0) >> 2];
0152         } else if (i == dev->rom_base_reg) {
0153             res = &dev->resource[PCI_ROM_RESOURCE];
0154             flags |= IORESOURCE_READONLY;
0155         } else {
0156             printk(KERN_ERR "PCI: bad cfg reg num 0x%x\n", i);
0157             continue;
0158         }
0159         res->flags = flags;
0160         if (mark_unset)
0161             res->flags |= IORESOURCE_UNSET;
0162         res->name = pci_name(dev);
0163         region.start = base;
0164         region.end = base + size - 1;
0165         pcibios_bus_to_resource(dev->bus, res, &region);
0166     }
0167 }
0168
0169 /**
0170  * of_create_pci_dev - Given a device tree node on a pci bus, create a pci_dev
0171  * @node: device tree node pointer
0172  * @bus: bus the device is sitting on
0173  * @devfn: PCI function number, extracted from device tree by caller.
0174  */
0175 struct pci_dev *of_create_pci_dev(struct device_node *node,
0176                  struct pci_bus *bus, int devfn)
0177 {
0178     struct pci_dev *dev;
0179
0180     dev = pci_alloc_dev(bus);
0181     if (!dev)
0182         return NULL;
0183
0184     pr_debug("    create device, devfn: %x, type: %s\n", devfn,
0185          of_node_get_device_type(node));
0186
0187     dev->dev.of_node = of_node_get(node);
0188     dev->dev.parent = bus->bridge;
0189     dev->dev.bus = &pci_bus_type;
0190     dev->devfn = devfn;
0191     dev->multifunction = 0;     /* maybe a lie? */
0192     dev->needs_freset = 0;      /* pcie fundamental reset required */
0193     set_pcie_port_type(dev);
0194
0195     pci_dev_assign_slot(dev);
0196     dev->vendor = get_int_prop(node, "vendor-id", 0xffff);
0197     dev->device = get_int_prop(node, "device-id", 0xffff);
0198     dev->subsystem_vendor = get_int_prop(node, "subsystem-vendor-id", 0);
0199     dev->subsystem_device = get_int_prop(node, "subsystem-id", 0);
0200
0201     dev->cfg_size = pci_cfg_space_size(dev);
0202
0203     dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
0204         dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
0205     dev->class = get_int_prop(node, "class-code", 0);
0206     dev->revision = get_int_prop(node, "revision-id", 0);
0207
0208     pr_debug("    class: 0x%x\n", dev->class);
0209     pr_debug("    revision: 0x%x\n", dev->revision);
0210
0211     dev->current_state = PCI_UNKNOWN;   /* unknown power state */
0212     dev->error_state = pci_channel_io_normal;
0213     dev->dma_mask = 0xffffffff;
0214
0215     /* Early fixups, before probing the BARs */
0216     pci_fixup_device(pci_fixup_early, dev);
0217
0218     if (of_node_is_type(node, "pci") || of_node_is_type(node, "pciex")) {
0219         /* a PCI-PCI bridge */
0220         dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
0221         dev->rom_base_reg = PCI_ROM_ADDRESS1;
0222         set_pcie_hotplug_bridge(dev);
0223     } else if (of_node_is_type(node, "cardbus")) {
0224         dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
0225     } else {
0226         dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
0227         dev->rom_base_reg = PCI_ROM_ADDRESS;
0228         /* Maybe do a default OF mapping here */
0229         dev->irq = 0;
0230     }
0231
0232     of_pci_parse_addrs(node, dev);
0233
0234     pr_debug("    adding to system ...\n");
0235
0236     pci_device_add(dev, bus);
0237
0238     return dev;
0239 }
0240 EXPORT_SYMBOL(of_create_pci_dev);
0241
0242 /**
0243  * of_scan_pci_bridge - Set up a PCI bridge and scan for child nodes
0244  * @dev: pci_dev structure for the bridge
0245  *
0246  * of_scan_bus() calls this routine for each PCI bridge that it finds, and
0247  * this routine in turn call of_scan_bus() recursively to scan for more child
0248  * devices.
0249  */
0250 void of_scan_pci_bridge(struct pci_dev *dev)
0251 {
0252     struct device_node *node = dev->dev.of_node;
0253     struct pci_bus *bus;
0254     struct pci_controller *phb;
0255     const __be32 *busrange, *ranges;
0256     int len, i, mode;
0257     struct pci_bus_region region;
0258     struct resource *res;
0259     unsigned int flags;
0260     u64 size;
0261
0262     pr_debug("of_scan_pci_bridge(%pOF)\n", node);
0263
0264     /* parse bus-range property */
0265     busrange = of_get_property(node, "bus-range", &len);
0266     if (busrange == NULL || len != 8) {
0267         printk(KERN_DEBUG "Can't get bus-range for PCI-PCI bridge %pOF\n",
0268                node);
0269         return;
0270     }
0271     ranges = of_get_property(node, "ranges", &len);
0272     if (ranges == NULL) {
0273         printk(KERN_DEBUG "Can't get ranges for PCI-PCI bridge %pOF\n",
0274                node);
0275         return;
0276     }
0277
0278     bus = pci_find_bus(pci_domain_nr(dev->bus),
0279                of_read_number(busrange, 1));
0280     if (!bus) {
0281         bus = pci_add_new_bus(dev->bus, dev,
0282                       of_read_number(busrange, 1));
0283         if (!bus) {
0284             printk(KERN_ERR "Failed to create pci bus for %pOF\n",
0285                    node);
0286             return;
0287         }
0288     }
0289
0290     bus->primary = dev->bus->number;
0291     pci_bus_insert_busn_res(bus, of_read_number(busrange, 1),
0292                 of_read_number(busrange+1, 1));
0293     bus->bridge_ctl = 0;
0294
0295     /* parse ranges property */
0296     /* PCI #address-cells == 3 and #size-cells == 2 always */
0297     res = &dev->resource[PCI_BRIDGE_RESOURCES];
0298     for (i = 0; i < PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES; ++i) {
0299         res->flags = 0;
0300         bus->resource[i] = res;
0301         ++res;
0302     }
0303     i = 1;
0304     for (; len >= 32; len -= 32, ranges += 8) {
0305         flags = pci_parse_of_flags(of_read_number(ranges, 1), 1);
0306         size = of_read_number(&ranges[6], 2);
0307         if (flags == 0 || size == 0)
0308             continue;
0309         if (flags & IORESOURCE_IO) {
0310             res = bus->resource[0];
0311             if (res->flags) {
0312                 printk(KERN_ERR "PCI: ignoring extra I/O range"
0313                        " for bridge %pOF\n", node);
0314                 continue;
0315             }
0316         } else {
0317             if (i >= PCI_NUM_RESOURCES - PCI_BRIDGE_RESOURCES) {
0318                 printk(KERN_ERR "PCI: too many memory ranges"
0319                        " for bridge %pOF\n", node);
0320                 continue;
0321             }
0322             res = bus->resource[i];
0323             ++i;
0324         }
0325         res->flags = flags;
0326         region.start = of_read_number(&ranges[1], 2);
0327         region.end = region.start + size - 1;
0328         pcibios_bus_to_resource(dev->bus, res, &region);
0329     }
0330     sprintf(bus->name, "PCI Bus %04x:%02x", pci_domain_nr(bus),
0331         bus->number);
0332     pr_debug("    bus name: %s\n", bus->name);
0333
0334     phb = pci_bus_to_host(bus);
0335
0336     mode = PCI_PROBE_NORMAL;
0337     if (phb->controller_ops.probe_mode)
0338         mode = phb->controller_ops.probe_mode(bus);
0339     pr_debug("    probe mode: %d\n", mode);
0340
0341     if (mode == PCI_PROBE_DEVTREE)
0342         of_scan_bus(node, bus);
0343     else if (mode == PCI_PROBE_NORMAL)
0344         pci_scan_child_bus(bus);
0345 }
0346 EXPORT_SYMBOL(of_scan_pci_bridge);
0347
0348 static struct pci_dev *of_scan_pci_dev(struct pci_bus *bus,
0349                 struct device_node *dn)
0350 {
0351     struct pci_dev *dev = NULL;
0352     const __be32 *reg;
0353     int reglen, devfn;
0354 #ifdef CONFIG_EEH
0355     struct eeh_dev *edev = pdn_to_eeh_dev(PCI_DN(dn));
0356 #endif
0357
0358     pr_debug("  * %pOF\n", dn);
0359     if (!of_device_is_available(dn))
0360         return NULL;
0361
0362     reg = of_get_property(dn, "reg", &reglen);
0363     if (reg == NULL || reglen < 20)
0364         return NULL;
0365     devfn = (of_read_number(reg, 1) >> 8) & 0xff;
0366
0367     /* Check if the PCI device is already there */
0368     dev = pci_get_slot(bus, devfn);
0369     if (dev) {
0370         pci_dev_put(dev);
0371         return dev;
0372     }
0373
0374     /* Device removed permanently ? */
0375 #ifdef CONFIG_EEH
0376     if (edev && (edev->mode & EEH_DEV_REMOVED))
0377         return NULL;
0378 #endif
0379
0380     /* create a new pci_dev for this device */
0381     dev = of_create_pci_dev(dn, bus, devfn);
0382     if (!dev)
0383         return NULL;
0384
0385     pr_debug("  dev header type: %x\n", dev->hdr_type);
0386     return dev;
0387 }
0388
0389 /**
0390  * __of_scan_bus - given a PCI bus node, setup bus and scan for child devices
0391  * @node: device tree node for the PCI bus
0392  * @bus: pci_bus structure for the PCI bus
0393  * @rescan_existing: Flag indicating bus has already been set up
0394  */
0395 static void __of_scan_bus(struct device_node *node, struct pci_bus *bus,
0396               int rescan_existing)
0397 {
0398     struct device_node *child;
0399     struct pci_dev *dev;
0400
0401     pr_debug("of_scan_bus(%pOF) bus no %d...\n",
0402          node, bus->number);
0403
0404     /* Scan direct children */
0405     for_each_child_of_node(node, child) {
0406         dev = of_scan_pci_dev(bus, child);
0407         if (!dev)
0408             continue;
0409         pr_debug("    dev header type: %x\n", dev->hdr_type);
0410     }
0411
0412     /* Apply all fixups necessary. We don't fixup the bus "self"
0413      * for an existing bridge that is being rescanned
0414      */
0415     if (!rescan_existing)
0416         pcibios_setup_bus_self(bus);
0417
0418     /* Now scan child busses */
0419     for_each_pci_bridge(dev, bus)
0420         of_scan_pci_bridge(dev);
0421 }
0422
0423 /**
0424  * of_scan_bus - given a PCI bus node, setup bus and scan for child devices
0425  * @node: device tree node for the PCI bus
0426  * @bus: pci_bus structure for the PCI bus
0427  */
0428 void of_scan_bus(struct device_node *node, struct pci_bus *bus)
0429 {
0430     __of_scan_bus(node, bus, 0);
0431 }
0432 EXPORT_SYMBOL_GPL(of_scan_bus);
0433
0434 /**
0435  * of_rescan_bus - given a PCI bus node, scan for child devices
0436  * @node: device tree node for the PCI bus
0437  * @bus: pci_bus structure for the PCI bus
0438  *
0439  * Same as of_scan_bus, but for a pci_bus structure that has already been
0440  * setup.
0441  */
0442 void of_rescan_bus(struct device_node *node, struct pci_bus *bus)
0443 {
0444     __of_scan_bus(node, bus, 1);
0445 }
0446 EXPORT_SYMBOL_GPL(of_rescan_bus);
0447