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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Derived from arch/i386/kernel/irq.c
0004  *    Copyright (C) 1992 Linus Torvalds
0005  *  Adapted from arch/i386 by Gary Thomas
0006  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
0007  *  Updated and modified by Cort Dougan <cort@fsmlabs.com>
0008  *    Copyright (C) 1996-2001 Cort Dougan
0009  *  Adapted for Power Macintosh by Paul Mackerras
0010  *    Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
0011  *
0012  * This file contains the code used by various IRQ handling routines:
0013  * asking for different IRQ's should be done through these routines
0014  * instead of just grabbing them. Thus setups with different IRQ numbers
0015  * shouldn't result in any weird surprises, and installing new handlers
0016  * should be easier.
0017  *
0018  * The MPC8xx has an interrupt mask in the SIU.  If a bit is set, the
0019  * interrupt is _enabled_.  As expected, IRQ0 is bit 0 in the 32-bit
0020  * mask register (of which only 16 are defined), hence the weird shifting
0021  * and complement of the cached_irq_mask.  I want to be able to stuff
0022  * this right into the SIU SMASK register.
0023  * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx
0024  * to reduce code space and undefined function references.
0025  */
0026 
0027 #undef DEBUG
0028 
0029 #include <linux/export.h>
0030 #include <linux/threads.h>
0031 #include <linux/kernel_stat.h>
0032 #include <linux/signal.h>
0033 #include <linux/sched.h>
0034 #include <linux/ptrace.h>
0035 #include <linux/ioport.h>
0036 #include <linux/interrupt.h>
0037 #include <linux/timex.h>
0038 #include <linux/init.h>
0039 #include <linux/slab.h>
0040 #include <linux/delay.h>
0041 #include <linux/irq.h>
0042 #include <linux/seq_file.h>
0043 #include <linux/cpumask.h>
0044 #include <linux/profile.h>
0045 #include <linux/bitops.h>
0046 #include <linux/list.h>
0047 #include <linux/radix-tree.h>
0048 #include <linux/mutex.h>
0049 #include <linux/pci.h>
0050 #include <linux/debugfs.h>
0051 #include <linux/of.h>
0052 #include <linux/of_irq.h>
0053 #include <linux/vmalloc.h>
0054 #include <linux/pgtable.h>
0055 #include <linux/static_call.h>
0056 
0057 #include <linux/uaccess.h>
0058 #include <asm/interrupt.h>
0059 #include <asm/io.h>
0060 #include <asm/irq.h>
0061 #include <asm/cache.h>
0062 #include <asm/ptrace.h>
0063 #include <asm/machdep.h>
0064 #include <asm/udbg.h>
0065 #include <asm/smp.h>
0066 #include <asm/hw_irq.h>
0067 #include <asm/softirq_stack.h>
0068 #include <asm/ppc_asm.h>
0069 
0070 #define CREATE_TRACE_POINTS
0071 #include <asm/trace.h>
0072 #include <asm/cpu_has_feature.h>
0073 
0074 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
0075 EXPORT_PER_CPU_SYMBOL(irq_stat);
0076 
0077 #ifdef CONFIG_PPC32
0078 atomic_t ppc_n_lost_interrupts;
0079 
0080 #ifdef CONFIG_TAU_INT
0081 extern int tau_initialized;
0082 u32 tau_interrupts(unsigned long cpu);
0083 #endif
0084 #endif /* CONFIG_PPC32 */
0085 
0086 int arch_show_interrupts(struct seq_file *p, int prec)
0087 {
0088     int j;
0089 
0090 #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
0091     if (tau_initialized) {
0092         seq_printf(p, "%*s: ", prec, "TAU");
0093         for_each_online_cpu(j)
0094             seq_printf(p, "%10u ", tau_interrupts(j));
0095         seq_puts(p, "  PowerPC             Thermal Assist (cpu temp)\n");
0096     }
0097 #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
0098 
0099     seq_printf(p, "%*s: ", prec, "LOC");
0100     for_each_online_cpu(j)
0101         seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event);
0102         seq_printf(p, "  Local timer interrupts for timer event device\n");
0103 
0104     seq_printf(p, "%*s: ", prec, "BCT");
0105     for_each_online_cpu(j)
0106         seq_printf(p, "%10u ", per_cpu(irq_stat, j).broadcast_irqs_event);
0107     seq_printf(p, "  Broadcast timer interrupts for timer event device\n");
0108 
0109     seq_printf(p, "%*s: ", prec, "LOC");
0110     for_each_online_cpu(j)
0111         seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others);
0112         seq_printf(p, "  Local timer interrupts for others\n");
0113 
0114     seq_printf(p, "%*s: ", prec, "SPU");
0115     for_each_online_cpu(j)
0116         seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs);
0117     seq_printf(p, "  Spurious interrupts\n");
0118 
0119     seq_printf(p, "%*s: ", prec, "PMI");
0120     for_each_online_cpu(j)
0121         seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs);
0122     seq_printf(p, "  Performance monitoring interrupts\n");
0123 
0124     seq_printf(p, "%*s: ", prec, "MCE");
0125     for_each_online_cpu(j)
0126         seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
0127     seq_printf(p, "  Machine check exceptions\n");
0128 
0129 #ifdef CONFIG_PPC_BOOK3S_64
0130     if (cpu_has_feature(CPU_FTR_HVMODE)) {
0131         seq_printf(p, "%*s: ", prec, "HMI");
0132         for_each_online_cpu(j)
0133             seq_printf(p, "%10u ", paca_ptrs[j]->hmi_irqs);
0134         seq_printf(p, "  Hypervisor Maintenance Interrupts\n");
0135     }
0136 #endif
0137 
0138     seq_printf(p, "%*s: ", prec, "NMI");
0139     for_each_online_cpu(j)
0140         seq_printf(p, "%10u ", per_cpu(irq_stat, j).sreset_irqs);
0141     seq_printf(p, "  System Reset interrupts\n");
0142 
0143 #ifdef CONFIG_PPC_WATCHDOG
0144     seq_printf(p, "%*s: ", prec, "WDG");
0145     for_each_online_cpu(j)
0146         seq_printf(p, "%10u ", per_cpu(irq_stat, j).soft_nmi_irqs);
0147     seq_printf(p, "  Watchdog soft-NMI interrupts\n");
0148 #endif
0149 
0150 #ifdef CONFIG_PPC_DOORBELL
0151     if (cpu_has_feature(CPU_FTR_DBELL)) {
0152         seq_printf(p, "%*s: ", prec, "DBL");
0153         for_each_online_cpu(j)
0154             seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
0155         seq_printf(p, "  Doorbell interrupts\n");
0156     }
0157 #endif
0158 
0159     return 0;
0160 }
0161 
0162 /*
0163  * /proc/stat helpers
0164  */
0165 u64 arch_irq_stat_cpu(unsigned int cpu)
0166 {
0167     u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
0168 
0169     sum += per_cpu(irq_stat, cpu).broadcast_irqs_event;
0170     sum += per_cpu(irq_stat, cpu).pmu_irqs;
0171     sum += per_cpu(irq_stat, cpu).mce_exceptions;
0172     sum += per_cpu(irq_stat, cpu).spurious_irqs;
0173     sum += per_cpu(irq_stat, cpu).timer_irqs_others;
0174 #ifdef CONFIG_PPC_BOOK3S_64
0175     sum += paca_ptrs[cpu]->hmi_irqs;
0176 #endif
0177     sum += per_cpu(irq_stat, cpu).sreset_irqs;
0178 #ifdef CONFIG_PPC_WATCHDOG
0179     sum += per_cpu(irq_stat, cpu).soft_nmi_irqs;
0180 #endif
0181 #ifdef CONFIG_PPC_DOORBELL
0182     sum += per_cpu(irq_stat, cpu).doorbell_irqs;
0183 #endif
0184 
0185     return sum;
0186 }
0187 
0188 static inline void check_stack_overflow(unsigned long sp)
0189 {
0190     if (!IS_ENABLED(CONFIG_DEBUG_STACKOVERFLOW))
0191         return;
0192 
0193     sp &= THREAD_SIZE - 1;
0194 
0195     /* check for stack overflow: is there less than 1/4th free? */
0196     if (unlikely(sp < THREAD_SIZE / 4)) {
0197         pr_err("do_IRQ: stack overflow: %ld\n", sp);
0198         dump_stack();
0199     }
0200 }
0201 
0202 #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
0203 static __always_inline void call_do_softirq(const void *sp)
0204 {
0205     /* Temporarily switch r1 to sp, call __do_softirq() then restore r1. */
0206     asm volatile (
0207          PPC_STLU " %%r1, %[offset](%[sp])  ;"
0208         "mr     %%r1, %[sp]     ;"
0209         "bl     %[callee]       ;"
0210          PPC_LL "   %%r1, 0(%%r1)       ;"
0211          : // Outputs
0212          : // Inputs
0213            [sp] "b" (sp), [offset] "i" (THREAD_SIZE - STACK_FRAME_OVERHEAD),
0214            [callee] "i" (__do_softirq)
0215          : // Clobbers
0216            "lr", "xer", "ctr", "memory", "cr0", "cr1", "cr5", "cr6",
0217            "cr7", "r0", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
0218            "r11", "r12"
0219     );
0220 }
0221 #endif
0222 
0223 DEFINE_STATIC_CALL_RET0(ppc_get_irq, *ppc_md.get_irq);
0224 
0225 static void __do_irq(struct pt_regs *regs, unsigned long oldsp)
0226 {
0227     unsigned int irq;
0228 
0229     trace_irq_entry(regs);
0230 
0231     check_stack_overflow(oldsp);
0232 
0233     /*
0234      * Query the platform PIC for the interrupt & ack it.
0235      *
0236      * This will typically lower the interrupt line to the CPU
0237      */
0238     irq = static_call(ppc_get_irq)();
0239 
0240     /* We can hard enable interrupts now to allow perf interrupts */
0241     if (should_hard_irq_enable())
0242         do_hard_irq_enable();
0243 
0244     /* And finally process it */
0245     if (unlikely(!irq))
0246         __this_cpu_inc(irq_stat.spurious_irqs);
0247     else
0248         generic_handle_irq(irq);
0249 
0250     trace_irq_exit(regs);
0251 }
0252 
0253 static __always_inline void call_do_irq(struct pt_regs *regs, void *sp)
0254 {
0255     register unsigned long r3 asm("r3") = (unsigned long)regs;
0256 
0257     /* Temporarily switch r1 to sp, call __do_irq() then restore r1. */
0258     asm volatile (
0259          PPC_STLU " %%r1, %[offset](%[sp])  ;"
0260         "mr     %%r4, %%r1      ;"
0261         "mr     %%r1, %[sp]     ;"
0262         "bl     %[callee]       ;"
0263          PPC_LL "   %%r1, 0(%%r1)       ;"
0264          : // Outputs
0265            "+r" (r3)
0266          : // Inputs
0267            [sp] "b" (sp), [offset] "i" (THREAD_SIZE - STACK_FRAME_OVERHEAD),
0268            [callee] "i" (__do_irq)
0269          : // Clobbers
0270            "lr", "xer", "ctr", "memory", "cr0", "cr1", "cr5", "cr6",
0271            "cr7", "r0", "r4", "r5", "r6", "r7", "r8", "r9", "r10",
0272            "r11", "r12"
0273     );
0274 }
0275 
0276 void __do_IRQ(struct pt_regs *regs)
0277 {
0278     struct pt_regs *old_regs = set_irq_regs(regs);
0279     void *cursp, *irqsp, *sirqsp;
0280 
0281     /* Switch to the irq stack to handle this */
0282     cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
0283     irqsp = hardirq_ctx[raw_smp_processor_id()];
0284     sirqsp = softirq_ctx[raw_smp_processor_id()];
0285 
0286     /* Already there ? If not switch stack and call */
0287     if (unlikely(cursp == irqsp || cursp == sirqsp))
0288         __do_irq(regs, current_stack_pointer);
0289     else
0290         call_do_irq(regs, irqsp);
0291 
0292     set_irq_regs(old_regs);
0293 }
0294 
0295 DEFINE_INTERRUPT_HANDLER_ASYNC(do_IRQ)
0296 {
0297     __do_IRQ(regs);
0298 }
0299 
0300 static void *__init alloc_vm_stack(void)
0301 {
0302     return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP,
0303                   NUMA_NO_NODE, (void *)_RET_IP_);
0304 }
0305 
0306 static void __init vmap_irqstack_init(void)
0307 {
0308     int i;
0309 
0310     for_each_possible_cpu(i) {
0311         softirq_ctx[i] = alloc_vm_stack();
0312         hardirq_ctx[i] = alloc_vm_stack();
0313     }
0314 }
0315 
0316 
0317 void __init init_IRQ(void)
0318 {
0319     if (IS_ENABLED(CONFIG_VMAP_STACK))
0320         vmap_irqstack_init();
0321 
0322     if (ppc_md.init_IRQ)
0323         ppc_md.init_IRQ();
0324 
0325     if (!WARN_ON(!ppc_md.get_irq))
0326         static_call_update(ppc_get_irq, ppc_md.get_irq);
0327 }
0328 
0329 #ifdef CONFIG_BOOKE_OR_40x
0330 void   *critirq_ctx[NR_CPUS] __read_mostly;
0331 void    *dbgirq_ctx[NR_CPUS] __read_mostly;
0332 void *mcheckirq_ctx[NR_CPUS] __read_mostly;
0333 #endif
0334 
0335 void *softirq_ctx[NR_CPUS] __read_mostly;
0336 void *hardirq_ctx[NR_CPUS] __read_mostly;
0337 
0338 #ifdef CONFIG_SOFTIRQ_ON_OWN_STACK
0339 void do_softirq_own_stack(void)
0340 {
0341     call_do_softirq(softirq_ctx[smp_processor_id()]);
0342 }
0343 #endif
0344 
0345 irq_hw_number_t virq_to_hw(unsigned int virq)
0346 {
0347     struct irq_data *irq_data = irq_get_irq_data(virq);
0348     return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
0349 }
0350 EXPORT_SYMBOL_GPL(virq_to_hw);
0351 
0352 #ifdef CONFIG_SMP
0353 int irq_choose_cpu(const struct cpumask *mask)
0354 {
0355     int cpuid;
0356 
0357     if (cpumask_equal(mask, cpu_online_mask)) {
0358         static int irq_rover;
0359         static DEFINE_RAW_SPINLOCK(irq_rover_lock);
0360         unsigned long flags;
0361 
0362         /* Round-robin distribution... */
0363 do_round_robin:
0364         raw_spin_lock_irqsave(&irq_rover_lock, flags);
0365 
0366         irq_rover = cpumask_next(irq_rover, cpu_online_mask);
0367         if (irq_rover >= nr_cpu_ids)
0368             irq_rover = cpumask_first(cpu_online_mask);
0369 
0370         cpuid = irq_rover;
0371 
0372         raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
0373     } else {
0374         cpuid = cpumask_first_and(mask, cpu_online_mask);
0375         if (cpuid >= nr_cpu_ids)
0376             goto do_round_robin;
0377     }
0378 
0379     return get_hard_smp_processor_id(cpuid);
0380 }
0381 #else
0382 int irq_choose_cpu(const struct cpumask *mask)
0383 {
0384     return hard_smp_processor_id();
0385 }
0386 #endif
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