powerpc/kernel/idle_6xx.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  This file contains the power_save function for 6xx & 7xxx CPUs
0004  *  rewritten in assembler
0005  *
0006  *  Warning ! This code assumes that if your machine has a 750fx
0007  *  it will have PLL 1 set to low speed mode (used during NAP/DOZE).
0008  *  if this is not the case some additional changes will have to
0009  *  be done to check a runtime var (a bit like powersave-nap)
0010  */
0011
0012 #include <linux/threads.h>
0013 #include <asm/reg.h>
0014 #include <asm/page.h>
0015 #include <asm/cputable.h>
0016 #include <asm/thread_info.h>
0017 #include <asm/ppc_asm.h>
0018 #include <asm/asm-offsets.h>
0019 #include <asm/feature-fixups.h>
0020
0021     .text
0022
0023 /*
0024  * Init idle, called at early CPU setup time from head.S for each CPU
0025  * Make sure no rest of NAP mode remains in HID0, save default
0026  * values for some CPU specific registers. Called with r24
0027  * containing CPU number and r3 reloc offset
0028  */
0029 _GLOBAL(init_idle_6xx)
0030 BEGIN_FTR_SECTION
0031     mfspr   r4,SPRN_HID0
0032     rlwinm  r4,r4,0,10,8    /* Clear NAP */
0033     mtspr   SPRN_HID0, r4
0034     b   1f
0035 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
0036     blr
0037 1:
0038     slwi    r5,r24,2
0039     add r5,r5,r3
0040 BEGIN_FTR_SECTION
0041     mfspr   r4,SPRN_MSSCR0
0042     addis   r6,r5, nap_save_msscr0@ha
0043     stw r4,nap_save_msscr0@l(r6)
0044 END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
0045 BEGIN_FTR_SECTION
0046     mfspr   r4,SPRN_HID1
0047     addis   r6,r5,nap_save_hid1@ha
0048     stw r4,nap_save_hid1@l(r6)
0049 END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
0050     blr
0051
0052 /*
0053  * Here is the power_save_6xx function. This could eventually be
0054  * split into several functions & changing the function pointer
0055  * depending on the various features.
0056  */
0057 _GLOBAL(ppc6xx_idle)
0058     /* Check if we can nap or doze, put HID0 mask in r3
0059      */
0060     lis r3, 0
0061 BEGIN_FTR_SECTION
0062     lis r3,HID0_DOZE@h
0063 END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
0064 BEGIN_FTR_SECTION
0065     /* We must dynamically check for the NAP feature as it
0066      * can be cleared by CPU init after the fixups are done
0067      */
0068     lis r4,cur_cpu_spec@ha
0069     lwz r4,cur_cpu_spec@l(r4)
0070     lwz r4,CPU_SPEC_FEATURES(r4)
0071     andi.   r0,r4,CPU_FTR_CAN_NAP
0072     beq 1f
0073     /* Now check if user or arch enabled NAP mode */
0074     lis r4,powersave_nap@ha
0075     lwz r4,powersave_nap@l(r4)
0076     cmpwi   0,r4,0
0077     beq 1f
0078     lis r3,HID0_NAP@h
0079 1:
0080 END_FTR_SECTION_IFSET(CPU_FTR_CAN_NAP)
0081     cmpwi   0,r3,0
0082     beqlr
0083
0084     /* Some pre-nap cleanups needed on some CPUs */
0085     andis.  r0,r3,HID0_NAP@h
0086     beq 2f
0087 BEGIN_FTR_SECTION
0088     /* Disable L2 prefetch on some 745x and try to ensure
0089      * L2 prefetch engines are idle. As explained by errata
0090      * text, we can't be sure they are, we just hope very hard
0091      * that well be enough (sic !). At least I noticed Apple
0092      * doesn't even bother doing the dcbf's here...
0093      */
0094     mfspr   r4,SPRN_MSSCR0
0095     rlwinm  r4,r4,0,0,29
0096     sync
0097     mtspr   SPRN_MSSCR0,r4
0098     sync
0099     isync
0100     lis r4,KERNELBASE@h
0101     dcbf    0,r4
0102     dcbf    0,r4
0103     dcbf    0,r4
0104     dcbf    0,r4
0105 END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
0106 2:
0107 BEGIN_FTR_SECTION
0108     /* Go to low speed mode on some 750FX */
0109     lis r4,powersave_lowspeed@ha
0110     lwz r4,powersave_lowspeed@l(r4)
0111     cmpwi   0,r4,0
0112     beq 1f
0113     mfspr   r4,SPRN_HID1
0114     oris    r4,r4,0x0001
0115     mtspr   SPRN_HID1,r4
0116 1:
0117 END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
0118
0119     /* Go to NAP or DOZE now */
0120     mfspr   r4,SPRN_HID0
0121     lis r5,(HID0_NAP|HID0_SLEEP)@h
0122 BEGIN_FTR_SECTION
0123     oris    r5,r5,HID0_DOZE@h
0124 END_FTR_SECTION_IFSET(CPU_FTR_CAN_DOZE)
0125     andc    r4,r4,r5
0126     or  r4,r4,r3
0127 BEGIN_FTR_SECTION
0128     oris    r4,r4,HID0_DPM@h    /* that should be done once for all  */
0129 END_FTR_SECTION_IFCLR(CPU_FTR_NO_DPM)
0130     mtspr   SPRN_HID0,r4
0131 BEGIN_FTR_SECTION
0132     PPC_DSSALL
0133     sync
0134 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
0135     lwz r8,TI_LOCAL_FLAGS(r2)   /* set napping bit */
0136     ori r8,r8,_TLF_NAPPING  /* so when we take an exception */
0137     stw r8,TI_LOCAL_FLAGS(r2)   /* it will return to our caller */
0138     mfmsr   r7
0139     ori r7,r7,MSR_EE
0140     oris    r7,r7,MSR_POW@h
0141 1:  sync
0142     mtmsr   r7
0143     isync
0144     b   1b
0145
0146 /*
0147  * Return from NAP/DOZE mode, restore some CPU specific registers,
0148  * R11 points to the exception frame. We have to preserve r10.
0149  */
0150 _GLOBAL(power_save_ppc32_restore)
0151     lwz r9,_LINK(r11)       /* interrupted in ppc6xx_idle: */
0152     stw r9,_NIP(r11)        /* make it do a blr */
0153
0154 #ifdef CONFIG_SMP
0155     lwz r11,TASK_CPU(r2)    /* get cpu number * 4 */
0156     slwi    r11,r11,2
0157 #else
0158     li  r11,0
0159 #endif
0160     /* Todo make sure all these are in the same page
0161      * and load r11 (@ha part + CPU offset) only once
0162      */
0163 BEGIN_FTR_SECTION
0164     mfspr   r9,SPRN_HID0
0165     andis.  r9,r9,HID0_NAP@h
0166     beq 1f
0167     addis   r9, r11, nap_save_msscr0@ha
0168     lwz r9,nap_save_msscr0@l(r9)
0169     mtspr   SPRN_MSSCR0, r9
0170     sync
0171     isync
0172 1:
0173 END_FTR_SECTION_IFSET(CPU_FTR_NAP_DISABLE_L2_PR)
0174 BEGIN_FTR_SECTION
0175     addis   r9, r11, nap_save_hid1@ha
0176     lwz r9,nap_save_hid1@l(r9)
0177     mtspr   SPRN_HID1, r9
0178 END_FTR_SECTION_IFSET(CPU_FTR_DUAL_PLL_750FX)
0179     blr
0180 _ASM_NOKPROBE_SYMBOL(power_save_ppc32_restore)
0181
0182     .data
0183
0184 _GLOBAL(nap_save_msscr0)
0185     .space  4*NR_CPUS
0186
0187 _GLOBAL(nap_save_hid1)
0188     .space  4*NR_CPUS
0189
0190 _GLOBAL(powersave_lowspeed)
0191     .long   0