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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Kernel execution entry point code.
0004  *
0005  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
0006  *      Initial PowerPC version.
0007  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
0008  *      Rewritten for PReP
0009  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
0010  *      Low-level exception handers, MMU support, and rewrite.
0011  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
0012  *      PowerPC 8xx modifications.
0013  *    Copyright (c) 1998-1999 TiVo, Inc.
0014  *      PowerPC 403GCX modifications.
0015  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
0016  *      PowerPC 403GCX/405GP modifications.
0017  *    Copyright 2000 MontaVista Software Inc.
0018  *  PPC405 modifications
0019  *      PowerPC 403GCX/405GP modifications.
0020  *  Author: MontaVista Software, Inc.
0021  *          frank_rowand@mvista.com or source@mvista.com
0022  *      debbie_chu@mvista.com
0023  *    Copyright 2002-2005 MontaVista Software, Inc.
0024  *      PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
0025  */
0026 
0027 #include <linux/init.h>
0028 #include <linux/pgtable.h>
0029 #include <asm/processor.h>
0030 #include <asm/page.h>
0031 #include <asm/mmu.h>
0032 #include <asm/cputable.h>
0033 #include <asm/thread_info.h>
0034 #include <asm/ppc_asm.h>
0035 #include <asm/asm-offsets.h>
0036 #include <asm/ptrace.h>
0037 #include <asm/synch.h>
0038 #include <asm/export.h>
0039 #include <asm/code-patching-asm.h>
0040 #include "head_booke.h"
0041 
0042 
0043 /* As with the other PowerPC ports, it is expected that when code
0044  * execution begins here, the following registers contain valid, yet
0045  * optional, information:
0046  *
0047  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
0048  *   r4 - Starting address of the init RAM disk
0049  *   r5 - Ending address of the init RAM disk
0050  *   r6 - Start of kernel command line string (e.g. "mem=128")
0051  *   r7 - End of kernel command line string
0052  *
0053  */
0054     __HEAD
0055 _GLOBAL(_stext);
0056 _GLOBAL(_start);
0057     /*
0058      * Reserve a word at a fixed location to store the address
0059      * of abatron_pteptrs
0060      */
0061     nop
0062     mr  r31,r3      /* save device tree ptr */
0063     li  r24,0       /* CPU number */
0064 
0065 #ifdef CONFIG_RELOCATABLE
0066 /*
0067  * Relocate ourselves to the current runtime address.
0068  * This is called only by the Boot CPU.
0069  * "relocate" is called with our current runtime virutal
0070  * address.
0071  * r21 will be loaded with the physical runtime address of _stext
0072  */
0073     bcl 20,31,$+4           /* Get our runtime address */
0074 0:  mflr    r21             /* Make it accessible */
0075     addis   r21,r21,(_stext - 0b)@ha
0076     addi    r21,r21,(_stext - 0b)@l     /* Get our current runtime base */
0077 
0078     /*
0079      * We have the runtime (virutal) address of our base.
0080      * We calculate our shift of offset from a 256M page.
0081      * We could map the 256M page we belong to at PAGE_OFFSET and
0082      * get going from there.
0083      */
0084     lis r4,KERNELBASE@h
0085     ori r4,r4,KERNELBASE@l
0086     rlwinm  r6,r21,0,4,31           /* r6 = PHYS_START % 256M */
0087     rlwinm  r5,r4,0,4,31            /* r5 = KERNELBASE % 256M */
0088     subf    r3,r5,r6            /* r3 = r6 - r5 */
0089     add r3,r4,r3            /* Required Virutal Address */
0090 
0091     bl  relocate
0092 #endif
0093 
0094     bl  init_cpu_state
0095 
0096     /*
0097      * This is where the main kernel code starts.
0098      */
0099 
0100     /* ptr to current */
0101     lis r2,init_task@h
0102     ori r2,r2,init_task@l
0103 
0104     /* ptr to current thread */
0105     addi    r4,r2,THREAD    /* init task's THREAD */
0106     mtspr   SPRN_SPRG_THREAD,r4
0107 
0108     /* stack */
0109     lis r1,init_thread_union@h
0110     ori r1,r1,init_thread_union@l
0111     li  r0,0
0112     stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
0113 
0114     bl  early_init
0115 
0116 #ifdef CONFIG_RELOCATABLE
0117     /*
0118      * Relocatable kernel support based on processing of dynamic
0119      * relocation entries.
0120      *
0121      * r25 will contain RPN/ERPN for the start address of memory
0122      * r21 will contain the current offset of _stext
0123      */
0124     lis r3,kernstart_addr@ha
0125     la  r3,kernstart_addr@l(r3)
0126 
0127     /*
0128      * Compute the kernstart_addr.
0129      * kernstart_addr => (r6,r8)
0130      * kernstart_addr & ~0xfffffff => (r6,r7)
0131      */
0132     rlwinm  r6,r25,0,28,31  /* ERPN. Bits 32-35 of Address */
0133     rlwinm  r7,r25,0,0,3    /* RPN - assuming 256 MB page size */
0134     rlwinm  r8,r21,0,4,31   /* r8 = (_stext & 0xfffffff) */
0135     or  r8,r7,r8    /* Compute the lower 32bit of kernstart_addr */
0136 
0137     /* Store kernstart_addr */
0138     stw r6,0(r3)    /* higher 32bit */
0139     stw r8,4(r3)    /* lower 32bit  */
0140 
0141     /*
0142      * Compute the virt_phys_offset :
0143      * virt_phys_offset = stext.run - kernstart_addr
0144      *
0145      * stext.run = (KERNELBASE & ~0xfffffff) + (kernstart_addr & 0xfffffff)
0146      * When we relocate, we have :
0147      *
0148      *  (kernstart_addr & 0xfffffff) = (stext.run & 0xfffffff)
0149      *
0150      * hence:
0151      *  virt_phys_offset = (KERNELBASE & ~0xfffffff) - (kernstart_addr & ~0xfffffff)
0152      *
0153      */
0154 
0155     /* KERNELBASE&~0xfffffff => (r4,r5) */
0156     li  r4, 0       /* higer 32bit */
0157     lis r5,KERNELBASE@h
0158     rlwinm  r5,r5,0,0,3 /* Align to 256M, lower 32bit */
0159 
0160     /*
0161      * 64bit subtraction.
0162      */
0163     subfc   r5,r7,r5
0164     subfe   r4,r6,r4
0165 
0166     /* Store virt_phys_offset */
0167     lis r3,virt_phys_offset@ha
0168     la  r3,virt_phys_offset@l(r3)
0169 
0170     stw r4,0(r3)
0171     stw r5,4(r3)
0172 
0173 #elif defined(CONFIG_DYNAMIC_MEMSTART)
0174     /*
0175      * Mapping based, page aligned dynamic kernel loading.
0176      *
0177      * r25 will contain RPN/ERPN for the start address of memory
0178      *
0179      * Add the difference between KERNELBASE and PAGE_OFFSET to the
0180      * start of physical memory to get kernstart_addr.
0181      */
0182     lis r3,kernstart_addr@ha
0183     la  r3,kernstart_addr@l(r3)
0184 
0185     lis r4,KERNELBASE@h
0186     ori r4,r4,KERNELBASE@l
0187     lis r5,PAGE_OFFSET@h
0188     ori r5,r5,PAGE_OFFSET@l
0189     subf    r4,r5,r4
0190 
0191     rlwinm  r6,r25,0,28,31  /* ERPN */
0192     rlwinm  r7,r25,0,0,3    /* RPN - assuming 256 MB page size */
0193     add r7,r7,r4
0194 
0195     stw r6,0(r3)
0196     stw r7,4(r3)
0197 #endif
0198 
0199 /*
0200  * Decide what sort of machine this is and initialize the MMU.
0201  */
0202 #ifdef CONFIG_KASAN
0203     bl  kasan_early_init
0204 #endif
0205     li  r3,0
0206     mr  r4,r31
0207     bl  machine_init
0208     bl  MMU_init
0209 
0210     /* Setup PTE pointers for the Abatron bdiGDB */
0211     lis r6, swapper_pg_dir@h
0212     ori r6, r6, swapper_pg_dir@l
0213     lis r5, abatron_pteptrs@h
0214     ori r5, r5, abatron_pteptrs@l
0215     lis r4, KERNELBASE@h
0216     ori r4, r4, KERNELBASE@l
0217     stw r5, 0(r4)   /* Save abatron_pteptrs at a fixed location */
0218     stw r6, 0(r5)
0219 
0220     /* Clear the Machine Check Syndrome Register */
0221     li  r0,0
0222     mtspr   SPRN_MCSR,r0
0223 
0224     /* Let's move on */
0225     lis r4,start_kernel@h
0226     ori r4,r4,start_kernel@l
0227     lis r3,MSR_KERNEL@h
0228     ori r3,r3,MSR_KERNEL@l
0229     mtspr   SPRN_SRR0,r4
0230     mtspr   SPRN_SRR1,r3
0231     rfi         /* change context and jump to start_kernel */
0232 
0233 /*
0234  * Interrupt vector entry code
0235  *
0236  * The Book E MMUs are always on so we don't need to handle
0237  * interrupts in real mode as with previous PPC processors. In
0238  * this case we handle interrupts in the kernel virtual address
0239  * space.
0240  *
0241  * Interrupt vectors are dynamically placed relative to the
0242  * interrupt prefix as determined by the address of interrupt_base.
0243  * The interrupt vectors offsets are programmed using the labels
0244  * for each interrupt vector entry.
0245  *
0246  * Interrupt vectors must be aligned on a 16 byte boundary.
0247  * We align on a 32 byte cache line boundary for good measure.
0248  */
0249 
0250 interrupt_base:
0251     /* Critical Input Interrupt */
0252     CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
0253 
0254     /* Machine Check Interrupt */
0255     CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
0256                machine_check_exception)
0257     MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
0258 
0259     /* Data Storage Interrupt */
0260     DATA_STORAGE_EXCEPTION
0261 
0262         /* Instruction Storage Interrupt */
0263     INSTRUCTION_STORAGE_EXCEPTION
0264 
0265     /* External Input Interrupt */
0266     EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTERNAL, ExternalInput, do_IRQ)
0267 
0268     /* Alignment Interrupt */
0269     ALIGNMENT_EXCEPTION
0270 
0271     /* Program Interrupt */
0272     PROGRAM_EXCEPTION
0273 
0274     /* Floating Point Unavailable Interrupt */
0275 #ifdef CONFIG_PPC_FPU
0276     FP_UNAVAILABLE_EXCEPTION
0277 #else
0278     EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_UNAVAIL, \
0279           FloatingPointUnavailable, unknown_exception)
0280 #endif
0281     /* System Call Interrupt */
0282     START_EXCEPTION(SystemCall)
0283     SYSCALL_ENTRY   0xc00 BOOKE_INTERRUPT_SYSCALL
0284 
0285     /* Auxiliary Processor Unavailable Interrupt */
0286     EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_UNAVAIL, \
0287           AuxillaryProcessorUnavailable, unknown_exception)
0288 
0289     /* Decrementer Interrupt */
0290     DECREMENTER_EXCEPTION
0291 
0292     /* Fixed Internal Timer Interrupt */
0293     /* TODO: Add FIT support */
0294     EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT, FixedIntervalTimer, unknown_exception)
0295 
0296     /* Watchdog Timer Interrupt */
0297     /* TODO: Add watchdog support */
0298 #ifdef CONFIG_BOOKE_WDT
0299     CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, WatchdogException)
0300 #else
0301     CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, unknown_exception)
0302 #endif
0303 
0304     /* Data TLB Error Interrupt */
0305     START_EXCEPTION(DataTLBError44x)
0306     mtspr   SPRN_SPRG_WSCRATCH0, r10        /* Save some working registers */
0307     mtspr   SPRN_SPRG_WSCRATCH1, r11
0308     mtspr   SPRN_SPRG_WSCRATCH2, r12
0309     mtspr   SPRN_SPRG_WSCRATCH3, r13
0310     mfcr    r11
0311     mtspr   SPRN_SPRG_WSCRATCH4, r11
0312     mfspr   r10, SPRN_DEAR      /* Get faulting address */
0313 
0314     /* If we are faulting a kernel address, we have to use the
0315      * kernel page tables.
0316      */
0317     lis r11, PAGE_OFFSET@h
0318     cmplw   r10, r11
0319     blt+    3f
0320     lis r11, swapper_pg_dir@h
0321     ori r11, r11, swapper_pg_dir@l
0322 
0323     mfspr   r12,SPRN_MMUCR
0324     rlwinm  r12,r12,0,0,23      /* Clear TID */
0325 
0326     b   4f
0327 
0328     /* Get the PGD for the current thread */
0329 3:
0330     mfspr   r11,SPRN_SPRG_THREAD
0331     lwz r11,PGDIR(r11)
0332 
0333     /* Load PID into MMUCR TID */
0334     mfspr   r12,SPRN_MMUCR
0335     mfspr   r13,SPRN_PID        /* Get PID */
0336     rlwimi  r12,r13,0,24,31     /* Set TID */
0337 #ifdef CONFIG_PPC_KUAP
0338     cmpwi   r13,0
0339     beq 2f          /* KUAP Fault */
0340 #endif
0341 
0342 4:
0343     mtspr   SPRN_MMUCR,r12
0344 
0345     /* Mask of required permission bits. Note that while we
0346      * do copy ESR:ST to _PAGE_RW position as trying to write
0347      * to an RO page is pretty common, we don't do it with
0348      * _PAGE_DIRTY. We could do it, but it's a fairly rare
0349      * event so I'd rather take the overhead when it happens
0350      * rather than adding an instruction here. We should measure
0351      * whether the whole thing is worth it in the first place
0352      * as we could avoid loading SPRN_ESR completely in the first
0353      * place...
0354      *
0355      * TODO: Is it worth doing that mfspr & rlwimi in the first
0356      *       place or can we save a couple of instructions here ?
0357      */
0358     mfspr   r12,SPRN_ESR
0359     li  r13,_PAGE_PRESENT|_PAGE_ACCESSED
0360     rlwimi  r13,r12,10,30,30
0361 
0362     /* Load the PTE */
0363     /* Compute pgdir/pmd offset */
0364     rlwinm  r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
0365     lwzx    r11, r12, r11       /* Get pgd/pmd entry */
0366     rlwinm. r12, r11, 0, 0, 20  /* Extract pt base address */
0367     beq 2f          /* Bail if no table */
0368 
0369     /* Compute pte address */
0370     rlwimi  r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
0371     lwz r11, 0(r12)     /* Get high word of pte entry */
0372     lwz r12, 4(r12)     /* Get low word of pte entry */
0373 
0374     lis r10,tlb_44x_index@ha
0375 
0376     andc.   r13,r13,r12     /* Check permission */
0377 
0378     /* Load the next available TLB index */
0379     lwz r13,tlb_44x_index@l(r10)
0380 
0381     bne 2f          /* Bail if permission mismatch */
0382 
0383     /* Increment, rollover, and store TLB index */
0384     addi    r13,r13,1
0385 
0386     patch_site 0f, patch__tlb_44x_hwater_D
0387     /* Compare with watermark (instruction gets patched) */
0388 0:  cmpwi   0,r13,1         /* reserve entries */
0389     ble 5f
0390     li  r13,0
0391 5:
0392     /* Store the next available TLB index */
0393     stw r13,tlb_44x_index@l(r10)
0394 
0395     /* Re-load the faulting address */
0396     mfspr   r10,SPRN_DEAR
0397 
0398      /* Jump to common tlb load */
0399     b   finish_tlb_load_44x
0400 
0401 2:
0402     /* The bailout.  Restore registers to pre-exception conditions
0403      * and call the heavyweights to help us out.
0404      */
0405     mfspr   r11, SPRN_SPRG_RSCRATCH4
0406     mtcr    r11
0407     mfspr   r13, SPRN_SPRG_RSCRATCH3
0408     mfspr   r12, SPRN_SPRG_RSCRATCH2
0409     mfspr   r11, SPRN_SPRG_RSCRATCH1
0410     mfspr   r10, SPRN_SPRG_RSCRATCH0
0411     b   DataStorage
0412 
0413     /* Instruction TLB Error Interrupt */
0414     /*
0415      * Nearly the same as above, except we get our
0416      * information from different registers and bailout
0417      * to a different point.
0418      */
0419     START_EXCEPTION(InstructionTLBError44x)
0420     mtspr   SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
0421     mtspr   SPRN_SPRG_WSCRATCH1, r11
0422     mtspr   SPRN_SPRG_WSCRATCH2, r12
0423     mtspr   SPRN_SPRG_WSCRATCH3, r13
0424     mfcr    r11
0425     mtspr   SPRN_SPRG_WSCRATCH4, r11
0426     mfspr   r10, SPRN_SRR0      /* Get faulting address */
0427 
0428     /* If we are faulting a kernel address, we have to use the
0429      * kernel page tables.
0430      */
0431     lis r11, PAGE_OFFSET@h
0432     cmplw   r10, r11
0433     blt+    3f
0434     lis r11, swapper_pg_dir@h
0435     ori r11, r11, swapper_pg_dir@l
0436 
0437     mfspr   r12,SPRN_MMUCR
0438     rlwinm  r12,r12,0,0,23      /* Clear TID */
0439 
0440     b   4f
0441 
0442     /* Get the PGD for the current thread */
0443 3:
0444     mfspr   r11,SPRN_SPRG_THREAD
0445     lwz r11,PGDIR(r11)
0446 
0447     /* Load PID into MMUCR TID */
0448     mfspr   r12,SPRN_MMUCR
0449     mfspr   r13,SPRN_PID        /* Get PID */
0450     rlwimi  r12,r13,0,24,31     /* Set TID */
0451 #ifdef CONFIG_PPC_KUAP
0452     cmpwi   r13,0
0453     beq 2f          /* KUAP Fault */
0454 #endif
0455 
0456 4:
0457     mtspr   SPRN_MMUCR,r12
0458 
0459     /* Make up the required permissions */
0460     li  r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
0461 
0462     /* Compute pgdir/pmd offset */
0463     rlwinm  r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
0464     lwzx    r11, r12, r11       /* Get pgd/pmd entry */
0465     rlwinm. r12, r11, 0, 0, 20  /* Extract pt base address */
0466     beq 2f          /* Bail if no table */
0467 
0468     /* Compute pte address */
0469     rlwimi  r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
0470     lwz r11, 0(r12)     /* Get high word of pte entry */
0471     lwz r12, 4(r12)     /* Get low word of pte entry */
0472 
0473     lis r10,tlb_44x_index@ha
0474 
0475     andc.   r13,r13,r12     /* Check permission */
0476 
0477     /* Load the next available TLB index */
0478     lwz r13,tlb_44x_index@l(r10)
0479 
0480     bne 2f          /* Bail if permission mismatch */
0481 
0482     /* Increment, rollover, and store TLB index */
0483     addi    r13,r13,1
0484 
0485     patch_site 0f, patch__tlb_44x_hwater_I
0486     /* Compare with watermark (instruction gets patched) */
0487 0:  cmpwi   0,r13,1         /* reserve entries */
0488     ble 5f
0489     li  r13,0
0490 5:
0491     /* Store the next available TLB index */
0492     stw r13,tlb_44x_index@l(r10)
0493 
0494     /* Re-load the faulting address */
0495     mfspr   r10,SPRN_SRR0
0496 
0497     /* Jump to common TLB load point */
0498     b   finish_tlb_load_44x
0499 
0500 2:
0501     /* The bailout.  Restore registers to pre-exception conditions
0502      * and call the heavyweights to help us out.
0503      */
0504     mfspr   r11, SPRN_SPRG_RSCRATCH4
0505     mtcr    r11
0506     mfspr   r13, SPRN_SPRG_RSCRATCH3
0507     mfspr   r12, SPRN_SPRG_RSCRATCH2
0508     mfspr   r11, SPRN_SPRG_RSCRATCH1
0509     mfspr   r10, SPRN_SPRG_RSCRATCH0
0510     b   InstructionStorage
0511 
0512 /*
0513  * Both the instruction and data TLB miss get to this
0514  * point to load the TLB.
0515  *  r10 - EA of fault
0516  *  r11 - PTE high word value
0517  *  r12 - PTE low word value
0518  *  r13 - TLB index
0519  *  MMUCR - loaded with proper value when we get here
0520  *  Upon exit, we reload everything and RFI.
0521  */
0522 finish_tlb_load_44x:
0523     /* Combine RPN & ERPN an write WS 0 */
0524     rlwimi  r11,r12,0,0,31-PAGE_SHIFT
0525     tlbwe   r11,r13,PPC44x_TLB_XLAT
0526 
0527     /*
0528      * Create WS1. This is the faulting address (EPN),
0529      * page size, and valid flag.
0530      */
0531     li  r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
0532     /* Insert valid and page size */
0533     rlwimi  r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
0534     tlbwe   r10,r13,PPC44x_TLB_PAGEID   /* Write PAGEID */
0535 
0536     /* And WS 2 */
0537     li  r10,0xf85           /* Mask to apply from PTE */
0538     rlwimi  r10,r12,29,30,30        /* DIRTY -> SW position */
0539     and r11,r12,r10         /* Mask PTE bits to keep */
0540     andi.   r10,r12,_PAGE_USER      /* User page ? */
0541     beq 1f              /* nope, leave U bits empty */
0542     rlwimi  r11,r11,3,26,28         /* yes, copy S bits to U */
0543     rlwinm  r11,r11,0,~PPC44x_TLB_SX    /* Clear SX if User page */
0544 1:  tlbwe   r11,r13,PPC44x_TLB_ATTRIB   /* Write ATTRIB */
0545 
0546     /* Done...restore registers and get out of here.
0547     */
0548     mfspr   r11, SPRN_SPRG_RSCRATCH4
0549     mtcr    r11
0550     mfspr   r13, SPRN_SPRG_RSCRATCH3
0551     mfspr   r12, SPRN_SPRG_RSCRATCH2
0552     mfspr   r11, SPRN_SPRG_RSCRATCH1
0553     mfspr   r10, SPRN_SPRG_RSCRATCH0
0554     rfi                 /* Force context change */
0555 
0556 /* TLB error interrupts for 476
0557  */
0558 #ifdef CONFIG_PPC_47x
0559     START_EXCEPTION(DataTLBError47x)
0560     mtspr   SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
0561     mtspr   SPRN_SPRG_WSCRATCH1,r11
0562     mtspr   SPRN_SPRG_WSCRATCH2,r12
0563     mtspr   SPRN_SPRG_WSCRATCH3,r13
0564     mfcr    r11
0565     mtspr   SPRN_SPRG_WSCRATCH4,r11
0566     mfspr   r10,SPRN_DEAR       /* Get faulting address */
0567 
0568     /* If we are faulting a kernel address, we have to use the
0569      * kernel page tables.
0570      */
0571     lis r11,PAGE_OFFSET@h
0572     cmplw   cr0,r10,r11
0573     blt+    3f
0574     lis r11,swapper_pg_dir@h
0575     ori r11,r11, swapper_pg_dir@l
0576     li  r12,0           /* MMUCR = 0 */
0577     b   4f
0578 
0579     /* Get the PGD for the current thread and setup MMUCR */
0580 3:  mfspr   r11,SPRN_SPRG3
0581     lwz r11,PGDIR(r11)
0582     mfspr   r12,SPRN_PID        /* Get PID */
0583 #ifdef CONFIG_PPC_KUAP
0584     cmpwi   r12,0
0585     beq 2f          /* KUAP Fault */
0586 #endif
0587 4:  mtspr   SPRN_MMUCR,r12      /* Set MMUCR */
0588 
0589     /* Mask of required permission bits. Note that while we
0590      * do copy ESR:ST to _PAGE_RW position as trying to write
0591      * to an RO page is pretty common, we don't do it with
0592      * _PAGE_DIRTY. We could do it, but it's a fairly rare
0593      * event so I'd rather take the overhead when it happens
0594      * rather than adding an instruction here. We should measure
0595      * whether the whole thing is worth it in the first place
0596      * as we could avoid loading SPRN_ESR completely in the first
0597      * place...
0598      *
0599      * TODO: Is it worth doing that mfspr & rlwimi in the first
0600      *       place or can we save a couple of instructions here ?
0601      */
0602     mfspr   r12,SPRN_ESR
0603     li  r13,_PAGE_PRESENT|_PAGE_ACCESSED
0604     rlwimi  r13,r12,10,30,30
0605 
0606     /* Load the PTE */
0607     /* Compute pgdir/pmd offset */
0608     rlwinm  r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
0609     lwzx    r11,r12,r11     /* Get pgd/pmd entry */
0610 
0611     /* Word 0 is EPN,V,TS,DSIZ */
0612     li  r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
0613     rlwimi  r10,r12,0,32-PAGE_SHIFT,31  /* Insert valid and page size*/
0614     li  r12,0
0615     tlbwe   r10,r12,0
0616 
0617     /* XXX can we do better ? Need to make sure tlbwe has established
0618      * latch V bit in MMUCR0 before the PTE is loaded further down */
0619 #ifdef CONFIG_SMP
0620     isync
0621 #endif
0622 
0623     rlwinm. r12,r11,0,0,20      /* Extract pt base address */
0624     /* Compute pte address */
0625     rlwimi  r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
0626     beq 2f          /* Bail if no table */
0627     lwz r11,0(r12)      /* Get high word of pte entry */
0628 
0629     /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
0630      * bottom of r12 to create a data dependency... We can also use r10
0631      * as destination nowadays
0632      */
0633 #ifdef CONFIG_SMP
0634     lwsync
0635 #endif
0636     lwz r12,4(r12)      /* Get low word of pte entry */
0637 
0638     andc.   r13,r13,r12     /* Check permission */
0639 
0640      /* Jump to common tlb load */
0641     beq finish_tlb_load_47x
0642 
0643 2:  /* The bailout.  Restore registers to pre-exception conditions
0644      * and call the heavyweights to help us out.
0645      */
0646     mfspr   r11,SPRN_SPRG_RSCRATCH4
0647     mtcr    r11
0648     mfspr   r13,SPRN_SPRG_RSCRATCH3
0649     mfspr   r12,SPRN_SPRG_RSCRATCH2
0650     mfspr   r11,SPRN_SPRG_RSCRATCH1
0651     mfspr   r10,SPRN_SPRG_RSCRATCH0
0652     b   DataStorage
0653 
0654     /* Instruction TLB Error Interrupt */
0655     /*
0656      * Nearly the same as above, except we get our
0657      * information from different registers and bailout
0658      * to a different point.
0659      */
0660     START_EXCEPTION(InstructionTLBError47x)
0661     mtspr   SPRN_SPRG_WSCRATCH0,r10 /* Save some working registers */
0662     mtspr   SPRN_SPRG_WSCRATCH1,r11
0663     mtspr   SPRN_SPRG_WSCRATCH2,r12
0664     mtspr   SPRN_SPRG_WSCRATCH3,r13
0665     mfcr    r11
0666     mtspr   SPRN_SPRG_WSCRATCH4,r11
0667     mfspr   r10,SPRN_SRR0       /* Get faulting address */
0668 
0669     /* If we are faulting a kernel address, we have to use the
0670      * kernel page tables.
0671      */
0672     lis r11,PAGE_OFFSET@h
0673     cmplw   cr0,r10,r11
0674     blt+    3f
0675     lis r11,swapper_pg_dir@h
0676     ori r11,r11, swapper_pg_dir@l
0677     li  r12,0           /* MMUCR = 0 */
0678     b   4f
0679 
0680     /* Get the PGD for the current thread and setup MMUCR */
0681 3:  mfspr   r11,SPRN_SPRG_THREAD
0682     lwz r11,PGDIR(r11)
0683     mfspr   r12,SPRN_PID        /* Get PID */
0684 #ifdef CONFIG_PPC_KUAP
0685     cmpwi   r12,0
0686     beq 2f          /* KUAP Fault */
0687 #endif
0688 4:  mtspr   SPRN_MMUCR,r12      /* Set MMUCR */
0689 
0690     /* Make up the required permissions */
0691     li  r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
0692 
0693     /* Load PTE */
0694     /* Compute pgdir/pmd offset */
0695     rlwinm  r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
0696     lwzx    r11,r12,r11     /* Get pgd/pmd entry */
0697 
0698     /* Word 0 is EPN,V,TS,DSIZ */
0699     li  r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
0700     rlwimi  r10,r12,0,32-PAGE_SHIFT,31  /* Insert valid and page size*/
0701     li  r12,0
0702     tlbwe   r10,r12,0
0703 
0704     /* XXX can we do better ? Need to make sure tlbwe has established
0705      * latch V bit in MMUCR0 before the PTE is loaded further down */
0706 #ifdef CONFIG_SMP
0707     isync
0708 #endif
0709 
0710     rlwinm. r12,r11,0,0,20      /* Extract pt base address */
0711     /* Compute pte address */
0712     rlwimi  r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
0713     beq 2f          /* Bail if no table */
0714 
0715     lwz r11,0(r12)      /* Get high word of pte entry */
0716     /* XXX can we do better ? maybe insert a known 0 bit from r11 into the
0717      * bottom of r12 to create a data dependency... We can also use r10
0718      * as destination nowadays
0719      */
0720 #ifdef CONFIG_SMP
0721     lwsync
0722 #endif
0723     lwz r12,4(r12)      /* Get low word of pte entry */
0724 
0725     andc.   r13,r13,r12     /* Check permission */
0726 
0727     /* Jump to common TLB load point */
0728     beq finish_tlb_load_47x
0729 
0730 2:  /* The bailout.  Restore registers to pre-exception conditions
0731      * and call the heavyweights to help us out.
0732      */
0733     mfspr   r11, SPRN_SPRG_RSCRATCH4
0734     mtcr    r11
0735     mfspr   r13, SPRN_SPRG_RSCRATCH3
0736     mfspr   r12, SPRN_SPRG_RSCRATCH2
0737     mfspr   r11, SPRN_SPRG_RSCRATCH1
0738     mfspr   r10, SPRN_SPRG_RSCRATCH0
0739     b   InstructionStorage
0740 
0741 /*
0742  * Both the instruction and data TLB miss get to this
0743  * point to load the TLB.
0744  *  r10 - free to use
0745  *  r11 - PTE high word value
0746  *  r12 - PTE low word value
0747  *      r13 - free to use
0748  *  MMUCR - loaded with proper value when we get here
0749  *  Upon exit, we reload everything and RFI.
0750  */
0751 finish_tlb_load_47x:
0752     /* Combine RPN & ERPN an write WS 1 */
0753     rlwimi  r11,r12,0,0,31-PAGE_SHIFT
0754     tlbwe   r11,r13,1
0755 
0756     /* And make up word 2 */
0757     li  r10,0xf85           /* Mask to apply from PTE */
0758     rlwimi  r10,r12,29,30,30        /* DIRTY -> SW position */
0759     and r11,r12,r10         /* Mask PTE bits to keep */
0760     andi.   r10,r12,_PAGE_USER      /* User page ? */
0761     beq 1f              /* nope, leave U bits empty */
0762     rlwimi  r11,r11,3,26,28         /* yes, copy S bits to U */
0763     rlwinm  r11,r11,0,~PPC47x_TLB2_SX   /* Clear SX if User page */
0764 1:  tlbwe   r11,r13,2
0765 
0766     /* Done...restore registers and get out of here.
0767     */
0768     mfspr   r11, SPRN_SPRG_RSCRATCH4
0769     mtcr    r11
0770     mfspr   r13, SPRN_SPRG_RSCRATCH3
0771     mfspr   r12, SPRN_SPRG_RSCRATCH2
0772     mfspr   r11, SPRN_SPRG_RSCRATCH1
0773     mfspr   r10, SPRN_SPRG_RSCRATCH0
0774     rfi
0775 
0776 #endif /* CONFIG_PPC_47x */
0777 
0778     /* Debug Interrupt */
0779     /*
0780      * This statement needs to exist at the end of the IVPR
0781      * definition just in case you end up taking a debug
0782      * exception within another exception.
0783      */
0784     DEBUG_CRIT_EXCEPTION
0785 
0786 interrupt_end:
0787 
0788 /*
0789  * Global functions
0790  */
0791 
0792 /*
0793  * Adjust the machine check IVOR on 440A cores
0794  */
0795 _GLOBAL(__fixup_440A_mcheck)
0796     li  r3,MachineCheckA@l
0797     mtspr   SPRN_IVOR1,r3
0798     sync
0799     blr
0800 
0801 /*
0802  * Init CPU state. This is called at boot time or for secondary CPUs
0803  * to setup initial TLB entries, setup IVORs, etc...
0804  *
0805  */
0806 _GLOBAL(init_cpu_state)
0807     mflr    r22
0808 #ifdef CONFIG_PPC_47x
0809     /* We use the PVR to differentiate 44x cores from 476 */
0810     mfspr   r3,SPRN_PVR
0811     srwi    r3,r3,16
0812     cmplwi  cr0,r3,PVR_476FPE@h
0813     beq head_start_47x
0814     cmplwi  cr0,r3,PVR_476@h
0815     beq head_start_47x
0816     cmplwi  cr0,r3,PVR_476_ISS@h
0817     beq head_start_47x
0818 #endif /* CONFIG_PPC_47x */
0819 
0820 /*
0821  * In case the firmware didn't do it, we apply some workarounds
0822  * that are good for all 440 core variants here
0823  */
0824     mfspr   r3,SPRN_CCR0
0825     rlwinm  r3,r3,0,0,27    /* disable icache prefetch */
0826     isync
0827     mtspr   SPRN_CCR0,r3
0828     isync
0829     sync
0830 
0831 /*
0832  * Set up the initial MMU state for 44x
0833  *
0834  * We are still executing code at the virtual address
0835  * mappings set by the firmware for the base of RAM.
0836  *
0837  * We first invalidate all TLB entries but the one
0838  * we are running from.  We then load the KERNELBASE
0839  * mappings so we can begin to use kernel addresses
0840  * natively and so the interrupt vector locations are
0841  * permanently pinned (necessary since Book E
0842  * implementations always have translation enabled).
0843  *
0844  * TODO: Use the known TLB entry we are running from to
0845  *   determine which physical region we are located
0846  *   in.  This can be used to determine where in RAM
0847  *   (on a shared CPU system) or PCI memory space
0848  *   (on a DRAMless system) we are located.
0849  *       For now, we assume a perfect world which means
0850  *   we are located at the base of DRAM (physical 0).
0851  */
0852 
0853 /*
0854  * Search TLB for entry that we are currently using.
0855  * Invalidate all entries but the one we are using.
0856  */
0857     /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
0858     mfspr   r3,SPRN_PID         /* Get PID */
0859     mfmsr   r4              /* Get MSR */
0860     andi.   r4,r4,MSR_IS@l          /* TS=1? */
0861     beq wmmucr              /* If not, leave STS=0 */
0862     oris    r3,r3,PPC44x_MMUCR_STS@h    /* Set STS=1 */
0863 wmmucr: mtspr   SPRN_MMUCR,r3           /* Put MMUCR */
0864     sync
0865 
0866     bcl 20,31,$+4           /* Find our address */
0867 invstr: mflr    r5              /* Make it accessible */
0868     tlbsx   r23,0,r5            /* Find entry we are in */
0869     li  r4,0                /* Start at TLB entry 0 */
0870     li  r3,0                /* Set PAGEID inval value */
0871 1:  cmpw    r23,r4              /* Is this our entry? */
0872     beq skpinv              /* If so, skip the inval */
0873     tlbwe   r3,r4,PPC44x_TLB_PAGEID     /* If not, inval the entry */
0874 skpinv: addi    r4,r4,1             /* Increment */
0875     cmpwi   r4,64               /* Are we done? */
0876     bne 1b              /* If not, repeat */
0877     isync                   /* If so, context change */
0878 
0879 /*
0880  * Configure and load pinned entry into TLB slot 63.
0881  */
0882 #ifdef CONFIG_NONSTATIC_KERNEL
0883     /*
0884      * In case of a NONSTATIC_KERNEL we reuse the TLB XLAT
0885      * entries of the initial mapping set by the boot loader.
0886      * The XLAT entry is stored in r25
0887      */
0888 
0889     /* Read the XLAT entry for our current mapping */
0890     tlbre   r25,r23,PPC44x_TLB_XLAT
0891 
0892     lis r3,KERNELBASE@h
0893     ori r3,r3,KERNELBASE@l
0894 
0895     /* Use our current RPN entry */
0896     mr  r4,r25
0897 #else
0898 
0899     lis r3,PAGE_OFFSET@h
0900     ori r3,r3,PAGE_OFFSET@l
0901 
0902     /* Kernel is at the base of RAM */
0903     li r4, 0            /* Load the kernel physical address */
0904 #endif
0905 
0906     /* Load the kernel PID = 0 */
0907     li  r0,0
0908     mtspr   SPRN_PID,r0
0909     sync
0910 
0911     /* Initialize MMUCR */
0912     li  r5,0
0913     mtspr   SPRN_MMUCR,r5
0914     sync
0915 
0916     /* pageid fields */
0917     clrrwi  r3,r3,10        /* Mask off the effective page number */
0918     ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
0919 
0920     /* xlat fields */
0921     clrrwi  r4,r4,10        /* Mask off the real page number */
0922                     /* ERPN is 0 for first 4GB page */
0923 
0924     /* attrib fields */
0925     /* Added guarded bit to protect against speculative loads/stores */
0926     li  r5,0
0927     ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
0928 
0929         li      r0,63                    /* TLB slot 63 */
0930 
0931     tlbwe   r3,r0,PPC44x_TLB_PAGEID /* Load the pageid fields */
0932     tlbwe   r4,r0,PPC44x_TLB_XLAT   /* Load the translation fields */
0933     tlbwe   r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
0934 
0935     /* Force context change */
0936     mfmsr   r0
0937     mtspr   SPRN_SRR1, r0
0938     lis r0,3f@h
0939     ori r0,r0,3f@l
0940     mtspr   SPRN_SRR0,r0
0941     sync
0942     rfi
0943 
0944     /* If necessary, invalidate original entry we used */
0945 3:  cmpwi   r23,63
0946     beq 4f
0947     li  r6,0
0948     tlbwe   r6,r23,PPC44x_TLB_PAGEID
0949     isync
0950 
0951 4:
0952 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
0953     /* Add UART mapping for early debug. */
0954 
0955     /* pageid fields */
0956     lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
0957     ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K
0958 
0959     /* xlat fields */
0960     lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
0961     ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
0962 
0963     /* attrib fields */
0964     li  r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
0965         li      r0,62                    /* TLB slot 0 */
0966 
0967     tlbwe   r3,r0,PPC44x_TLB_PAGEID
0968     tlbwe   r4,r0,PPC44x_TLB_XLAT
0969     tlbwe   r5,r0,PPC44x_TLB_ATTRIB
0970 
0971     /* Force context change */
0972     isync
0973 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
0974 
0975     /* Establish the interrupt vector offsets */
0976     SET_IVOR(0,  CriticalInput);
0977     SET_IVOR(1,  MachineCheck);
0978     SET_IVOR(2,  DataStorage);
0979     SET_IVOR(3,  InstructionStorage);
0980     SET_IVOR(4,  ExternalInput);
0981     SET_IVOR(5,  Alignment);
0982     SET_IVOR(6,  Program);
0983     SET_IVOR(7,  FloatingPointUnavailable);
0984     SET_IVOR(8,  SystemCall);
0985     SET_IVOR(9,  AuxillaryProcessorUnavailable);
0986     SET_IVOR(10, Decrementer);
0987     SET_IVOR(11, FixedIntervalTimer);
0988     SET_IVOR(12, WatchdogTimer);
0989     SET_IVOR(13, DataTLBError44x);
0990     SET_IVOR(14, InstructionTLBError44x);
0991     SET_IVOR(15, DebugCrit);
0992 
0993     b   head_start_common
0994 
0995 
0996 #ifdef CONFIG_PPC_47x
0997 
0998 #ifdef CONFIG_SMP
0999 
1000 /* Entry point for secondary 47x processors */
1001 _GLOBAL(start_secondary_47x)
1002         mr      r24,r3          /* CPU number */
1003 
1004     bl  init_cpu_state
1005 
1006     /* Now we need to bolt the rest of kernel memory which
1007      * is done in C code. We must be careful because our task
1008      * struct or our stack can (and will probably) be out
1009      * of reach of the initial 256M TLB entry, so we use a
1010      * small temporary stack in .bss for that. This works
1011      * because only one CPU at a time can be in this code
1012      */
1013     lis r1,temp_boot_stack@h
1014     ori r1,r1,temp_boot_stack@l
1015     addi    r1,r1,1024-STACK_FRAME_OVERHEAD
1016     li  r0,0
1017     stw r0,0(r1)
1018     bl  mmu_init_secondary
1019 
1020     /* Now we can get our task struct and real stack pointer */
1021 
1022     /* Get current's stack and current */
1023     lis r2,secondary_current@ha
1024     lwz r2,secondary_current@l(r2)
1025     lwz r1,TASK_STACK(r2)
1026 
1027     /* Current stack pointer */
1028     addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1029     li  r0,0
1030     stw r0,0(r1)
1031 
1032     /* Kernel stack for exception entry in SPRG3 */
1033     addi    r4,r2,THREAD    /* init task's THREAD */
1034     mtspr   SPRN_SPRG3,r4
1035 
1036     b   start_secondary
1037 
1038 #endif /* CONFIG_SMP */
1039 
1040 /*
1041  * Set up the initial MMU state for 44x
1042  *
1043  * We are still executing code at the virtual address
1044  * mappings set by the firmware for the base of RAM.
1045  */
1046 
1047 head_start_47x:
1048     /* Load our current PID->MMUCR TID and MSR IS->MMUCR STS */
1049     mfspr   r3,SPRN_PID         /* Get PID */
1050     mfmsr   r4              /* Get MSR */
1051     andi.   r4,r4,MSR_IS@l          /* TS=1? */
1052     beq 1f              /* If not, leave STS=0 */
1053     oris    r3,r3,PPC47x_MMUCR_STS@h    /* Set STS=1 */
1054 1:  mtspr   SPRN_MMUCR,r3           /* Put MMUCR */
1055     sync
1056 
1057     /* Find the entry we are running from */
1058     bcl 20,31,$+4
1059 1:  mflr    r23
1060     tlbsx   r23,0,r23
1061     tlbre   r24,r23,0
1062     tlbre   r25,r23,1
1063     tlbre   r26,r23,2
1064 
1065 /*
1066  * Cleanup time
1067  */
1068 
1069     /* Initialize MMUCR */
1070     li  r5,0
1071     mtspr   SPRN_MMUCR,r5
1072     sync
1073 
1074 clear_all_utlb_entries:
1075 
1076     #; Set initial values.
1077 
1078     addis       r3,0,0x8000
1079     addi        r4,0,0
1080     addi        r5,0,0
1081     b       clear_utlb_entry
1082 
1083     #; Align the loop to speed things up.
1084 
1085     .align      6
1086 
1087 clear_utlb_entry:
1088 
1089     tlbwe       r4,r3,0
1090     tlbwe       r5,r3,1
1091     tlbwe       r5,r3,2
1092     addis       r3,r3,0x2000
1093     cmpwi       r3,0
1094     bne     clear_utlb_entry
1095     addis       r3,0,0x8000
1096     addis       r4,r4,0x100
1097     cmpwi       r4,0
1098     bne     clear_utlb_entry
1099 
1100     #; Restore original entry.
1101 
1102     oris    r23,r23,0x8000  /* specify the way */
1103     tlbwe       r24,r23,0
1104     tlbwe       r25,r23,1
1105     tlbwe       r26,r23,2
1106 
1107 /*
1108  * Configure and load pinned entry into TLB for the kernel core
1109  */
1110 
1111     lis r3,PAGE_OFFSET@h
1112     ori r3,r3,PAGE_OFFSET@l
1113 
1114     /* Load the kernel PID = 0 */
1115     li  r0,0
1116     mtspr   SPRN_PID,r0
1117     sync
1118 
1119     /* Word 0 */
1120     clrrwi  r3,r3,12        /* Mask off the effective page number */
1121     ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
1122 
1123     /* Word 1 - use r25.  RPN is the same as the original entry */
1124 
1125     /* Word 2 */
1126     li  r5,0
1127     ori r5,r5,PPC47x_TLB2_S_RWX
1128 #ifdef CONFIG_SMP
1129     ori r5,r5,PPC47x_TLB2_M
1130 #endif
1131 
1132     /* We write to way 0 and bolted 0 */
1133     lis r0,0x8800
1134     tlbwe   r3,r0,0
1135     tlbwe   r25,r0,1
1136     tlbwe   r5,r0,2
1137 
1138 /*
1139  * Configure SSPCR, ISPCR and USPCR for now to search everything, we can fix
1140  * them up later
1141  */
1142     LOAD_REG_IMMEDIATE(r3, 0x9abcdef0)
1143     mtspr   SPRN_SSPCR,r3
1144     mtspr   SPRN_USPCR,r3
1145     LOAD_REG_IMMEDIATE(r3, 0x12345670)
1146     mtspr   SPRN_ISPCR,r3
1147 
1148     /* Force context change */
1149     mfmsr   r0
1150     mtspr   SPRN_SRR1, r0
1151     lis r0,3f@h
1152     ori r0,r0,3f@l
1153     mtspr   SPRN_SRR0,r0
1154     sync
1155     rfi
1156 
1157     /* Invalidate original entry we used */
1158 3:
1159     rlwinm  r24,r24,0,21,19 /* clear the "valid" bit */
1160     tlbwe   r24,r23,0
1161     addi    r24,0,0
1162     tlbwe   r24,r23,1
1163     tlbwe   r24,r23,2
1164     isync                   /* Clear out the shadow TLB entries */
1165 
1166 #ifdef CONFIG_PPC_EARLY_DEBUG_44x
1167     /* Add UART mapping for early debug. */
1168 
1169     /* Word 0 */
1170     lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
1171     ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M
1172 
1173     /* Word 1 */
1174     lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
1175     ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
1176 
1177     /* Word 2 */
1178     li  r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)
1179 
1180     /* Bolted in way 0, bolt slot 5, we -hope- we don't hit the same
1181      * congruence class as the kernel, we need to make sure of it at
1182      * some point
1183      */
1184         lis r0,0x8d00
1185     tlbwe   r3,r0,0
1186     tlbwe   r4,r0,1
1187     tlbwe   r5,r0,2
1188 
1189     /* Force context change */
1190     isync
1191 #endif /* CONFIG_PPC_EARLY_DEBUG_44x */
1192 
1193     /* Establish the interrupt vector offsets */
1194     SET_IVOR(0,  CriticalInput);
1195     SET_IVOR(1,  MachineCheckA);
1196     SET_IVOR(2,  DataStorage);
1197     SET_IVOR(3,  InstructionStorage);
1198     SET_IVOR(4,  ExternalInput);
1199     SET_IVOR(5,  Alignment);
1200     SET_IVOR(6,  Program);
1201     SET_IVOR(7,  FloatingPointUnavailable);
1202     SET_IVOR(8,  SystemCall);
1203     SET_IVOR(9,  AuxillaryProcessorUnavailable);
1204     SET_IVOR(10, Decrementer);
1205     SET_IVOR(11, FixedIntervalTimer);
1206     SET_IVOR(12, WatchdogTimer);
1207     SET_IVOR(13, DataTLBError47x);
1208     SET_IVOR(14, InstructionTLBError47x);
1209     SET_IVOR(15, DebugCrit);
1210 
1211     /* We configure icbi to invalidate 128 bytes at a time since the
1212      * current 32-bit kernel code isn't too happy with icache != dcache
1213      * block size. We also disable the BTAC as this can cause errors
1214      * in some circumstances (see IBM Erratum 47).
1215      */
1216     mfspr   r3,SPRN_CCR0
1217     oris    r3,r3,0x0020
1218     ori r3,r3,0x0040
1219     mtspr   SPRN_CCR0,r3
1220     isync
1221 
1222 #endif /* CONFIG_PPC_47x */
1223 
1224 /*
1225  * Here we are back to code that is common between 44x and 47x
1226  *
1227  * We proceed to further kernel initialization and return to the
1228  * main kernel entry
1229  */
1230 head_start_common:
1231     /* Establish the interrupt vector base */
1232     lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
1233     mtspr   SPRN_IVPR,r4
1234 
1235     /*
1236      * If the kernel was loaded at a non-zero 256 MB page, we need to
1237      * mask off the most significant 4 bits to get the relative address
1238      * from the start of physical memory
1239      */
1240     rlwinm  r22,r22,0,4,31
1241     addis   r22,r22,PAGE_OFFSET@h
1242     mtlr    r22
1243     isync
1244     blr
1245 
1246 #ifdef CONFIG_SMP
1247     .data
1248     .align  12
1249 temp_boot_stack:
1250     .space  1024
1251 #endif /* CONFIG_SMP */
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