powerpc/kernel/cpu_setup_ppc970.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * This file contains low level CPU setup functions.
0004  *    Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
0005  */
0006
0007 #include <asm/processor.h>
0008 #include <asm/page.h>
0009 #include <asm/cputable.h>
0010 #include <asm/ppc_asm.h>
0011 #include <asm/asm-offsets.h>
0012 #include <asm/cache.h>
0013
0014 _GLOBAL(__cpu_preinit_ppc970)
0015     /* Do nothing if not running in HV mode */
0016     mfmsr   r0
0017     rldicl. r0,r0,4,63
0018     beqlr
0019
0020     /* Make sure HID4:rm_ci is off before MMU is turned off, that large
0021      * pages are enabled with HID4:61 and clear HID5:DCBZ_size and
0022      * HID5:DCBZ32_ill
0023      */
0024     li  r0,0
0025     mfspr   r3,SPRN_HID4
0026     rldimi  r3,r0,40,23 /* clear bit 23 (rm_ci) */
0027     rldimi  r3,r0,2,61  /* clear bit 61 (lg_pg_en) */
0028     sync
0029     mtspr   SPRN_HID4,r3
0030     isync
0031     sync
0032     mfspr   r3,SPRN_HID5
0033     rldimi  r3,r0,6,56  /* clear bits 56 & 57 (DCBZ*) */
0034     sync
0035     mtspr   SPRN_HID5,r3
0036     isync
0037     sync
0038
0039     /* Setup some basic HID1 features */
0040     mfspr   r0,SPRN_HID1
0041     li  r3,0x1200       /* enable i-fetch cacheability */
0042     sldi    r3,r3,44        /* and prefetch */
0043     or  r0,r0,r3
0044     mtspr   SPRN_HID1,r0
0045     mtspr   SPRN_HID1,r0
0046     isync
0047
0048     /* Clear HIOR */
0049     li  r0,0
0050     sync
0051     mtspr   SPRN_HIOR,0     /* Clear interrupt prefix */
0052     isync
0053     blr
0054
0055 /* Definitions for the table use to save CPU states */
0056 #define CS_HID0     0
0057 #define CS_HID1     8
0058 #define CS_HID4     16
0059 #define CS_HID5     24
0060 #define CS_SIZE     32
0061
0062     .data
0063     .balign L1_CACHE_BYTES,0
0064 cpu_state_storage:
0065     .space  CS_SIZE
0066     .balign L1_CACHE_BYTES,0
0067     .text
0068
0069
0070 _GLOBAL(__setup_cpu_ppc970)
0071     /* Do nothing if not running in HV mode */
0072     mfmsr   r0
0073     rldicl. r0,r0,4,63
0074     beq no_hv_mode
0075
0076     mfspr   r0,SPRN_HID0
0077     li  r11,5           /* clear DOZE and SLEEP */
0078     rldimi  r0,r11,52,8     /* set NAP and DPM */
0079     li  r11,0
0080     rldimi  r0,r11,32,31        /* clear EN_ATTN */
0081     b   load_hids       /* Jump to shared code */
0082
0083
0084 _GLOBAL(__setup_cpu_ppc970MP)
0085     /* Do nothing if not running in HV mode */
0086     mfmsr   r0
0087     rldicl. r0,r0,4,63
0088     beq no_hv_mode
0089
0090     mfspr   r0,SPRN_HID0
0091     li  r11,0x15        /* clear DOZE and SLEEP */
0092     rldimi  r0,r11,52,6     /* set DEEPNAP, NAP and DPM */
0093     li  r11,0
0094     rldimi  r0,r11,32,31        /* clear EN_ATTN */
0095
0096 load_hids:
0097     mtspr   SPRN_HID0,r0
0098     mfspr   r0,SPRN_HID0
0099     mfspr   r0,SPRN_HID0
0100     mfspr   r0,SPRN_HID0
0101     mfspr   r0,SPRN_HID0
0102     mfspr   r0,SPRN_HID0
0103     mfspr   r0,SPRN_HID0
0104     sync
0105     isync
0106
0107     /* Try to set LPES = 01 in HID4 */
0108     mfspr   r0,SPRN_HID4
0109     clrldi  r0,r0,1         /* clear LPES0 */
0110     ori r0,r0,HID4_LPES1    /* set LPES1 */
0111     sync
0112     mtspr   SPRN_HID4,r0
0113     isync
0114
0115     /* Save away cpu state */
0116     LOAD_REG_ADDR(r5,cpu_state_storage)
0117
0118     /* Save HID0,1,4 and 5 */
0119     mfspr   r3,SPRN_HID0
0120     std r3,CS_HID0(r5)
0121     mfspr   r3,SPRN_HID1
0122     std r3,CS_HID1(r5)
0123     mfspr   r4,SPRN_HID4
0124     std r4,CS_HID4(r5)
0125     mfspr   r3,SPRN_HID5
0126     std r3,CS_HID5(r5)
0127
0128     /* See if we successfully set LPES1 to 1; if not we are in Apple mode */
0129     andi.   r4,r4,HID4_LPES1
0130     bnelr
0131
0132 no_hv_mode:
0133     /* Disable CPU_FTR_HVMODE and exit, since we don't have HV mode */
0134     ld  r5,CPU_SPEC_FEATURES(r4)
0135     LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
0136     andc    r5,r5,r6
0137     std r5,CPU_SPEC_FEATURES(r4)
0138     blr
0139
0140 /* Called with no MMU context (typically MSR:IR/DR off) to
0141  * restore CPU state as backed up by the previous
0142  * function. This does not include cache setting
0143  */
0144 _GLOBAL(__restore_cpu_ppc970)
0145     /* Do nothing if not running in HV mode */
0146     mfmsr   r0
0147     rldicl. r0,r0,4,63
0148     beqlr
0149
0150     LOAD_REG_ADDR(r5,cpu_state_storage)
0151     /* Before accessing memory, we make sure rm_ci is clear */
0152     li  r0,0
0153     mfspr   r3,SPRN_HID4
0154     rldimi  r3,r0,40,23 /* clear bit 23 (rm_ci) */
0155     sync
0156     mtspr   SPRN_HID4,r3
0157     isync
0158     sync
0159
0160     /* Clear interrupt prefix */
0161     li  r0,0
0162     sync
0163     mtspr   SPRN_HIOR,0
0164     isync
0165
0166     /* Restore HID0 */
0167     ld  r3,CS_HID0(r5)
0168     sync
0169     isync
0170     mtspr   SPRN_HID0,r3
0171     mfspr   r3,SPRN_HID0
0172     mfspr   r3,SPRN_HID0
0173     mfspr   r3,SPRN_HID0
0174     mfspr   r3,SPRN_HID0
0175     mfspr   r3,SPRN_HID0
0176     mfspr   r3,SPRN_HID0
0177     sync
0178     isync
0179
0180     /* Restore HID1 */
0181     ld  r3,CS_HID1(r5)
0182     sync
0183     isync
0184     mtspr   SPRN_HID1,r3
0185     mtspr   SPRN_HID1,r3
0186     sync
0187     isync
0188
0189     /* Restore HID4 */
0190     ld  r3,CS_HID4(r5)
0191     sync
0192     isync
0193     mtspr   SPRN_HID4,r3
0194     sync
0195     isync
0196
0197     /* Restore HID5 */
0198     ld  r3,CS_HID5(r5)
0199     sync
0200     isync
0201     mtspr   SPRN_HID5,r3
0202     sync
0203     isync
0204     blr
0205