powerpc/kernel/cpu_setup_44x.S

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * This file contains low level CPU setup functions.
0004  * Valentine Barshak <vbarshak@ru.mvista.com>
0005  * MontaVista Software, Inc (c) 2007
0006  *
0007  * Based on cpu_setup_6xx code by
0008  * Benjamin Herrenschmidt <benh@kernel.crashing.org>
0009  */
0010
0011 #include <asm/processor.h>
0012 #include <asm/cputable.h>
0013 #include <asm/ppc_asm.h>
0014
0015 _GLOBAL(__setup_cpu_440ep)
0016     b   __init_fpu_44x
0017 _GLOBAL(__setup_cpu_440epx)
0018     mflr    r4
0019     bl  __init_fpu_44x
0020     bl  __plb_disable_wrp
0021     bl  __fixup_440A_mcheck
0022     mtlr    r4
0023     blr
0024 _GLOBAL(__setup_cpu_440grx)
0025     mflr    r4
0026     bl  __plb_disable_wrp
0027     bl  __fixup_440A_mcheck
0028     mtlr    r4
0029     blr
0030 _GLOBAL(__setup_cpu_460ex)
0031 _GLOBAL(__setup_cpu_460gt)
0032 _GLOBAL(__setup_cpu_460sx)
0033 _GLOBAL(__setup_cpu_apm821xx)
0034     mflr    r4
0035     bl  __init_fpu_44x
0036     bl  __fixup_440A_mcheck
0037     mtlr    r4
0038     blr
0039
0040 _GLOBAL(__setup_cpu_440x5)
0041 _GLOBAL(__setup_cpu_440gx)
0042 _GLOBAL(__setup_cpu_440spe)
0043     b   __fixup_440A_mcheck
0044
0045 /* enable APU between CPU and FPU */
0046 _GLOBAL(__init_fpu_44x)
0047     mfspr   r3,SPRN_CCR0
0048     /* Clear DAPUIB flag in CCR0 */
0049     rlwinm  r3,r3,0,12,10
0050     mtspr   SPRN_CCR0,r3
0051     isync
0052     blr
0053
0054 /*
0055  * Workaround for the incorrect write to DDR SDRAM errata.
0056  * The write address can be corrupted during writes to
0057  * DDR SDRAM when write pipelining is enabled on PLB0.
0058  * Disable write pipelining here.
0059  */
0060 #define DCRN_PLB4A0_ACR 0x81
0061
0062 _GLOBAL(__plb_disable_wrp)
0063     mfdcr   r3,DCRN_PLB4A0_ACR
0064     /* clear WRP bit in PLB4A0_ACR */
0065     rlwinm  r3,r3,0,8,6
0066     mtdcr   DCRN_PLB4A0_ACR,r3
0067     isync
0068     blr
0069