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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * This program is used to generate definitions needed by
0004  * assembly language modules.
0005  *
0006  * We use the technique used in the OSF Mach kernel code:
0007  * generate asm statements containing #defines,
0008  * compile this file to assembler, and then extract the
0009  * #defines from the assembly-language output.
0010  */
0011 
0012 #include <linux/compat.h>
0013 #include <linux/signal.h>
0014 #include <linux/sched.h>
0015 #include <linux/kernel.h>
0016 #include <linux/errno.h>
0017 #include <linux/string.h>
0018 #include <linux/types.h>
0019 #include <linux/mman.h>
0020 #include <linux/mm.h>
0021 #include <linux/suspend.h>
0022 #include <linux/hrtimer.h>
0023 #ifdef CONFIG_PPC64
0024 #include <linux/time.h>
0025 #include <linux/hardirq.h>
0026 #endif
0027 #include <linux/kbuild.h>
0028 
0029 #include <asm/io.h>
0030 #include <asm/page.h>
0031 #include <asm/processor.h>
0032 #include <asm/cputable.h>
0033 #include <asm/thread_info.h>
0034 #include <asm/rtas.h>
0035 #include <asm/vdso_datapage.h>
0036 #include <asm/dbell.h>
0037 #ifdef CONFIG_PPC64
0038 #include <asm/paca.h>
0039 #include <asm/lppaca.h>
0040 #include <asm/cache.h>
0041 #include <asm/mmu.h>
0042 #include <asm/hvcall.h>
0043 #include <asm/xics.h>
0044 #endif
0045 #ifdef CONFIG_PPC_POWERNV
0046 #include <asm/opal.h>
0047 #endif
0048 #if defined(CONFIG_KVM) || defined(CONFIG_KVM_GUEST)
0049 #include <linux/kvm_host.h>
0050 #endif
0051 #if defined(CONFIG_KVM) && defined(CONFIG_PPC_BOOK3S)
0052 #include <asm/kvm_book3s.h>
0053 #include <asm/kvm_ppc.h>
0054 #endif
0055 
0056 #ifdef CONFIG_PPC32
0057 #ifdef CONFIG_BOOKE_OR_40x
0058 #include "head_booke.h"
0059 #endif
0060 #endif
0061 
0062 #if defined(CONFIG_PPC_FSL_BOOK3E)
0063 #include "../mm/mmu_decl.h"
0064 #endif
0065 
0066 #ifdef CONFIG_PPC_8xx
0067 #include <asm/fixmap.h>
0068 #endif
0069 
0070 #ifdef CONFIG_XMON
0071 #include "../xmon/xmon_bpts.h"
0072 #endif
0073 
0074 #define STACK_PT_REGS_OFFSET(sym, val)  \
0075     DEFINE(sym, STACK_FRAME_OVERHEAD + offsetof(struct pt_regs, val))
0076 
0077 int main(void)
0078 {
0079     OFFSET(THREAD, task_struct, thread);
0080     OFFSET(MM, task_struct, mm);
0081 #ifdef CONFIG_STACKPROTECTOR
0082     OFFSET(TASK_CANARY, task_struct, stack_canary);
0083 #ifdef CONFIG_PPC64
0084     OFFSET(PACA_CANARY, paca_struct, canary);
0085 #endif
0086 #endif
0087 #ifdef CONFIG_PPC32
0088 #ifdef CONFIG_PPC_RTAS
0089     OFFSET(RTAS_SP, thread_struct, rtas_sp);
0090 #endif
0091 #endif /* CONFIG_PPC64 */
0092     OFFSET(TASK_STACK, task_struct, stack);
0093 #ifdef CONFIG_SMP
0094     OFFSET(TASK_CPU, task_struct, thread_info.cpu);
0095 #endif
0096 
0097 #ifdef CONFIG_LIVEPATCH_64
0098     OFFSET(TI_livepatch_sp, thread_info, livepatch_sp);
0099 #endif
0100 
0101     OFFSET(KSP, thread_struct, ksp);
0102     OFFSET(PT_REGS, thread_struct, regs);
0103 #ifdef CONFIG_BOOKE
0104     OFFSET(THREAD_NORMSAVES, thread_struct, normsave[0]);
0105 #endif
0106 #ifdef CONFIG_PPC_FPU
0107     OFFSET(THREAD_FPEXC_MODE, thread_struct, fpexc_mode);
0108     OFFSET(THREAD_FPSTATE, thread_struct, fp_state.fpr);
0109     OFFSET(THREAD_FPSAVEAREA, thread_struct, fp_save_area);
0110 #endif
0111     OFFSET(FPSTATE_FPSCR, thread_fp_state, fpscr);
0112     OFFSET(THREAD_LOAD_FP, thread_struct, load_fp);
0113 #ifdef CONFIG_ALTIVEC
0114     OFFSET(THREAD_VRSTATE, thread_struct, vr_state.vr);
0115     OFFSET(THREAD_VRSAVEAREA, thread_struct, vr_save_area);
0116     OFFSET(THREAD_USED_VR, thread_struct, used_vr);
0117     OFFSET(VRSTATE_VSCR, thread_vr_state, vscr);
0118     OFFSET(THREAD_LOAD_VEC, thread_struct, load_vec);
0119 #endif /* CONFIG_ALTIVEC */
0120 #ifdef CONFIG_VSX
0121     OFFSET(THREAD_USED_VSR, thread_struct, used_vsr);
0122 #endif /* CONFIG_VSX */
0123 #ifdef CONFIG_PPC64
0124     OFFSET(KSP_VSID, thread_struct, ksp_vsid);
0125 #else /* CONFIG_PPC64 */
0126     OFFSET(PGDIR, thread_struct, pgdir);
0127     OFFSET(SRR0, thread_struct, srr0);
0128     OFFSET(SRR1, thread_struct, srr1);
0129     OFFSET(DAR, thread_struct, dar);
0130     OFFSET(DSISR, thread_struct, dsisr);
0131 #ifdef CONFIG_PPC_BOOK3S_32
0132     OFFSET(THR0, thread_struct, r0);
0133     OFFSET(THR3, thread_struct, r3);
0134     OFFSET(THR4, thread_struct, r4);
0135     OFFSET(THR5, thread_struct, r5);
0136     OFFSET(THR6, thread_struct, r6);
0137     OFFSET(THR8, thread_struct, r8);
0138     OFFSET(THR9, thread_struct, r9);
0139     OFFSET(THR11, thread_struct, r11);
0140     OFFSET(THLR, thread_struct, lr);
0141     OFFSET(THCTR, thread_struct, ctr);
0142     OFFSET(THSR0, thread_struct, sr0);
0143 #endif
0144 #ifdef CONFIG_SPE
0145     OFFSET(THREAD_EVR0, thread_struct, evr[0]);
0146     OFFSET(THREAD_ACC, thread_struct, acc);
0147     OFFSET(THREAD_USED_SPE, thread_struct, used_spe);
0148 #endif /* CONFIG_SPE */
0149 #endif /* CONFIG_PPC64 */
0150 #ifdef CONFIG_KVM_BOOK3S_32_HANDLER
0151     OFFSET(THREAD_KVM_SVCPU, thread_struct, kvm_shadow_vcpu);
0152 #endif
0153 #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
0154     OFFSET(THREAD_KVM_VCPU, thread_struct, kvm_vcpu);
0155 #endif
0156 
0157 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
0158     OFFSET(PACATMSCRATCH, paca_struct, tm_scratch);
0159     OFFSET(THREAD_TM_TFHAR, thread_struct, tm_tfhar);
0160     OFFSET(THREAD_TM_TEXASR, thread_struct, tm_texasr);
0161     OFFSET(THREAD_TM_TFIAR, thread_struct, tm_tfiar);
0162     OFFSET(THREAD_TM_TAR, thread_struct, tm_tar);
0163     OFFSET(THREAD_TM_PPR, thread_struct, tm_ppr);
0164     OFFSET(THREAD_TM_DSCR, thread_struct, tm_dscr);
0165     OFFSET(THREAD_TM_AMR, thread_struct, tm_amr);
0166     OFFSET(PT_CKPT_REGS, thread_struct, ckpt_regs);
0167     OFFSET(THREAD_CKVRSTATE, thread_struct, ckvr_state.vr);
0168     OFFSET(THREAD_CKVRSAVE, thread_struct, ckvrsave);
0169     OFFSET(THREAD_CKFPSTATE, thread_struct, ckfp_state.fpr);
0170     /* Local pt_regs on stack for Transactional Memory funcs. */
0171     DEFINE(TM_FRAME_SIZE, STACK_FRAME_OVERHEAD +
0172            sizeof(struct pt_regs) + 16);
0173 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
0174 
0175     OFFSET(TI_LOCAL_FLAGS, thread_info, local_flags);
0176 
0177 #ifdef CONFIG_PPC64
0178     OFFSET(DCACHEL1BLOCKSIZE, ppc64_caches, l1d.block_size);
0179     OFFSET(DCACHEL1LOGBLOCKSIZE, ppc64_caches, l1d.log_block_size);
0180     /* paca */
0181     OFFSET(PACAPACAINDEX, paca_struct, paca_index);
0182     OFFSET(PACAPROCSTART, paca_struct, cpu_start);
0183     OFFSET(PACAKSAVE, paca_struct, kstack);
0184     OFFSET(PACACURRENT, paca_struct, __current);
0185     DEFINE(PACA_THREAD_INFO, offsetof(struct paca_struct, __current) +
0186                  offsetof(struct task_struct, thread_info));
0187     OFFSET(PACASAVEDMSR, paca_struct, saved_msr);
0188     OFFSET(PACAR1, paca_struct, saved_r1);
0189     OFFSET(PACATOC, paca_struct, kernel_toc);
0190     OFFSET(PACAKBASE, paca_struct, kernelbase);
0191     OFFSET(PACAKMSR, paca_struct, kernel_msr);
0192 #ifdef CONFIG_PPC_BOOK3S_64
0193     OFFSET(PACAHSRR_VALID, paca_struct, hsrr_valid);
0194     OFFSET(PACASRR_VALID, paca_struct, srr_valid);
0195 #endif
0196     OFFSET(PACAIRQSOFTMASK, paca_struct, irq_soft_mask);
0197     OFFSET(PACAIRQHAPPENED, paca_struct, irq_happened);
0198     OFFSET(PACA_FTRACE_ENABLED, paca_struct, ftrace_enabled);
0199 
0200 #ifdef CONFIG_PPC_BOOK3E
0201     OFFSET(PACAPGD, paca_struct, pgd);
0202     OFFSET(PACA_KERNELPGD, paca_struct, kernel_pgd);
0203     OFFSET(PACA_EXGEN, paca_struct, exgen);
0204     OFFSET(PACA_EXTLB, paca_struct, extlb);
0205     OFFSET(PACA_EXMC, paca_struct, exmc);
0206     OFFSET(PACA_EXCRIT, paca_struct, excrit);
0207     OFFSET(PACA_EXDBG, paca_struct, exdbg);
0208     OFFSET(PACA_MC_STACK, paca_struct, mc_kstack);
0209     OFFSET(PACA_CRIT_STACK, paca_struct, crit_kstack);
0210     OFFSET(PACA_DBG_STACK, paca_struct, dbg_kstack);
0211     OFFSET(PACA_TCD_PTR, paca_struct, tcd_ptr);
0212 
0213     OFFSET(TCD_ESEL_NEXT, tlb_core_data, esel_next);
0214     OFFSET(TCD_ESEL_MAX, tlb_core_data, esel_max);
0215     OFFSET(TCD_ESEL_FIRST, tlb_core_data, esel_first);
0216 #endif /* CONFIG_PPC_BOOK3E */
0217 
0218 #ifdef CONFIG_PPC_BOOK3S_64
0219     OFFSET(PACA_EXGEN, paca_struct, exgen);
0220     OFFSET(PACA_EXMC, paca_struct, exmc);
0221     OFFSET(PACA_EXNMI, paca_struct, exnmi);
0222 #ifdef CONFIG_PPC_64S_HASH_MMU
0223     OFFSET(PACA_SLBSHADOWPTR, paca_struct, slb_shadow_ptr);
0224     OFFSET(SLBSHADOW_STACKVSID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].vsid);
0225     OFFSET(SLBSHADOW_STACKESID, slb_shadow, save_area[SLB_NUM_BOLTED - 1].esid);
0226     OFFSET(SLBSHADOW_SAVEAREA, slb_shadow, save_area);
0227 #endif
0228     OFFSET(LPPACA_PMCINUSE, lppaca, pmcregs_in_use);
0229 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
0230     OFFSET(PACA_PMCINUSE, paca_struct, pmcregs_in_use);
0231 #endif
0232     OFFSET(LPPACA_YIELDCOUNT, lppaca, yield_count);
0233 #endif /* CONFIG_PPC_BOOK3S_64 */
0234     OFFSET(PACAEMERGSP, paca_struct, emergency_sp);
0235 #ifdef CONFIG_PPC_BOOK3S_64
0236     OFFSET(PACAMCEMERGSP, paca_struct, mc_emergency_sp);
0237     OFFSET(PACA_NMI_EMERG_SP, paca_struct, nmi_emergency_sp);
0238     OFFSET(PACA_IN_MCE, paca_struct, in_mce);
0239     OFFSET(PACA_IN_NMI, paca_struct, in_nmi);
0240     OFFSET(PACA_RFI_FLUSH_FALLBACK_AREA, paca_struct, rfi_flush_fallback_area);
0241     OFFSET(PACA_EXRFI, paca_struct, exrfi);
0242     OFFSET(PACA_L1D_FLUSH_SIZE, paca_struct, l1d_flush_size);
0243 
0244 #endif
0245     OFFSET(PACAHWCPUID, paca_struct, hw_cpu_id);
0246     OFFSET(PACAKEXECSTATE, paca_struct, kexec_state);
0247     OFFSET(PACA_DSCR_DEFAULT, paca_struct, dscr_default);
0248 #ifdef CONFIG_PPC64
0249     OFFSET(PACA_EXIT_SAVE_R1, paca_struct, exit_save_r1);
0250 #endif
0251 #ifdef CONFIG_PPC_BOOK3E
0252     OFFSET(PACA_TRAP_SAVE, paca_struct, trap_save);
0253 #endif
0254     OFFSET(PACA_SPRG_VDSO, paca_struct, sprg_vdso);
0255 #else /* CONFIG_PPC64 */
0256 #endif /* CONFIG_PPC64 */
0257 
0258     /* RTAS */
0259     OFFSET(RTASBASE, rtas_t, base);
0260     OFFSET(RTASENTRY, rtas_t, entry);
0261 
0262     /* Interrupt register frame */
0263     DEFINE(INT_FRAME_SIZE, STACK_INT_FRAME_SIZE);
0264     DEFINE(SWITCH_FRAME_SIZE, STACK_FRAME_WITH_PT_REGS);
0265     STACK_PT_REGS_OFFSET(GPR0, gpr[0]);
0266     STACK_PT_REGS_OFFSET(GPR1, gpr[1]);
0267     STACK_PT_REGS_OFFSET(GPR2, gpr[2]);
0268     STACK_PT_REGS_OFFSET(GPR3, gpr[3]);
0269     STACK_PT_REGS_OFFSET(GPR4, gpr[4]);
0270     STACK_PT_REGS_OFFSET(GPR5, gpr[5]);
0271     STACK_PT_REGS_OFFSET(GPR6, gpr[6]);
0272     STACK_PT_REGS_OFFSET(GPR7, gpr[7]);
0273     STACK_PT_REGS_OFFSET(GPR8, gpr[8]);
0274     STACK_PT_REGS_OFFSET(GPR9, gpr[9]);
0275     STACK_PT_REGS_OFFSET(GPR10, gpr[10]);
0276     STACK_PT_REGS_OFFSET(GPR11, gpr[11]);
0277     STACK_PT_REGS_OFFSET(GPR12, gpr[12]);
0278     STACK_PT_REGS_OFFSET(GPR13, gpr[13]);
0279     /*
0280      * Note: these symbols include _ because they overlap with special
0281      * register names
0282      */
0283     STACK_PT_REGS_OFFSET(_NIP, nip);
0284     STACK_PT_REGS_OFFSET(_MSR, msr);
0285     STACK_PT_REGS_OFFSET(_CTR, ctr);
0286     STACK_PT_REGS_OFFSET(_LINK, link);
0287     STACK_PT_REGS_OFFSET(_CCR, ccr);
0288     STACK_PT_REGS_OFFSET(_XER, xer);
0289     STACK_PT_REGS_OFFSET(_DAR, dar);
0290     STACK_PT_REGS_OFFSET(_DEAR, dear);
0291     STACK_PT_REGS_OFFSET(_DSISR, dsisr);
0292     STACK_PT_REGS_OFFSET(_ESR, esr);
0293     STACK_PT_REGS_OFFSET(ORIG_GPR3, orig_gpr3);
0294     STACK_PT_REGS_OFFSET(RESULT, result);
0295     STACK_PT_REGS_OFFSET(_TRAP, trap);
0296 #ifdef CONFIG_PPC64
0297     STACK_PT_REGS_OFFSET(SOFTE, softe);
0298     STACK_PT_REGS_OFFSET(_PPR, ppr);
0299 #endif
0300 
0301 #ifdef CONFIG_PPC_PKEY
0302     STACK_PT_REGS_OFFSET(STACK_REGS_AMR, amr);
0303     STACK_PT_REGS_OFFSET(STACK_REGS_IAMR, iamr);
0304 #endif
0305 
0306 #if defined(CONFIG_PPC32) && defined(CONFIG_BOOKE)
0307     STACK_PT_REGS_OFFSET(MAS0, mas0);
0308     /* we overload MMUCR for 44x on MAS0 since they are mutually exclusive */
0309     STACK_PT_REGS_OFFSET(MMUCR, mas0);
0310     STACK_PT_REGS_OFFSET(MAS1, mas1);
0311     STACK_PT_REGS_OFFSET(MAS2, mas2);
0312     STACK_PT_REGS_OFFSET(MAS3, mas3);
0313     STACK_PT_REGS_OFFSET(MAS6, mas6);
0314     STACK_PT_REGS_OFFSET(MAS7, mas7);
0315     STACK_PT_REGS_OFFSET(_SRR0, srr0);
0316     STACK_PT_REGS_OFFSET(_SRR1, srr1);
0317     STACK_PT_REGS_OFFSET(_CSRR0, csrr0);
0318     STACK_PT_REGS_OFFSET(_CSRR1, csrr1);
0319     STACK_PT_REGS_OFFSET(_DSRR0, dsrr0);
0320     STACK_PT_REGS_OFFSET(_DSRR1, dsrr1);
0321 #endif
0322 
0323     /* About the CPU features table */
0324     OFFSET(CPU_SPEC_FEATURES, cpu_spec, cpu_features);
0325     OFFSET(CPU_SPEC_SETUP, cpu_spec, cpu_setup);
0326     OFFSET(CPU_SPEC_RESTORE, cpu_spec, cpu_restore);
0327 
0328     OFFSET(pbe_address, pbe, address);
0329     OFFSET(pbe_orig_address, pbe, orig_address);
0330     OFFSET(pbe_next, pbe, next);
0331 
0332 #ifndef CONFIG_PPC64
0333     DEFINE(TASK_SIZE, TASK_SIZE);
0334     DEFINE(NUM_USER_SEGMENTS, TASK_SIZE>>28);
0335 #endif /* ! CONFIG_PPC64 */
0336 
0337     /* datapage offsets for use by vdso */
0338     OFFSET(VDSO_DATA_OFFSET, vdso_arch_data, data);
0339     OFFSET(CFG_TB_TICKS_PER_SEC, vdso_arch_data, tb_ticks_per_sec);
0340 #ifdef CONFIG_PPC64
0341     OFFSET(CFG_ICACHE_BLOCKSZ, vdso_arch_data, icache_block_size);
0342     OFFSET(CFG_DCACHE_BLOCKSZ, vdso_arch_data, dcache_block_size);
0343     OFFSET(CFG_ICACHE_LOGBLOCKSZ, vdso_arch_data, icache_log_block_size);
0344     OFFSET(CFG_DCACHE_LOGBLOCKSZ, vdso_arch_data, dcache_log_block_size);
0345     OFFSET(CFG_SYSCALL_MAP64, vdso_arch_data, syscall_map);
0346     OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, compat_syscall_map);
0347 #else
0348     OFFSET(CFG_SYSCALL_MAP32, vdso_arch_data, syscall_map);
0349 #endif
0350 
0351 #ifdef CONFIG_BUG
0352     DEFINE(BUG_ENTRY_SIZE, sizeof(struct bug_entry));
0353 #endif
0354 
0355 #ifdef CONFIG_KVM
0356     OFFSET(VCPU_HOST_STACK, kvm_vcpu, arch.host_stack);
0357     OFFSET(VCPU_HOST_PID, kvm_vcpu, arch.host_pid);
0358     OFFSET(VCPU_GUEST_PID, kvm_vcpu, arch.pid);
0359     OFFSET(VCPU_GPRS, kvm_vcpu, arch.regs.gpr);
0360     OFFSET(VCPU_VRSAVE, kvm_vcpu, arch.vrsave);
0361     OFFSET(VCPU_FPRS, kvm_vcpu, arch.fp.fpr);
0362 #ifdef CONFIG_ALTIVEC
0363     OFFSET(VCPU_VRS, kvm_vcpu, arch.vr.vr);
0364 #endif
0365     OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
0366     OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
0367     OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
0368 #ifdef CONFIG_PPC_BOOK3S
0369     OFFSET(VCPU_TAR, kvm_vcpu, arch.tar);
0370 #endif
0371     OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
0372     OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
0373 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
0374     OFFSET(VCPU_MSR, kvm_vcpu, arch.shregs.msr);
0375     OFFSET(VCPU_SRR0, kvm_vcpu, arch.shregs.srr0);
0376     OFFSET(VCPU_SRR1, kvm_vcpu, arch.shregs.srr1);
0377     OFFSET(VCPU_SPRG0, kvm_vcpu, arch.shregs.sprg0);
0378     OFFSET(VCPU_SPRG1, kvm_vcpu, arch.shregs.sprg1);
0379     OFFSET(VCPU_SPRG2, kvm_vcpu, arch.shregs.sprg2);
0380     OFFSET(VCPU_SPRG3, kvm_vcpu, arch.shregs.sprg3);
0381 #endif
0382 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
0383     OFFSET(VCPU_TB_RMENTRY, kvm_vcpu, arch.rm_entry);
0384     OFFSET(VCPU_TB_RMINTR, kvm_vcpu, arch.rm_intr);
0385     OFFSET(VCPU_TB_RMEXIT, kvm_vcpu, arch.rm_exit);
0386     OFFSET(VCPU_TB_GUEST, kvm_vcpu, arch.guest_time);
0387     OFFSET(VCPU_TB_CEDE, kvm_vcpu, arch.cede_time);
0388     OFFSET(VCPU_CUR_ACTIVITY, kvm_vcpu, arch.cur_activity);
0389     OFFSET(VCPU_ACTIVITY_START, kvm_vcpu, arch.cur_tb_start);
0390     OFFSET(TAS_SEQCOUNT, kvmhv_tb_accumulator, seqcount);
0391     OFFSET(TAS_TOTAL, kvmhv_tb_accumulator, tb_total);
0392     OFFSET(TAS_MIN, kvmhv_tb_accumulator, tb_min);
0393     OFFSET(TAS_MAX, kvmhv_tb_accumulator, tb_max);
0394 #endif
0395     OFFSET(VCPU_SHARED_SPRG3, kvm_vcpu_arch_shared, sprg3);
0396     OFFSET(VCPU_SHARED_SPRG4, kvm_vcpu_arch_shared, sprg4);
0397     OFFSET(VCPU_SHARED_SPRG5, kvm_vcpu_arch_shared, sprg5);
0398     OFFSET(VCPU_SHARED_SPRG6, kvm_vcpu_arch_shared, sprg6);
0399     OFFSET(VCPU_SHARED_SPRG7, kvm_vcpu_arch_shared, sprg7);
0400     OFFSET(VCPU_SHADOW_PID, kvm_vcpu, arch.shadow_pid);
0401     OFFSET(VCPU_SHADOW_PID1, kvm_vcpu, arch.shadow_pid1);
0402     OFFSET(VCPU_SHARED, kvm_vcpu, arch.shared);
0403     OFFSET(VCPU_SHARED_MSR, kvm_vcpu_arch_shared, msr);
0404     OFFSET(VCPU_SHADOW_MSR, kvm_vcpu, arch.shadow_msr);
0405 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_KVM_BOOK3S_PR_POSSIBLE)
0406     OFFSET(VCPU_SHAREDBE, kvm_vcpu, arch.shared_big_endian);
0407 #endif
0408 
0409     OFFSET(VCPU_SHARED_MAS0, kvm_vcpu_arch_shared, mas0);
0410     OFFSET(VCPU_SHARED_MAS1, kvm_vcpu_arch_shared, mas1);
0411     OFFSET(VCPU_SHARED_MAS2, kvm_vcpu_arch_shared, mas2);
0412     OFFSET(VCPU_SHARED_MAS7_3, kvm_vcpu_arch_shared, mas7_3);
0413     OFFSET(VCPU_SHARED_MAS4, kvm_vcpu_arch_shared, mas4);
0414     OFFSET(VCPU_SHARED_MAS6, kvm_vcpu_arch_shared, mas6);
0415 
0416     OFFSET(VCPU_KVM, kvm_vcpu, kvm);
0417     OFFSET(KVM_LPID, kvm, arch.lpid);
0418 
0419     /* book3s */
0420 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
0421     OFFSET(KVM_TLB_SETS, kvm, arch.tlb_sets);
0422     OFFSET(KVM_SDR1, kvm, arch.sdr1);
0423     OFFSET(KVM_HOST_LPID, kvm, arch.host_lpid);
0424     OFFSET(KVM_HOST_LPCR, kvm, arch.host_lpcr);
0425     OFFSET(KVM_HOST_SDR1, kvm, arch.host_sdr1);
0426     OFFSET(KVM_ENABLED_HCALLS, kvm, arch.enabled_hcalls);
0427     OFFSET(KVM_VRMA_SLB_V, kvm, arch.vrma_slb_v);
0428     OFFSET(KVM_RADIX, kvm, arch.radix);
0429     OFFSET(KVM_SECURE_GUEST, kvm, arch.secure_guest);
0430     OFFSET(VCPU_DSISR, kvm_vcpu, arch.shregs.dsisr);
0431     OFFSET(VCPU_DAR, kvm_vcpu, arch.shregs.dar);
0432     OFFSET(VCPU_VPA, kvm_vcpu, arch.vpa.pinned_addr);
0433     OFFSET(VCPU_VPA_DIRTY, kvm_vcpu, arch.vpa.dirty);
0434     OFFSET(VCPU_HEIR, kvm_vcpu, arch.emul_inst);
0435     OFFSET(VCPU_NESTED, kvm_vcpu, arch.nested);
0436     OFFSET(VCPU_CPU, kvm_vcpu, cpu);
0437     OFFSET(VCPU_THREAD_CPU, kvm_vcpu, arch.thread_cpu);
0438 #endif
0439 #ifdef CONFIG_PPC_BOOK3S
0440     OFFSET(VCPU_PURR, kvm_vcpu, arch.purr);
0441     OFFSET(VCPU_SPURR, kvm_vcpu, arch.spurr);
0442     OFFSET(VCPU_IC, kvm_vcpu, arch.ic);
0443     OFFSET(VCPU_DSCR, kvm_vcpu, arch.dscr);
0444     OFFSET(VCPU_AMR, kvm_vcpu, arch.amr);
0445     OFFSET(VCPU_UAMOR, kvm_vcpu, arch.uamor);
0446     OFFSET(VCPU_IAMR, kvm_vcpu, arch.iamr);
0447     OFFSET(VCPU_CTRL, kvm_vcpu, arch.ctrl);
0448     OFFSET(VCPU_DABR, kvm_vcpu, arch.dabr);
0449     OFFSET(VCPU_DABRX, kvm_vcpu, arch.dabrx);
0450     OFFSET(VCPU_DAWR0, kvm_vcpu, arch.dawr0);
0451     OFFSET(VCPU_DAWRX0, kvm_vcpu, arch.dawrx0);
0452     OFFSET(VCPU_DAWR1, kvm_vcpu, arch.dawr1);
0453     OFFSET(VCPU_DAWRX1, kvm_vcpu, arch.dawrx1);
0454     OFFSET(VCPU_CIABR, kvm_vcpu, arch.ciabr);
0455     OFFSET(VCPU_HFLAGS, kvm_vcpu, arch.hflags);
0456     OFFSET(VCPU_DEC_EXPIRES, kvm_vcpu, arch.dec_expires);
0457     OFFSET(VCPU_PENDING_EXC, kvm_vcpu, arch.pending_exceptions);
0458     OFFSET(VCPU_CEDED, kvm_vcpu, arch.ceded);
0459     OFFSET(VCPU_PRODDED, kvm_vcpu, arch.prodded);
0460     OFFSET(VCPU_IRQ_PENDING, kvm_vcpu, arch.irq_pending);
0461     OFFSET(VCPU_DBELL_REQ, kvm_vcpu, arch.doorbell_request);
0462     OFFSET(VCPU_MMCR, kvm_vcpu, arch.mmcr);
0463     OFFSET(VCPU_MMCRA, kvm_vcpu, arch.mmcra);
0464     OFFSET(VCPU_MMCRS, kvm_vcpu, arch.mmcrs);
0465     OFFSET(VCPU_PMC, kvm_vcpu, arch.pmc);
0466     OFFSET(VCPU_SIAR, kvm_vcpu, arch.siar);
0467     OFFSET(VCPU_SDAR, kvm_vcpu, arch.sdar);
0468     OFFSET(VCPU_SIER, kvm_vcpu, arch.sier);
0469     OFFSET(VCPU_SLB, kvm_vcpu, arch.slb);
0470     OFFSET(VCPU_SLB_MAX, kvm_vcpu, arch.slb_max);
0471     OFFSET(VCPU_SLB_NR, kvm_vcpu, arch.slb_nr);
0472     OFFSET(VCPU_FAULT_DSISR, kvm_vcpu, arch.fault_dsisr);
0473     OFFSET(VCPU_FAULT_DAR, kvm_vcpu, arch.fault_dar);
0474     OFFSET(VCPU_INTR_MSR, kvm_vcpu, arch.intr_msr);
0475     OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
0476     OFFSET(VCPU_TRAP, kvm_vcpu, arch.trap);
0477     OFFSET(VCPU_CFAR, kvm_vcpu, arch.cfar);
0478     OFFSET(VCPU_PPR, kvm_vcpu, arch.ppr);
0479     OFFSET(VCPU_FSCR, kvm_vcpu, arch.fscr);
0480     OFFSET(VCPU_PSPB, kvm_vcpu, arch.pspb);
0481     OFFSET(VCPU_EBBHR, kvm_vcpu, arch.ebbhr);
0482     OFFSET(VCPU_EBBRR, kvm_vcpu, arch.ebbrr);
0483     OFFSET(VCPU_BESCR, kvm_vcpu, arch.bescr);
0484     OFFSET(VCPU_CSIGR, kvm_vcpu, arch.csigr);
0485     OFFSET(VCPU_TACR, kvm_vcpu, arch.tacr);
0486     OFFSET(VCPU_TCSCR, kvm_vcpu, arch.tcscr);
0487     OFFSET(VCPU_ACOP, kvm_vcpu, arch.acop);
0488     OFFSET(VCPU_WORT, kvm_vcpu, arch.wort);
0489     OFFSET(VCPU_TID, kvm_vcpu, arch.tid);
0490     OFFSET(VCPU_PSSCR, kvm_vcpu, arch.psscr);
0491     OFFSET(VCPU_HFSCR, kvm_vcpu, arch.hfscr);
0492     OFFSET(VCORE_ENTRY_EXIT, kvmppc_vcore, entry_exit_map);
0493     OFFSET(VCORE_IN_GUEST, kvmppc_vcore, in_guest);
0494     OFFSET(VCORE_NAPPING_THREADS, kvmppc_vcore, napping_threads);
0495     OFFSET(VCORE_KVM, kvmppc_vcore, kvm);
0496     OFFSET(VCORE_TB_OFFSET, kvmppc_vcore, tb_offset);
0497     OFFSET(VCORE_TB_OFFSET_APPL, kvmppc_vcore, tb_offset_applied);
0498     OFFSET(VCORE_LPCR, kvmppc_vcore, lpcr);
0499     OFFSET(VCORE_PCR, kvmppc_vcore, pcr);
0500     OFFSET(VCORE_DPDES, kvmppc_vcore, dpdes);
0501     OFFSET(VCORE_VTB, kvmppc_vcore, vtb);
0502     OFFSET(VCPU_SLB_E, kvmppc_slb, orige);
0503     OFFSET(VCPU_SLB_V, kvmppc_slb, origv);
0504     DEFINE(VCPU_SLB_SIZE, sizeof(struct kvmppc_slb));
0505 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
0506     OFFSET(VCPU_TFHAR, kvm_vcpu, arch.tfhar);
0507     OFFSET(VCPU_TFIAR, kvm_vcpu, arch.tfiar);
0508     OFFSET(VCPU_TEXASR, kvm_vcpu, arch.texasr);
0509     OFFSET(VCPU_ORIG_TEXASR, kvm_vcpu, arch.orig_texasr);
0510     OFFSET(VCPU_GPR_TM, kvm_vcpu, arch.gpr_tm);
0511     OFFSET(VCPU_FPRS_TM, kvm_vcpu, arch.fp_tm.fpr);
0512     OFFSET(VCPU_VRS_TM, kvm_vcpu, arch.vr_tm.vr);
0513     OFFSET(VCPU_VRSAVE_TM, kvm_vcpu, arch.vrsave_tm);
0514     OFFSET(VCPU_CR_TM, kvm_vcpu, arch.cr_tm);
0515     OFFSET(VCPU_XER_TM, kvm_vcpu, arch.xer_tm);
0516     OFFSET(VCPU_LR_TM, kvm_vcpu, arch.lr_tm);
0517     OFFSET(VCPU_CTR_TM, kvm_vcpu, arch.ctr_tm);
0518     OFFSET(VCPU_AMR_TM, kvm_vcpu, arch.amr_tm);
0519     OFFSET(VCPU_PPR_TM, kvm_vcpu, arch.ppr_tm);
0520     OFFSET(VCPU_DSCR_TM, kvm_vcpu, arch.dscr_tm);
0521     OFFSET(VCPU_TAR_TM, kvm_vcpu, arch.tar_tm);
0522 #endif
0523 
0524 #ifdef CONFIG_PPC_BOOK3S_64
0525 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
0526     OFFSET(PACA_SVCPU, paca_struct, shadow_vcpu);
0527 # define SVCPU_FIELD(x, f)  DEFINE(x, offsetof(struct paca_struct, shadow_vcpu.f))
0528 #else
0529 # define SVCPU_FIELD(x, f)
0530 #endif
0531 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct paca_struct, kvm_hstate.f))
0532 #else   /* 32-bit */
0533 # define SVCPU_FIELD(x, f)  DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, f))
0534 # define HSTATE_FIELD(x, f) DEFINE(x, offsetof(struct kvmppc_book3s_shadow_vcpu, hstate.f))
0535 #endif
0536 
0537     SVCPU_FIELD(SVCPU_CR, cr);
0538     SVCPU_FIELD(SVCPU_XER, xer);
0539     SVCPU_FIELD(SVCPU_CTR, ctr);
0540     SVCPU_FIELD(SVCPU_LR, lr);
0541     SVCPU_FIELD(SVCPU_PC, pc);
0542     SVCPU_FIELD(SVCPU_R0, gpr[0]);
0543     SVCPU_FIELD(SVCPU_R1, gpr[1]);
0544     SVCPU_FIELD(SVCPU_R2, gpr[2]);
0545     SVCPU_FIELD(SVCPU_R3, gpr[3]);
0546     SVCPU_FIELD(SVCPU_R4, gpr[4]);
0547     SVCPU_FIELD(SVCPU_R5, gpr[5]);
0548     SVCPU_FIELD(SVCPU_R6, gpr[6]);
0549     SVCPU_FIELD(SVCPU_R7, gpr[7]);
0550     SVCPU_FIELD(SVCPU_R8, gpr[8]);
0551     SVCPU_FIELD(SVCPU_R9, gpr[9]);
0552     SVCPU_FIELD(SVCPU_R10, gpr[10]);
0553     SVCPU_FIELD(SVCPU_R11, gpr[11]);
0554     SVCPU_FIELD(SVCPU_R12, gpr[12]);
0555     SVCPU_FIELD(SVCPU_R13, gpr[13]);
0556     SVCPU_FIELD(SVCPU_FAULT_DSISR, fault_dsisr);
0557     SVCPU_FIELD(SVCPU_FAULT_DAR, fault_dar);
0558     SVCPU_FIELD(SVCPU_LAST_INST, last_inst);
0559     SVCPU_FIELD(SVCPU_SHADOW_SRR1, shadow_srr1);
0560 #ifdef CONFIG_PPC_BOOK3S_32
0561     SVCPU_FIELD(SVCPU_SR, sr);
0562 #endif
0563 #ifdef CONFIG_PPC64
0564     SVCPU_FIELD(SVCPU_SLB, slb);
0565     SVCPU_FIELD(SVCPU_SLB_MAX, slb_max);
0566     SVCPU_FIELD(SVCPU_SHADOW_FSCR, shadow_fscr);
0567 #endif
0568 
0569     HSTATE_FIELD(HSTATE_HOST_R1, host_r1);
0570     HSTATE_FIELD(HSTATE_HOST_R2, host_r2);
0571     HSTATE_FIELD(HSTATE_HOST_MSR, host_msr);
0572     HSTATE_FIELD(HSTATE_VMHANDLER, vmhandler);
0573     HSTATE_FIELD(HSTATE_SCRATCH0, scratch0);
0574     HSTATE_FIELD(HSTATE_SCRATCH1, scratch1);
0575     HSTATE_FIELD(HSTATE_SCRATCH2, scratch2);
0576     HSTATE_FIELD(HSTATE_IN_GUEST, in_guest);
0577     HSTATE_FIELD(HSTATE_RESTORE_HID5, restore_hid5);
0578     HSTATE_FIELD(HSTATE_NAPPING, napping);
0579 
0580 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
0581     HSTATE_FIELD(HSTATE_HWTHREAD_REQ, hwthread_req);
0582     HSTATE_FIELD(HSTATE_HWTHREAD_STATE, hwthread_state);
0583     HSTATE_FIELD(HSTATE_KVM_VCPU, kvm_vcpu);
0584     HSTATE_FIELD(HSTATE_KVM_VCORE, kvm_vcore);
0585     HSTATE_FIELD(HSTATE_XIVE_TIMA_PHYS, xive_tima_phys);
0586     HSTATE_FIELD(HSTATE_XIVE_TIMA_VIRT, xive_tima_virt);
0587     HSTATE_FIELD(HSTATE_HOST_IPI, host_ipi);
0588     HSTATE_FIELD(HSTATE_PTID, ptid);
0589     HSTATE_FIELD(HSTATE_FAKE_SUSPEND, fake_suspend);
0590     HSTATE_FIELD(HSTATE_MMCR0, host_mmcr[0]);
0591     HSTATE_FIELD(HSTATE_MMCR1, host_mmcr[1]);
0592     HSTATE_FIELD(HSTATE_MMCRA, host_mmcr[2]);
0593     HSTATE_FIELD(HSTATE_SIAR, host_mmcr[3]);
0594     HSTATE_FIELD(HSTATE_SDAR, host_mmcr[4]);
0595     HSTATE_FIELD(HSTATE_MMCR2, host_mmcr[5]);
0596     HSTATE_FIELD(HSTATE_SIER, host_mmcr[6]);
0597     HSTATE_FIELD(HSTATE_MMCR3, host_mmcr[7]);
0598     HSTATE_FIELD(HSTATE_SIER2, host_mmcr[8]);
0599     HSTATE_FIELD(HSTATE_SIER3, host_mmcr[9]);
0600     HSTATE_FIELD(HSTATE_PMC1, host_pmc[0]);
0601     HSTATE_FIELD(HSTATE_PMC2, host_pmc[1]);
0602     HSTATE_FIELD(HSTATE_PMC3, host_pmc[2]);
0603     HSTATE_FIELD(HSTATE_PMC4, host_pmc[3]);
0604     HSTATE_FIELD(HSTATE_PMC5, host_pmc[4]);
0605     HSTATE_FIELD(HSTATE_PMC6, host_pmc[5]);
0606     HSTATE_FIELD(HSTATE_PURR, host_purr);
0607     HSTATE_FIELD(HSTATE_SPURR, host_spurr);
0608     HSTATE_FIELD(HSTATE_DSCR, host_dscr);
0609     HSTATE_FIELD(HSTATE_DABR, dabr);
0610     HSTATE_FIELD(HSTATE_DECEXP, dec_expires);
0611     HSTATE_FIELD(HSTATE_SPLIT_MODE, kvm_split_mode);
0612     DEFINE(IPI_PRIORITY, IPI_PRIORITY);
0613     OFFSET(KVM_SPLIT_RPR, kvm_split_mode, rpr);
0614     OFFSET(KVM_SPLIT_PMMAR, kvm_split_mode, pmmar);
0615     OFFSET(KVM_SPLIT_LDBAR, kvm_split_mode, ldbar);
0616     OFFSET(KVM_SPLIT_DO_NAP, kvm_split_mode, do_nap);
0617     OFFSET(KVM_SPLIT_NAPPED, kvm_split_mode, napped);
0618 #endif /* CONFIG_KVM_BOOK3S_HV_POSSIBLE */
0619 
0620 #ifdef CONFIG_PPC_BOOK3S_64
0621     HSTATE_FIELD(HSTATE_CFAR, cfar);
0622     HSTATE_FIELD(HSTATE_PPR, ppr);
0623     HSTATE_FIELD(HSTATE_HOST_FSCR, host_fscr);
0624 #endif /* CONFIG_PPC_BOOK3S_64 */
0625 
0626 #else /* CONFIG_PPC_BOOK3S */
0627     OFFSET(VCPU_CR, kvm_vcpu, arch.regs.ccr);
0628     OFFSET(VCPU_XER, kvm_vcpu, arch.regs.xer);
0629     OFFSET(VCPU_LR, kvm_vcpu, arch.regs.link);
0630     OFFSET(VCPU_CTR, kvm_vcpu, arch.regs.ctr);
0631     OFFSET(VCPU_PC, kvm_vcpu, arch.regs.nip);
0632     OFFSET(VCPU_SPRG9, kvm_vcpu, arch.sprg9);
0633     OFFSET(VCPU_LAST_INST, kvm_vcpu, arch.last_inst);
0634     OFFSET(VCPU_FAULT_DEAR, kvm_vcpu, arch.fault_dear);
0635     OFFSET(VCPU_FAULT_ESR, kvm_vcpu, arch.fault_esr);
0636     OFFSET(VCPU_CRIT_SAVE, kvm_vcpu, arch.crit_save);
0637 #endif /* CONFIG_PPC_BOOK3S */
0638 #endif /* CONFIG_KVM */
0639 
0640 #ifdef CONFIG_KVM_GUEST
0641     OFFSET(KVM_MAGIC_SCRATCH1, kvm_vcpu_arch_shared, scratch1);
0642     OFFSET(KVM_MAGIC_SCRATCH2, kvm_vcpu_arch_shared, scratch2);
0643     OFFSET(KVM_MAGIC_SCRATCH3, kvm_vcpu_arch_shared, scratch3);
0644     OFFSET(KVM_MAGIC_INT, kvm_vcpu_arch_shared, int_pending);
0645     OFFSET(KVM_MAGIC_MSR, kvm_vcpu_arch_shared, msr);
0646     OFFSET(KVM_MAGIC_CRITICAL, kvm_vcpu_arch_shared, critical);
0647     OFFSET(KVM_MAGIC_SR, kvm_vcpu_arch_shared, sr);
0648 #endif
0649 
0650 #ifdef CONFIG_44x
0651     DEFINE(PGD_T_LOG2, PGD_T_LOG2);
0652     DEFINE(PTE_T_LOG2, PTE_T_LOG2);
0653 #endif
0654 #ifdef CONFIG_PPC_FSL_BOOK3E
0655     DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
0656     OFFSET(TLBCAM_MAS0, tlbcam, MAS0);
0657     OFFSET(TLBCAM_MAS1, tlbcam, MAS1);
0658     OFFSET(TLBCAM_MAS2, tlbcam, MAS2);
0659     OFFSET(TLBCAM_MAS3, tlbcam, MAS3);
0660     OFFSET(TLBCAM_MAS7, tlbcam, MAS7);
0661 #endif
0662 
0663 #if defined(CONFIG_KVM) && defined(CONFIG_SPE)
0664     OFFSET(VCPU_EVR, kvm_vcpu, arch.evr[0]);
0665     OFFSET(VCPU_ACC, kvm_vcpu, arch.acc);
0666     OFFSET(VCPU_SPEFSCR, kvm_vcpu, arch.spefscr);
0667     OFFSET(VCPU_HOST_SPEFSCR, kvm_vcpu, arch.host_spefscr);
0668 #endif
0669 
0670 #ifdef CONFIG_KVM_BOOKE_HV
0671     OFFSET(VCPU_HOST_MAS4, kvm_vcpu, arch.host_mas4);
0672     OFFSET(VCPU_HOST_MAS6, kvm_vcpu, arch.host_mas6);
0673 #endif
0674 
0675 #ifdef CONFIG_KVM_XICS
0676     DEFINE(VCPU_XIVE_SAVED_STATE, offsetof(struct kvm_vcpu,
0677                            arch.xive_saved_state));
0678     DEFINE(VCPU_XIVE_CAM_WORD, offsetof(struct kvm_vcpu,
0679                         arch.xive_cam_word));
0680     DEFINE(VCPU_XIVE_PUSHED, offsetof(struct kvm_vcpu, arch.xive_pushed));
0681     DEFINE(VCPU_XIVE_ESC_ON, offsetof(struct kvm_vcpu, arch.xive_esc_on));
0682     DEFINE(VCPU_XIVE_ESC_RADDR, offsetof(struct kvm_vcpu, arch.xive_esc_raddr));
0683     DEFINE(VCPU_XIVE_ESC_VADDR, offsetof(struct kvm_vcpu, arch.xive_esc_vaddr));
0684 #endif
0685 
0686 #ifdef CONFIG_KVM_EXIT_TIMING
0687     OFFSET(VCPU_TIMING_EXIT_TBU, kvm_vcpu, arch.timing_exit.tv32.tbu);
0688     OFFSET(VCPU_TIMING_EXIT_TBL, kvm_vcpu, arch.timing_exit.tv32.tbl);
0689     OFFSET(VCPU_TIMING_LAST_ENTER_TBU, kvm_vcpu, arch.timing_last_enter.tv32.tbu);
0690     OFFSET(VCPU_TIMING_LAST_ENTER_TBL, kvm_vcpu, arch.timing_last_enter.tv32.tbl);
0691 #endif
0692 
0693     DEFINE(PPC_DBELL_SERVER, PPC_DBELL_SERVER);
0694 
0695 #ifdef CONFIG_PPC_8xx
0696     DEFINE(VIRT_IMMR_BASE, (u64)__fix_to_virt(FIX_IMMR_BASE));
0697 #endif
0698 
0699 #ifdef CONFIG_XMON
0700     DEFINE(BPT_SIZE, BPT_SIZE);
0701 #endif
0702 
0703     return 0;
0704 }
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