uapi/asm/ptrace.h

0001 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
0002 /*
0003  * Copyright (C) 2001 PPC64 Team, IBM Corp
0004  *
0005  * This struct defines the way the registers are stored on the
0006  * kernel stack during a system call or other kernel entry.
0007  *
0008  * this should only contain volatile regs
0009  * since we can keep non-volatile in the thread_struct
0010  * should set this up when only volatiles are saved
0011  * by intr code.
0012  *
0013  * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
0014  * that the overall structure is a multiple of 16 bytes in length.
0015  *
0016  * Note that the offsets of the fields in this struct correspond with
0017  * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
0018  *
0019  * This program is free software; you can redistribute it and/or
0020  * modify it under the terms of the GNU General Public License
0021  * as published by the Free Software Foundation; either version
0022  * 2 of the License, or (at your option) any later version.
0023  */
0024 #ifndef _UAPI_ASM_POWERPC_PTRACE_H
0025 #define _UAPI_ASM_POWERPC_PTRACE_H
0026
0027
0028 #include <linux/types.h>
0029
0030 #ifndef __ASSEMBLY__
0031
0032 #ifdef __KERNEL__
0033 struct user_pt_regs
0034 #else
0035 struct pt_regs
0036 #endif
0037 {
0038     unsigned long gpr[32];
0039     unsigned long nip;
0040     unsigned long msr;
0041     unsigned long orig_gpr3;    /* Used for restarting system calls */
0042     unsigned long ctr;
0043     unsigned long link;
0044     unsigned long xer;
0045     unsigned long ccr;
0046 #ifdef __powerpc64__
0047     unsigned long softe;        /* Soft enabled/disabled */
0048 #else
0049     unsigned long mq;       /* 601 only (not used at present) */
0050                     /* Used on APUS to hold IPL value. */
0051 #endif
0052     unsigned long trap;     /* Reason for being here */
0053     /* N.B. for critical exceptions on 4xx, the dar and dsisr
0054        fields are overloaded to hold srr0 and srr1. */
0055     unsigned long dar;      /* Fault registers */
0056     unsigned long dsisr;        /* on 4xx/Book-E used for ESR */
0057     unsigned long result;       /* Result of a system call */
0058 };
0059
0060 #endif /* __ASSEMBLY__ */
0061
0062
0063 /*
0064  * Offsets used by 'ptrace' system call interface.
0065  * These can't be changed without breaking binary compatibility
0066  * with MkLinux, etc.
0067  */
0068 #define PT_R0   0
0069 #define PT_R1   1
0070 #define PT_R2   2
0071 #define PT_R3   3
0072 #define PT_R4   4
0073 #define PT_R5   5
0074 #define PT_R6   6
0075 #define PT_R7   7
0076 #define PT_R8   8
0077 #define PT_R9   9
0078 #define PT_R10  10
0079 #define PT_R11  11
0080 #define PT_R12  12
0081 #define PT_R13  13
0082 #define PT_R14  14
0083 #define PT_R15  15
0084 #define PT_R16  16
0085 #define PT_R17  17
0086 #define PT_R18  18
0087 #define PT_R19  19
0088 #define PT_R20  20
0089 #define PT_R21  21
0090 #define PT_R22  22
0091 #define PT_R23  23
0092 #define PT_R24  24
0093 #define PT_R25  25
0094 #define PT_R26  26
0095 #define PT_R27  27
0096 #define PT_R28  28
0097 #define PT_R29  29
0098 #define PT_R30  30
0099 #define PT_R31  31
0100
0101 #define PT_NIP  32
0102 #define PT_MSR  33
0103 #define PT_ORIG_R3 34
0104 #define PT_CTR  35
0105 #define PT_LNK  36
0106 #define PT_XER  37
0107 #define PT_CCR  38
0108 #ifndef __powerpc64__
0109 #define PT_MQ   39
0110 #else
0111 #define PT_SOFTE 39
0112 #endif
0113 #define PT_TRAP 40
0114 #define PT_DAR  41
0115 #define PT_DSISR 42
0116 #define PT_RESULT 43
0117 #define PT_DSCR 44
0118 #define PT_REGS_COUNT 44
0119
0120 #define PT_FPR0 48  /* each FP reg occupies 2 slots in this space */
0121
0122 #ifndef __powerpc64__
0123
0124 #define PT_FPR31 (PT_FPR0 + 2*31)
0125 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
0126
0127 #else /* __powerpc64__ */
0128
0129 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
0130
0131
0132 #define PT_VR0 82   /* each Vector reg occupies 2 slots in 64-bit */
0133 #define PT_VSCR (PT_VR0 + 32*2 + 1)
0134 #define PT_VRSAVE (PT_VR0 + 33*2)
0135
0136
0137 /*
0138  * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
0139  */
0140 #define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
0141 #define PT_VSR31 (PT_VSR0 + 2*31)
0142 #endif /* __powerpc64__ */
0143
0144 /*
0145  * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
0146  * The transfer totals 34 quadword.  Quadwords 0-31 contain the
0147  * corresponding vector registers.  Quadword 32 contains the vscr as the
0148  * last word (offset 12) within that quadword.  Quadword 33 contains the
0149  * vrsave as the first word (offset 0) within the quadword.
0150  *
0151  * This definition of the VMX state is compatible with the current PPC32
0152  * ptrace interface.  This allows signal handling and ptrace to use the same
0153  * structures.  This also simplifies the implementation of a bi-arch
0154  * (combined (32- and 64-bit) gdb.
0155  */
0156 #define PTRACE_GETVRREGS    0x12
0157 #define PTRACE_SETVRREGS    0x13
0158
0159 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and
0160  * spefscr, in one go */
0161 #define PTRACE_GETEVRREGS   0x14
0162 #define PTRACE_SETEVRREGS   0x15
0163
0164 /* Get the first 32 128bit VSX registers */
0165 #define PTRACE_GETVSRREGS   0x1b
0166 #define PTRACE_SETVSRREGS   0x1c
0167
0168 /* Syscall emulation defines */
0169 #define PTRACE_SYSEMU           0x1d
0170 #define PTRACE_SYSEMU_SINGLESTEP    0x1e
0171
0172 /*
0173  * Get or set a debug register. The first 16 are DABR registers and the
0174  * second 16 are IABR registers.
0175  */
0176 #define PTRACE_GET_DEBUGREG 0x19
0177 #define PTRACE_SET_DEBUGREG 0x1a
0178
0179 /* (new) PTRACE requests using the same numbers as x86 and the same
0180  * argument ordering. Additionally, they support more registers too
0181  */
0182 #define PTRACE_GETREGS            0xc
0183 #define PTRACE_SETREGS            0xd
0184 #define PTRACE_GETFPREGS          0xe
0185 #define PTRACE_SETFPREGS          0xf
0186 #define PTRACE_GETREGS64      0x16
0187 #define PTRACE_SETREGS64      0x17
0188
0189 /* Calls to trace a 64bit program from a 32bit program */
0190 #define PPC_PTRACE_PEEKTEXT_3264 0x95
0191 #define PPC_PTRACE_PEEKDATA_3264 0x94
0192 #define PPC_PTRACE_POKETEXT_3264 0x93
0193 #define PPC_PTRACE_POKEDATA_3264 0x92
0194 #define PPC_PTRACE_PEEKUSR_3264  0x91
0195 #define PPC_PTRACE_POKEUSR_3264  0x90
0196
0197 #define PTRACE_SINGLEBLOCK  0x100   /* resume execution until next branch */
0198
0199 #define PPC_PTRACE_GETHWDBGINFO 0x89
0200 #define PPC_PTRACE_SETHWDEBUG   0x88
0201 #define PPC_PTRACE_DELHWDEBUG   0x87
0202
0203 #ifndef __ASSEMBLY__
0204
0205 struct ppc_debug_info {
0206     __u32 version;          /* Only version 1 exists to date */
0207     __u32 num_instruction_bps;
0208     __u32 num_data_bps;
0209     __u32 num_condition_regs;
0210     __u32 data_bp_alignment;
0211     __u32 sizeof_condition;     /* size of the DVC register */
0212     __u64 features;
0213 };
0214
0215 #endif /* __ASSEMBLY__ */
0216
0217 /*
0218  * features will have bits indication whether there is support for:
0219  */
0220 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE     0x0000000000000001
0221 #define PPC_DEBUG_FEATURE_INSN_BP_MASK      0x0000000000000002
0222 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE     0x0000000000000004
0223 #define PPC_DEBUG_FEATURE_DATA_BP_MASK      0x0000000000000008
0224 #define PPC_DEBUG_FEATURE_DATA_BP_DAWR      0x0000000000000010
0225 #define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31   0x0000000000000020
0226
0227 #ifndef __ASSEMBLY__
0228
0229 struct ppc_hw_breakpoint {
0230     __u32 version;      /* currently, version must be 1 */
0231     __u32 trigger_type; /* only some combinations allowed */
0232     __u32 addr_mode;    /* address match mode */
0233     __u32 condition_mode;   /* break/watchpoint condition flags */
0234     __u64 addr;     /* break/watchpoint address */
0235     __u64 addr2;        /* range end or mask */
0236     __u64 condition_value;  /* contents of the DVC register */
0237 };
0238
0239 #endif /* __ASSEMBLY__ */
0240
0241 /*
0242  * Trigger Type
0243  */
0244 #define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x00000001
0245 #define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
0246 #define PPC_BREAKPOINT_TRIGGER_WRITE    0x00000004
0247 #define PPC_BREAKPOINT_TRIGGER_RW   \
0248     (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
0249
0250 /*
0251  * Address Mode
0252  */
0253 #define PPC_BREAKPOINT_MODE_EXACT       0x00000000
0254 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
0255 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
0256 #define PPC_BREAKPOINT_MODE_MASK        0x00000003
0257
0258 /*
0259  * Condition Mode
0260  */
0261 #define PPC_BREAKPOINT_CONDITION_MODE   0x00000003
0262 #define PPC_BREAKPOINT_CONDITION_NONE   0x00000000
0263 #define PPC_BREAKPOINT_CONDITION_AND    0x00000001
0264 #define PPC_BREAKPOINT_CONDITION_EXACT  PPC_BREAKPOINT_CONDITION_AND
0265 #define PPC_BREAKPOINT_CONDITION_OR 0x00000002
0266 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
0267 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
0268 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT   16
0269 #define PPC_BREAKPOINT_CONDITION_BE(n)  \
0270     (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
0271
0272 #endif /* _UAPI_ASM_POWERPC_PTRACE_H */