uapi/asm/auxvec.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 #ifndef _ASM_POWERPC_AUXVEC_H
0003 #define _ASM_POWERPC_AUXVEC_H
0004
0005 /*
0006  * We need to put in some extra aux table entries to tell glibc what
0007  * the cache block size is, so it can use the dcbz instruction safely.
0008  */
0009 #define AT_DCACHEBSIZE      19
0010 #define AT_ICACHEBSIZE      20
0011 #define AT_UCACHEBSIZE      21
0012 /* A special ignored type value for PPC, for glibc compatibility.  */
0013 #define AT_IGNOREPPC        22
0014
0015 /* The vDSO location. We have to use the same value as x86 for glibc's
0016  * sake :-)
0017  */
0018 #define AT_SYSINFO_EHDR     33
0019
0020 /*
0021  * AT_*CACHEBSIZE above represent the cache *block* size which is
0022  * the size that is affected by the cache management instructions.
0023  *
0024  * It doesn't nececssarily matches the cache *line* size which is
0025  * more of a performance tuning hint. Additionally the latter can
0026  * be different for the different cache levels.
0027  *
0028  * The set of entries below represent more extensive information
0029  * about the caches, in the form of two entry per cache type,
0030  * one entry containing the cache size in bytes, and the other
0031  * containing the cache line size in bytes in the bottom 16 bits
0032  * and the cache associativity in the next 16 bits.
0033  *
0034  * The associativity is such that if N is the 16-bit value, the
0035  * cache is N way set associative. A value if 0xffff means fully
0036  * associative, a value of 1 means directly mapped.
0037  *
0038  * For all these fields, a value of 0 means that the information
0039  * is not known.
0040  */
0041
0042 #define AT_L1I_CACHESIZE    40
0043 #define AT_L1I_CACHEGEOMETRY    41
0044 #define AT_L1D_CACHESIZE    42
0045 #define AT_L1D_CACHEGEOMETRY    43
0046 #define AT_L2_CACHESIZE     44
0047 #define AT_L2_CACHEGEOMETRY 45
0048 #define AT_L3_CACHESIZE     46
0049 #define AT_L3_CACHEGEOMETRY 47
0050
0051 #define AT_MINSIGSTKSZ      51      /* stack needed for signal delivery */
0052
0053 #define AT_VECTOR_SIZE_ARCH 15 /* entries in ARCH_DLINFO */
0054
0055 #endif