include/asm/xive.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright 2016,2017 IBM Corporation.
0004  */
0005 #ifndef _ASM_POWERPC_XIVE_H
0006 #define _ASM_POWERPC_XIVE_H
0007
0008 #include <asm/opal-api.h>
0009
0010 #define XIVE_INVALID_VP 0xffffffff
0011
0012 #ifdef CONFIG_PPC_XIVE
0013
0014 /*
0015  * Thread Interrupt Management Area (TIMA)
0016  *
0017  * This is a global MMIO region divided in 4 pages of varying access
0018  * permissions, providing access to per-cpu interrupt management
0019  * functions. It always identifies the CPU doing the access based
0020  * on the PowerBus initiator ID, thus we always access via the
0021  * same offset regardless of where the code is executing
0022  */
0023 extern void __iomem *xive_tima;
0024 extern unsigned long xive_tima_os;
0025
0026 /*
0027  * Offset in the TM area of our current execution level (provided by
0028  * the backend)
0029  */
0030 extern u32 xive_tima_offset;
0031
0032 /*
0033  * Per-irq data (irq_get_handler_data for normal IRQs), IPIs
0034  * have it stored in the xive_cpu structure. We also cache
0035  * for normal interrupts the current target CPU.
0036  *
0037  * This structure is setup by the backend for each interrupt.
0038  */
0039 struct xive_irq_data {
0040     u64 flags;
0041     u64 eoi_page;
0042     void __iomem *eoi_mmio;
0043     u64 trig_page;
0044     void __iomem *trig_mmio;
0045     u32 esb_shift;
0046     int src_chip;
0047     u32 hw_irq;
0048
0049     /* Setup/used by frontend */
0050     int target;
0051     /*
0052      * saved_p means that there is a queue entry for this interrupt
0053      * in some CPU's queue (not including guest vcpu queues), even
0054      * if P is not set in the source ESB.
0055      * stale_p means that there is no queue entry for this interrupt
0056      * in some CPU's queue, even if P is set in the source ESB.
0057      */
0058     bool saved_p;
0059     bool stale_p;
0060 };
0061 #define XIVE_IRQ_FLAG_STORE_EOI 0x01
0062 #define XIVE_IRQ_FLAG_LSI   0x02
0063 /* #define XIVE_IRQ_FLAG_SHIFT_BUG  0x04 */ /* P9 DD1.0 workaround */
0064 /* #define XIVE_IRQ_FLAG_MASK_FW    0x08 */ /* P9 DD1.0 workaround */
0065 /* #define XIVE_IRQ_FLAG_EOI_FW 0x10 */ /* P9 DD1.0 workaround */
0066 #define XIVE_IRQ_FLAG_H_INT_ESB 0x20
0067
0068 /* Special flag set by KVM for excalation interrupts */
0069 #define XIVE_IRQ_FLAG_NO_EOI    0x80
0070
0071 #define XIVE_INVALID_CHIP_ID    -1
0072
0073 /* A queue tracking structure in a CPU */
0074 struct xive_q {
0075     __be32          *qpage;
0076     u32         msk;
0077     u32         idx;
0078     u32         toggle;
0079     u64         eoi_phys;
0080     u32         esc_irq;
0081     atomic_t        count;
0082     atomic_t        pending_count;
0083     u64         guest_qaddr;
0084     u32         guest_qshift;
0085 };
0086
0087 /* Global enable flags for the XIVE support */
0088 extern bool __xive_enabled;
0089
0090 static inline bool xive_enabled(void) { return __xive_enabled; }
0091
0092 bool xive_spapr_init(void);
0093 bool xive_native_init(void);
0094 void xive_smp_probe(void);
0095 int  xive_smp_prepare_cpu(unsigned int cpu);
0096 void xive_smp_setup_cpu(void);
0097 void xive_smp_disable_cpu(void);
0098 void xive_teardown_cpu(void);
0099 void xive_shutdown(void);
0100 void xive_flush_interrupt(void);
0101
0102 /* xmon hook */
0103 void xmon_xive_do_dump(int cpu);
0104 int xmon_xive_get_irq_config(u32 hw_irq, struct irq_data *d);
0105 void xmon_xive_get_irq_all(void);
0106
0107 /* APIs used by KVM */
0108 u32 xive_native_default_eq_shift(void);
0109 u32 xive_native_alloc_vp_block(u32 max_vcpus);
0110 void xive_native_free_vp_block(u32 vp_base);
0111 int xive_native_populate_irq_data(u32 hw_irq,
0112                   struct xive_irq_data *data);
0113 void xive_cleanup_irq_data(struct xive_irq_data *xd);
0114 void xive_irq_free_data(unsigned int virq);
0115 void xive_native_free_irq(u32 irq);
0116 int xive_native_configure_irq(u32 hw_irq, u32 target, u8 prio, u32 sw_irq);
0117
0118 int xive_native_configure_queue(u32 vp_id, struct xive_q *q, u8 prio,
0119                 __be32 *qpage, u32 order, bool can_escalate);
0120 void xive_native_disable_queue(u32 vp_id, struct xive_q *q, u8 prio);
0121
0122 void xive_native_sync_source(u32 hw_irq);
0123 void xive_native_sync_queue(u32 hw_irq);
0124 bool is_xive_irq(struct irq_chip *chip);
0125 int xive_native_enable_vp(u32 vp_id, bool single_escalation);
0126 int xive_native_disable_vp(u32 vp_id);
0127 int xive_native_get_vp_info(u32 vp_id, u32 *out_cam_id, u32 *out_chip_id);
0128 bool xive_native_has_single_escalation(void);
0129 bool xive_native_has_save_restore(void);
0130
0131 int xive_native_get_queue_info(u32 vp_id, uint32_t prio,
0132                    u64 *out_qpage,
0133                    u64 *out_qsize,
0134                    u64 *out_qeoi_page,
0135                    u32 *out_escalate_irq,
0136                    u64 *out_qflags);
0137
0138 int xive_native_get_queue_state(u32 vp_id, uint32_t prio, u32 *qtoggle,
0139                 u32 *qindex);
0140 int xive_native_set_queue_state(u32 vp_id, uint32_t prio, u32 qtoggle,
0141                 u32 qindex);
0142 int xive_native_get_vp_state(u32 vp_id, u64 *out_state);
0143 bool xive_native_has_queue_state_support(void);
0144 extern u32 xive_native_alloc_irq_on_chip(u32 chip_id);
0145
0146 static inline u32 xive_native_alloc_irq(void)
0147 {
0148     return xive_native_alloc_irq_on_chip(OPAL_XIVE_ANY_CHIP);
0149 }
0150
0151 #else
0152
0153 static inline bool xive_enabled(void) { return false; }
0154
0155 static inline bool xive_spapr_init(void) { return false; }
0156 static inline bool xive_native_init(void) { return false; }
0157 static inline void xive_smp_probe(void) { }
0158 static inline int  xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
0159 static inline void xive_smp_setup_cpu(void) { }
0160 static inline void xive_smp_disable_cpu(void) { }
0161 static inline void xive_shutdown(void) { }
0162 static inline void xive_flush_interrupt(void) { }
0163
0164 static inline u32 xive_native_alloc_vp_block(u32 max_vcpus) { return XIVE_INVALID_VP; }
0165 static inline void xive_native_free_vp_block(u32 vp_base) { }
0166
0167 #endif
0168
0169 #endif /* _ASM_POWERPC_XIVE_H */