0001
0002
0003
0004
0005
0006 #ifndef _ASM_POWERPC_VDSO_TIMEBASE_H
0007 #define _ASM_POWERPC_VDSO_TIMEBASE_H
0008
0009 #include <asm/reg.h>
0010
0011
0012
0013
0014
0015 #if defined(__powerpc64__) && (defined(CONFIG_PPC_CELL) || defined(CONFIG_E500))
0016 #define mftb() ({unsigned long rval; \
0017 asm volatile( \
0018 "90: mfspr %0, %2;\n" \
0019 ASM_FTR_IFSET( \
0020 "97: cmpwi %0,0;\n" \
0021 " beq- 90b;\n", "", %1) \
0022 : "=r" (rval) \
0023 : "i" (CPU_FTR_CELL_TB_BUG), "i" (SPRN_TBRL) : "cr0"); \
0024 rval;})
0025 #elif defined(CONFIG_PPC_8xx)
0026 #define mftb() ({unsigned long rval; \
0027 asm volatile("mftbl %0" : "=r" (rval)); rval;})
0028 #else
0029 #define mftb() ({unsigned long rval; \
0030 asm volatile("mfspr %0, %1" : \
0031 "=r" (rval) : "i" (SPRN_TBRL)); rval;})
0032 #endif
0033
0034 #if defined(CONFIG_PPC_8xx)
0035 #define mftbu() ({unsigned long rval; \
0036 asm volatile("mftbu %0" : "=r" (rval)); rval;})
0037 #else
0038 #define mftbu() ({unsigned long rval; \
0039 asm volatile("mfspr %0, %1" : "=r" (rval) : \
0040 "i" (SPRN_TBRU)); rval;})
0041 #endif
0042
0043 #define mttbl(v) asm volatile("mttbl %0":: "r"(v))
0044 #define mttbu(v) asm volatile("mttbu %0":: "r"(v))
0045
0046 static __always_inline u64 get_tb(void)
0047 {
0048 unsigned int tbhi, tblo, tbhi2;
0049
0050
0051
0052
0053
0054 if (__is_defined(__powerpc64__))
0055 return mftb();
0056
0057 do {
0058 tbhi = mftbu();
0059 tblo = mftb();
0060 tbhi2 = mftbu();
0061 } while (tbhi != tbhi2);
0062
0063 return ((u64)tbhi << 32) | tblo;
0064 }
0065
0066 static inline void set_tb(unsigned int upper, unsigned int lower)
0067 {
0068 mtspr(SPRN_TBWL, 0);
0069 mtspr(SPRN_TBWU, upper);
0070 mtspr(SPRN_TBWL, lower);
0071 }
0072
0073 #endif