include/asm/uninorth.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * uninorth.h: definitions for using the "UniNorth" host bridge chip
0004  *             from Apple. This chip is used on "Core99" machines
0005  *         This also includes U2 used on more recent MacRISC2/3
0006  *             machines and U3 (G5)
0007  *
0008  */
0009 #ifdef __KERNEL__
0010 #ifndef __ASM_UNINORTH_H__
0011 #define __ASM_UNINORTH_H__
0012
0013 /*
0014  * Uni-N and U3 config space reg. definitions
0015  *
0016  * (Little endian)
0017  */
0018
0019 /* Address ranges selection. This one should work with Bandit too */
0020 /* Not U3 */
0021 #define UNI_N_ADDR_SELECT       0x48
0022 #define UNI_N_ADDR_COARSE_MASK      0xffff0000  /* 256Mb regions at *0000000 */
0023 #define UNI_N_ADDR_FINE_MASK        0x0000ffff  /*  16Mb regions at f*000000 */
0024
0025 /* AGP registers */
0026 /* Not U3 */
0027 #define UNI_N_CFG_GART_BASE     0x8c
0028 #define UNI_N_CFG_AGP_BASE      0x90
0029 #define UNI_N_CFG_GART_CTRL     0x94
0030 #define UNI_N_CFG_INTERNAL_STATUS   0x98
0031 #define UNI_N_CFG_GART_DUMMY_PAGE   0xa4
0032
0033 /* UNI_N_CFG_GART_CTRL bits definitions */
0034 #define UNI_N_CFG_GART_INVAL        0x00000001
0035 #define UNI_N_CFG_GART_ENABLE       0x00000100
0036 #define UNI_N_CFG_GART_2xRESET      0x00010000
0037 #define UNI_N_CFG_GART_DISSBADET    0x00020000
0038 /* The following seems to only be used only on U3 <j.glisse@gmail.com> */
0039 #define U3_N_CFG_GART_SYNCMODE      0x00040000
0040 #define U3_N_CFG_GART_PERFRD        0x00080000
0041 #define U3_N_CFG_GART_B2BGNT        0x00200000
0042 #define U3_N_CFG_GART_FASTDDR       0x00400000
0043
0044 /* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
0045  * revision 1.5 (x4 AGP) may need further changes.
0046  *
0047  * AGP_BASE register contains the base address of the AGP aperture on
0048  * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
0049  * even if decoding of this address range is enabled in the address select
0050  * register. Apparently, the only supported bases are 256Mb multiples
0051  * (high 4 bits of that register).
0052  *
0053  * GART_BASE register appear to contain the physical address of the GART
0054  * in system memory in the high address bits (page aligned), and the
0055  * GART size in the low order bits (number of GART pages)
0056  *
0057  * The GART format itself is one 32bits word per physical memory page.
0058  * This word contains, in little-endian format (!!!), the physical address
0059  * of the page in the high bits, and what appears to be an "enable" bit
0060  * in the LSB bit (0) that must be set to 1 when the entry is valid.
0061  *
0062  * Obviously, the GART is not cache coherent and so any change to it
0063  * must be flushed to memory (or maybe just make the GART space non
0064  * cachable). AGP memory itself doesn't seem to be cache coherent neither.
0065  *
0066  * In order to invalidate the GART (which is probably necessary to inval
0067  * the bridge internal TLBs), the following sequence has to be written,
0068  * in order, to the GART_CTRL register:
0069  *
0070  *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
0071  *   UNI_N_CFG_GART_ENABLE
0072  *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
0073  *   UNI_N_CFG_GART_ENABLE
0074  *
0075  * As far as AGP "features" are concerned, it looks like fast write may
0076  * not be supported but this has to be confirmed.
0077  *
0078  * Turning on AGP seem to require a double invalidate operation, one before
0079  * setting the AGP command register, on after.
0080  *
0081  * Turning off AGP seems to require the following sequence: first wait
0082  * for the AGP to be idle by reading the internal status register, then
0083  * write in that order to the GART_CTRL register:
0084  *
0085  *   UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
0086  *   0
0087  *   UNI_N_CFG_GART_2xRESET
0088  *   0
0089  */
0090
0091 /*
0092  * Uni-N memory mapped reg. definitions
0093  *
0094  * Those registers are Big-Endian !!
0095  *
0096  * Their meaning come from either Darwin and/or from experiments I made with
0097  * the bootrom, I'm not sure about their exact meaning yet
0098  *
0099  */
0100
0101 /* Version of the UniNorth chip */
0102 #define UNI_N_VERSION           0x0000      /* Known versions: 3,7 and 8 */
0103
0104 #define UNI_N_VERSION_107       0x0003      /* 1.0.7 */
0105 #define UNI_N_VERSION_10A       0x0007      /* 1.0.10 */
0106 #define UNI_N_VERSION_150       0x0011      /* 1.5 */
0107 #define UNI_N_VERSION_200       0x0024      /* 2.0 */
0108 #define UNI_N_VERSION_PANGEA        0x00C0      /* Integrated U1 + K */
0109 #define UNI_N_VERSION_INTREPID      0x00D2      /* Integrated U2 + K */
0110 #define UNI_N_VERSION_300       0x0030      /* 3.0 (U3 on G5) */
0111
0112 /* This register is used to enable/disable various clocks */
0113 #define UNI_N_CLOCK_CNTL        0x0020
0114 #define UNI_N_CLOCK_CNTL_PCI        0x00000001  /* PCI2 clock control */
0115 #define UNI_N_CLOCK_CNTL_GMAC       0x00000002  /* GMAC clock control */
0116 #define UNI_N_CLOCK_CNTL_FW     0x00000004  /* FireWire clock control */
0117 #define UNI_N_CLOCK_CNTL_ATA100     0x00000010  /* ATA-100 clock control (U2) */
0118
0119 /* Power Management control */
0120 #define UNI_N_POWER_MGT         0x0030
0121 #define UNI_N_POWER_MGT_NORMAL      0x00
0122 #define UNI_N_POWER_MGT_IDLE2       0x01
0123 #define UNI_N_POWER_MGT_SLEEP       0x02
0124
0125 /* This register is configured by Darwin depending on the UniN
0126  * revision
0127  */
0128 #define UNI_N_ARB_CTRL          0x0040
0129 #define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
0130 #define UNI_N_ARB_CTRL_QACK_DELAY_MASK  0x0e1f8000
0131 #define UNI_N_ARB_CTRL_QACK_DELAY   0x30
0132 #define UNI_N_ARB_CTRL_QACK_DELAY105    0x00
0133
0134 /* This one _might_ return the CPU number of the CPU reading it;
0135  * the bootROM decides whether to boot or to sleep/spinloop depending
0136  * on this register being 0 or not
0137  */
0138 #define UNI_N_CPU_NUMBER        0x0050
0139
0140 /* This register appear to be read by the bootROM to decide what
0141  *  to do on a non-recoverable reset (powerup or wakeup)
0142  */
0143 #define UNI_N_HWINIT_STATE      0x0070
0144 #define UNI_N_HWINIT_STATE_SLEEPING 0x01
0145 #define UNI_N_HWINIT_STATE_RUNNING  0x02
0146 /* This last bit appear to be used by the bootROM to know the second
0147  * CPU has started and will enter it's sleep loop with IP=0
0148  */
0149 #define UNI_N_HWINIT_STATE_CPU1_FLAG    0x10000000
0150
0151 /* This register controls AACK delay, which is set when 2004 iBook/PowerBook
0152  * is in low speed mode.
0153  */
0154 #define UNI_N_AACK_DELAY        0x0100
0155 #define UNI_N_AACK_DELAY_ENABLE     0x00000001
0156
0157 /* Clock status for Intrepid */
0158 #define UNI_N_CLOCK_STOP_STATUS0    0x0150
0159 #define UNI_N_CLOCK_STOPPED_EXTAGP  0x00200000
0160 #define UNI_N_CLOCK_STOPPED_AGPDEL  0x00100000
0161 #define UNI_N_CLOCK_STOPPED_I2S0_45_49  0x00080000
0162 #define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000
0163 #define UNI_N_CLOCK_STOPPED_I2S1_45_49  0x00020000
0164 #define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000
0165 #define UNI_N_CLOCK_STOPPED_TIMER   0x00008000
0166 #define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
0167 #define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
0168 #define UNI_N_CLOCK_STOPPED_SCC_VIA32   0x00001000
0169 #define UNI_N_CLOCK_STOPPED_SCC_SLOT0   0x00000800
0170 #define UNI_N_CLOCK_STOPPED_SCC_SLOT1   0x00000400
0171 #define UNI_N_CLOCK_STOPPED_SCC_SLOT2   0x00000200
0172 #define UNI_N_CLOCK_STOPPED_PCI_FBCLKO  0x00000100
0173 #define UNI_N_CLOCK_STOPPED_VEO0    0x00000080
0174 #define UNI_N_CLOCK_STOPPED_VEO1    0x00000040
0175 #define UNI_N_CLOCK_STOPPED_USB0    0x00000020
0176 #define UNI_N_CLOCK_STOPPED_USB1    0x00000010
0177 #define UNI_N_CLOCK_STOPPED_USB2    0x00000008
0178 #define UNI_N_CLOCK_STOPPED_32      0x00000004
0179 #define UNI_N_CLOCK_STOPPED_45      0x00000002
0180 #define UNI_N_CLOCK_STOPPED_49      0x00000001
0181
0182 #define UNI_N_CLOCK_STOP_STATUS1    0x0160
0183 #define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000
0184 #define UNI_N_CLOCK_STOPPED_CPUDEL  0x00040000
0185 #define UNI_N_CLOCK_STOPPED_CPU     0x00020000
0186 #define UNI_N_CLOCK_STOPPED_BUF_REFCKO  0x00010000
0187 #define UNI_N_CLOCK_STOPPED_PCI2    0x00008000
0188 #define UNI_N_CLOCK_STOPPED_FW      0x00004000
0189 #define UNI_N_CLOCK_STOPPED_GB      0x00002000
0190 #define UNI_N_CLOCK_STOPPED_ATA66   0x00001000
0191 #define UNI_N_CLOCK_STOPPED_ATA100  0x00000800
0192 #define UNI_N_CLOCK_STOPPED_MAX     0x00000400
0193 #define UNI_N_CLOCK_STOPPED_PCI1    0x00000200
0194 #define UNI_N_CLOCK_STOPPED_KLPCI   0x00000100
0195 #define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080
0196 #define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040
0197 #define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020
0198 #define UNI_N_CLOCK_STOPPED_7PCI1   0x00000008
0199 #define UNI_N_CLOCK_STOPPED_AGP     0x00000004
0200 #define UNI_N_CLOCK_STOPPED_PCI0    0x00000002
0201 #define UNI_N_CLOCK_STOPPED_18      0x00000001
0202
0203 /* Intrepid registe to OF do-platform-clockspreading */
0204 #define UNI_N_CLOCK_SPREADING       0x190
0205
0206 /* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
0207
0208
0209 /*
0210  * U3 specific registers
0211  */
0212
0213
0214 /* U3 Toggle */
0215 #define U3_TOGGLE_REG           0x00e0
0216 #define U3_PMC_START_STOP       0x0001
0217 #define U3_MPIC_RESET           0x0002
0218 #define U3_MPIC_OUTPUT_ENABLE       0x0004
0219
0220 /* U3 API PHY Config 1 */
0221 #define U3_API_PHY_CONFIG_1     0x23030
0222
0223 /* U3 HyperTransport registers */
0224 #define U3_HT_CONFIG_BASE           0x70000
0225 #define U3_HT_LINK_COMMAND      0x100
0226 #define U3_HT_LINK_CONFIG       0x110
0227 #define U3_HT_LINK_FREQ         0x120
0228
0229 #endif /* __ASM_UNINORTH_H__ */
0230 #endif /* __KERNEL__ */