include/asm/tsi108.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * common routine and memory layout for Tundra TSI108(Grendel) host bridge
0004  * memory controller.
0005  *
0006  * Author: Jacob Pan (jacob.pan@freescale.com)
0007  *     Alex Bounine (alexandreb@tundra.com)
0008  *
0009  * Copyright 2004-2006 Freescale Semiconductor, Inc.
0010  */
0011
0012 #ifndef __PPC_KERNEL_TSI108_H
0013 #define __PPC_KERNEL_TSI108_H
0014
0015 #include <asm/pci-bridge.h>
0016
0017 /* Size of entire register space */
0018 #define TSI108_REG_SIZE     (0x10000)
0019
0020 /* Sizes of register spaces for individual blocks */
0021 #define TSI108_HLP_SIZE     0x1000
0022 #define TSI108_PCI_SIZE     0x1000
0023 #define TSI108_CLK_SIZE     0x1000
0024 #define TSI108_PB_SIZE      0x1000
0025 #define TSI108_SD_SIZE      0x1000
0026 #define TSI108_DMA_SIZE     0x1000
0027 #define TSI108_ETH_SIZE     0x1000
0028 #define TSI108_I2C_SIZE     0x400
0029 #define TSI108_MPIC_SIZE    0x400
0030 #define TSI108_UART0_SIZE   0x200
0031 #define TSI108_GPIO_SIZE    0x200
0032 #define TSI108_UART1_SIZE   0x200
0033
0034 /* Offsets within Tsi108(A) CSR space for individual blocks */
0035 #define TSI108_HLP_OFFSET   0x0000
0036 #define TSI108_PCI_OFFSET   0x1000
0037 #define TSI108_CLK_OFFSET   0x2000
0038 #define TSI108_PB_OFFSET    0x3000
0039 #define TSI108_SD_OFFSET    0x4000
0040 #define TSI108_DMA_OFFSET   0x5000
0041 #define TSI108_ETH_OFFSET   0x6000
0042 #define TSI108_I2C_OFFSET   0x7000
0043 #define TSI108_MPIC_OFFSET  0x7400
0044 #define TSI108_UART0_OFFSET 0x7800
0045 #define TSI108_GPIO_OFFSET  0x7A00
0046 #define TSI108_UART1_OFFSET 0x7C00
0047
0048 /* Tsi108 registers used by common code components */
0049 #define TSI108_PCI_CSR      (0x004)
0050 #define TSI108_PCI_IRP_CFG_CTL  (0x180)
0051 #define TSI108_PCI_IRP_STAT (0x184)
0052 #define TSI108_PCI_IRP_ENABLE   (0x188)
0053 #define TSI108_PCI_IRP_INTAD    (0x18C)
0054
0055 #define TSI108_PCI_IRP_STAT_P_INT   (0x00400000)
0056 #define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
0057
0058 #define TSI108_CG_PWRUP_STATUS  (0x234)
0059
0060 #define TSI108_PB_ISR       (0x00C)
0061 #define TSI108_PB_ERRCS     (0x404)
0062 #define TSI108_PB_AERR      (0x408)
0063
0064 #define TSI108_PB_ERRCS_ES      (1 << 1)
0065 #define TSI108_PB_ISR_PBS_RD_ERR    (1 << 8)
0066
0067 #define TSI108_PCI_CFG_SIZE     (0x01000000)
0068
0069 /*
0070  * PHY Configuration Options
0071  *
0072  * Specify "bcm54xx" in the compatible property of your device tree phy
0073  * nodes if your board uses the Broadcom PHYs
0074  */
0075 #define TSI108_PHY_MV88E    0   /* Marvel 88Exxxx PHY */
0076 #define TSI108_PHY_BCM54XX  1   /* Broadcom BCM54xx PHY */
0077
0078 /* Global variables */
0079
0080 extern u32 tsi108_pci_cfg_base;
0081 /* Exported functions */
0082
0083 extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
0084                       int offset, int len, u32 val);
0085 extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
0086                      int offset, int len, u32 * val);
0087 extern void tsi108_clear_pci_error(u32 pci_cfg_base);
0088
0089 extern phys_addr_t get_csrbase(void);
0090
0091 typedef struct {
0092     u32 regs;       /* hw registers base address */
0093     u32 phyregs;        /* phy registers base address */
0094     u16 phy;        /* phy address */
0095     u16 irq_num;        /* irq number */
0096     u8 mac_addr[6];     /* phy mac address */
0097     u16 phy_type;   /* type of phy on board */
0098 } hw_info;
0099
0100 extern u32 get_vir_csrbase(void);
0101 extern u32 tsi108_csr_vir_base;
0102
0103 static inline u32 tsi108_read_reg(u32 reg_offset)
0104 {
0105     return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
0106 }
0107
0108 static inline void tsi108_write_reg(u32 reg_offset, u32 val)
0109 {
0110     out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
0111 }
0112
0113 #endif              /* __PPC_KERNEL_TSI108_H */