include/asm/sstep.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
0004  */
0005 #include <asm/inst.h>
0006
0007 struct pt_regs;
0008
0009 /*
0010  * We don't allow single-stepping an mtmsrd that would clear
0011  * MSR_RI, since that would make the exception unrecoverable.
0012  * Since we need to single-step to proceed from a breakpoint,
0013  * we don't allow putting a breakpoint on an mtmsrd instruction.
0014  * Similarly we don't allow breakpoints on rfid instructions.
0015  * These macros tell us if an instruction is a mtmsrd or rfid.
0016  * Note that these return true for both mtmsr/rfi (32-bit)
0017  * and mtmsrd/rfid (64-bit).
0018  */
0019 #define IS_MTMSRD(instr)    ((ppc_inst_val(instr) & 0xfc0007be) == 0x7c000124)
0020 #define IS_RFID(instr)      ((ppc_inst_val(instr) & 0xfc0007be) == 0x4c000024)
0021
0022 enum instruction_type {
0023     COMPUTE,        /* arith/logical/CR op, etc. */
0024     LOAD,           /* load and store types need to be contiguous */
0025     LOAD_MULTI,
0026     LOAD_FP,
0027     LOAD_VMX,
0028     LOAD_VSX,
0029     STORE,
0030     STORE_MULTI,
0031     STORE_FP,
0032     STORE_VMX,
0033     STORE_VSX,
0034     LARX,
0035     STCX,
0036     BRANCH,
0037     MFSPR,
0038     MTSPR,
0039     CACHEOP,
0040     BARRIER,
0041     SYSCALL,
0042     SYSCALL_VECTORED_0,
0043     MFMSR,
0044     MTMSR,
0045     RFI,
0046     INTERRUPT,
0047     UNKNOWN
0048 };
0049
0050 #define INSTR_TYPE_MASK 0x1f
0051
0052 #define OP_IS_LOAD(type)    ((LOAD <= (type) && (type) <= LOAD_VSX) || (type) == LARX)
0053 #define OP_IS_STORE(type)   ((STORE <= (type) && (type) <= STORE_VSX) || (type) == STCX)
0054 #define OP_IS_LOAD_STORE(type)  (LOAD <= (type) && (type) <= STCX)
0055
0056 /* Compute flags, ORed in with type */
0057 #define SETREG      0x20
0058 #define SETCC       0x40
0059 #define SETXER      0x80
0060
0061 /* Branch flags, ORed in with type */
0062 #define SETLK       0x20
0063 #define BRTAKEN     0x40
0064 #define DECCTR      0x80
0065
0066 /* Load/store flags, ORed in with type */
0067 #define SIGNEXT     0x20
0068 #define UPDATE      0x40    /* matches bit in opcode 31 instructions */
0069 #define BYTEREV     0x80
0070 #define FPCONV      0x100
0071
0072 /* Barrier type field, ORed in with type */
0073 #define BARRIER_MASK    0xe0
0074 #define BARRIER_SYNC    0x00
0075 #define BARRIER_ISYNC   0x20
0076 #define BARRIER_EIEIO   0x40
0077 #define BARRIER_LWSYNC  0x60
0078 #define BARRIER_PTESYNC 0x80
0079
0080 /* Cacheop values, ORed in with type */
0081 #define CACHEOP_MASK    0x700
0082 #define DCBST       0
0083 #define DCBF        0x100
0084 #define DCBTST      0x200
0085 #define DCBT        0x300
0086 #define ICBI        0x400
0087 #define DCBZ        0x500
0088
0089 /* VSX flags values */
0090 #define VSX_FPCONV  1   /* do floating point SP/DP conversion */
0091 #define VSX_SPLAT   2   /* store loaded value into all elements */
0092 #define VSX_LDLEFT  4   /* load VSX register from left */
0093 #define VSX_CHECK_VEC   8   /* check MSR_VEC not MSR_VSX for reg >= 32 */
0094
0095 /* Prefixed flag, ORed in with type */
0096 #define PREFIXED       0x800
0097
0098 /* Size field in type word */
0099 #define SIZE(n)     ((n) << 12)
0100 #define GETSIZE(w)  ((w) >> 12)
0101
0102 #define GETTYPE(t)  ((t) & INSTR_TYPE_MASK)
0103 #define GETLENGTH(t)   (((t) & PREFIXED) ? 8 : 4)
0104
0105 #define MKOP(t, f, s)   ((t) | (f) | SIZE(s))
0106
0107 /* Prefix instruction operands */
0108 #define GET_PREFIX_RA(i)    (((i) >> 16) & 0x1f)
0109 #define GET_PREFIX_R(i)     ((i) & (1ul << 20))
0110
0111 extern s32 patch__exec_instr;
0112
0113 struct instruction_op {
0114     int type;
0115     int reg;
0116     unsigned long val;
0117     /* For LOAD/STORE/LARX/STCX */
0118     unsigned long ea;
0119     int update_reg;
0120     /* For MFSPR */
0121     int spr;
0122     u32 ccval;
0123     u32 xerval;
0124     u8 element_size;    /* for VSX/VMX loads/stores */
0125     u8 vsx_flags;
0126 };
0127
0128 union vsx_reg {
0129     u8  b[16];
0130     u16 h[8];
0131     u32 w[4];
0132     unsigned long d[2];
0133     float   fp[4];
0134     double  dp[2];
0135     __vector128 v;
0136 };
0137
0138 /*
0139  * Decode an instruction, and return information about it in *op
0140  * without changing *regs.
0141  *
0142  * Return value is 1 if the instruction can be emulated just by
0143  * updating *regs with the information in *op, -1 if we need the
0144  * GPRs but *regs doesn't contain the full register set, or 0
0145  * otherwise.
0146  */
0147 extern int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
0148              ppc_inst_t instr);
0149
0150 /*
0151  * Emulate an instruction that can be executed just by updating
0152  * fields in *regs.
0153  */
0154 void emulate_update_regs(struct pt_regs *reg, struct instruction_op *op);
0155
0156 /*
0157  * Emulate instructions that cause a transfer of control,
0158  * arithmetic/logical instructions, loads and stores,
0159  * cache operations and barriers.
0160  *
0161  * Returns 1 if the instruction was emulated successfully,
0162  * 0 if it could not be emulated, or -1 for an instruction that
0163  * should not be emulated (rfid, mtmsrd clearing MSR_RI, etc.).
0164  */
0165 int emulate_step(struct pt_regs *regs, ppc_inst_t instr);
0166
0167 /*
0168  * Emulate a load or store instruction by reading/writing the
0169  * memory of the current process.  FP/VMX/VSX registers are assumed
0170  * to hold live values if the appropriate enable bit in regs->msr is
0171  * set; otherwise this will use the saved values in the thread struct
0172  * for user-mode accesses.
0173  */
0174 extern int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op);
0175
0176 extern void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
0177                  const void *mem, bool cross_endian);
0178 extern void emulate_vsx_store(struct instruction_op *op,
0179                   const union vsx_reg *reg, void *mem,
0180                   bool cross_endian);
0181 extern int emulate_dcbz(unsigned long ea, struct pt_regs *regs);