include/asm/spu_csa.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * spu_csa.h: Definitions for SPU context save area (CSA).
0004  *
0005  * (C) Copyright IBM 2005
0006  *
0007  * Author: Mark Nutter <mnutter@us.ibm.com>
0008  */
0009
0010 #ifndef _SPU_CSA_H_
0011 #define _SPU_CSA_H_
0012 #ifdef __KERNEL__
0013
0014 /*
0015  * Total number of 128-bit registers.
0016  */
0017 #define NR_SPU_GPRS             128
0018 #define NR_SPU_SPRS             9
0019 #define NR_SPU_REGS_PAD         7
0020 #define NR_SPU_SPILL_REGS       144 /* GPRS + SPRS + PAD */
0021 #define SIZEOF_SPU_SPILL_REGS   NR_SPU_SPILL_REGS * 16
0022
0023 #define SPU_SAVE_COMPLETE       0x3FFB
0024 #define SPU_RESTORE_COMPLETE    0x3FFC
0025
0026 /*
0027  * Definitions for various 'stopped' status conditions,
0028  * to be recreated during context restore.
0029  */
0030 #define SPU_STOPPED_STATUS_P    1
0031 #define SPU_STOPPED_STATUS_I    2
0032 #define SPU_STOPPED_STATUS_H    3
0033 #define SPU_STOPPED_STATUS_S    4
0034 #define SPU_STOPPED_STATUS_S_I  5
0035 #define SPU_STOPPED_STATUS_S_P  6
0036 #define SPU_STOPPED_STATUS_P_H  7
0037 #define SPU_STOPPED_STATUS_P_I  8
0038 #define SPU_STOPPED_STATUS_R    9
0039
0040 /*
0041  * Definitions for software decrementer status flag.
0042  */
0043 #define SPU_DECR_STATUS_RUNNING 0x1
0044 #define SPU_DECR_STATUS_WRAPPED 0x2
0045
0046 #ifndef  __ASSEMBLY__
0047 /**
0048  * spu_reg128 - generic 128-bit register definition.
0049  */
0050 struct spu_reg128 {
0051     u32 slot[4];
0052 };
0053
0054 /**
0055  * struct spu_lscsa - Local Store Context Save Area.
0056  * @gprs: Array of saved registers.
0057  * @fpcr: Saved floating point status control register.
0058  * @decr: Saved decrementer value.
0059  * @decr_status: Indicates software decrementer status flags.
0060  * @ppu_mb: Saved PPU mailbox data.
0061  * @ppuint_mb: Saved PPU interrupting mailbox data.
0062  * @tag_mask: Saved tag group mask.
0063  * @event_mask: Saved event mask.
0064  * @srr0: Saved SRR0.
0065  * @stopped_status: Conditions to be recreated by restore.
0066  * @ls: Saved contents of Local Storage Area.
0067  *
0068  * The LSCSA represents state that is primarily saved and
0069  * restored by SPU-side code.
0070  */
0071 struct spu_lscsa {
0072     struct spu_reg128 gprs[128];
0073     struct spu_reg128 fpcr;
0074     struct spu_reg128 decr;
0075     struct spu_reg128 decr_status;
0076     struct spu_reg128 ppu_mb;
0077     struct spu_reg128 ppuint_mb;
0078     struct spu_reg128 tag_mask;
0079     struct spu_reg128 event_mask;
0080     struct spu_reg128 srr0;
0081     struct spu_reg128 stopped_status;
0082
0083     /*
0084      * 'ls' must be page-aligned on all configurations.
0085      * Since we don't want to rely on having the spu-gcc
0086      * installed to build the kernel and this structure
0087      * is used in the SPU-side code, make it 64k-page
0088      * aligned for now.
0089      */
0090     unsigned char ls[LS_SIZE] __attribute__((aligned(65536)));
0091 };
0092
0093 #ifndef __SPU__
0094 /*
0095  * struct spu_problem_collapsed - condensed problem state area, w/o pads.
0096  */
0097 struct spu_problem_collapsed {
0098     u64 spc_mssync_RW;
0099     u32 mfc_lsa_W;
0100     u32 unused_pad0;
0101     u64 mfc_ea_W;
0102     union mfc_tag_size_class_cmd mfc_union_W;
0103     u32 dma_qstatus_R;
0104     u32 dma_querytype_RW;
0105     u32 dma_querymask_RW;
0106     u32 dma_tagstatus_R;
0107     u32 pu_mb_R;
0108     u32 spu_mb_W;
0109     u32 mb_stat_R;
0110     u32 spu_runcntl_RW;
0111     u32 spu_status_R;
0112     u32 spu_spc_R;
0113     u32 spu_npc_RW;
0114     u32 signal_notify1;
0115     u32 signal_notify2;
0116     u32 unused_pad1;
0117 };
0118
0119 /*
0120  * struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
0121  */
0122 struct spu_priv1_collapsed {
0123     u64 mfc_sr1_RW;
0124     u64 mfc_lpid_RW;
0125     u64 spu_idr_RW;
0126     u64 mfc_vr_RO;
0127     u64 spu_vr_RO;
0128     u64 int_mask_class0_RW;
0129     u64 int_mask_class1_RW;
0130     u64 int_mask_class2_RW;
0131     u64 int_stat_class0_RW;
0132     u64 int_stat_class1_RW;
0133     u64 int_stat_class2_RW;
0134     u64 int_route_RW;
0135     u64 mfc_atomic_flush_RW;
0136     u64 resource_allocation_groupID_RW;
0137     u64 resource_allocation_enable_RW;
0138     u64 mfc_fir_R;
0139     u64 mfc_fir_status_or_W;
0140     u64 mfc_fir_status_and_W;
0141     u64 mfc_fir_mask_R;
0142     u64 mfc_fir_mask_or_W;
0143     u64 mfc_fir_mask_and_W;
0144     u64 mfc_fir_chkstp_enable_RW;
0145     u64 smf_sbi_signal_sel;
0146     u64 smf_ato_signal_sel;
0147     u64 tlb_index_hint_RO;
0148     u64 tlb_index_W;
0149     u64 tlb_vpn_RW;
0150     u64 tlb_rpn_RW;
0151     u64 tlb_invalidate_entry_W;
0152     u64 tlb_invalidate_all_W;
0153     u64 smm_hid;
0154     u64 mfc_accr_RW;
0155     u64 mfc_dsisr_RW;
0156     u64 mfc_dar_RW;
0157     u64 rmt_index_RW;
0158     u64 rmt_data1_RW;
0159     u64 mfc_dsir_R;
0160     u64 mfc_lsacr_RW;
0161     u64 mfc_lscrr_R;
0162     u64 mfc_tclass_id_RW;
0163     u64 mfc_rm_boundary;
0164     u64 smf_dma_signal_sel;
0165     u64 smm_signal_sel;
0166     u64 mfc_cer_R;
0167     u64 pu_ecc_cntl_RW;
0168     u64 pu_ecc_stat_RW;
0169     u64 spu_ecc_addr_RW;
0170     u64 spu_err_mask_RW;
0171     u64 spu_trig0_sel;
0172     u64 spu_trig1_sel;
0173     u64 spu_trig2_sel;
0174     u64 spu_trig3_sel;
0175     u64 spu_trace_sel;
0176     u64 spu_event0_sel;
0177     u64 spu_event1_sel;
0178     u64 spu_event2_sel;
0179     u64 spu_event3_sel;
0180     u64 spu_trace_cntl;
0181 };
0182
0183 /*
0184  * struct spu_priv2_collapsed - condensed privileged 2 area, w/o pads.
0185  */
0186 struct spu_priv2_collapsed {
0187     u64 slb_index_W;
0188     u64 slb_esid_RW;
0189     u64 slb_vsid_RW;
0190     u64 slb_invalidate_entry_W;
0191     u64 slb_invalidate_all_W;
0192     struct mfc_cq_sr spuq[16];
0193     struct mfc_cq_sr puq[8];
0194     u64 mfc_control_RW;
0195     u64 puint_mb_R;
0196     u64 spu_privcntl_RW;
0197     u64 spu_lslr_RW;
0198     u64 spu_chnlcntptr_RW;
0199     u64 spu_chnlcnt_RW;
0200     u64 spu_chnldata_RW;
0201     u64 spu_cfg_RW;
0202     u64 spu_tag_status_query_RW;
0203     u64 spu_cmd_buf1_RW;
0204     u64 spu_cmd_buf2_RW;
0205     u64 spu_atomic_status_RW;
0206 };
0207
0208 /**
0209  * struct spu_state
0210  * @lscsa: Local Store Context Save Area.
0211  * @prob: Collapsed Problem State Area, w/o pads.
0212  * @priv1: Collapsed Privileged 1 Area, w/o pads.
0213  * @priv2: Collapsed Privileged 2 Area, w/o pads.
0214  * @spu_chnlcnt_RW: Array of saved channel counts.
0215  * @spu_chnldata_RW: Array of saved channel data.
0216  * @suspend_time: Time stamp when decrementer disabled.
0217  *
0218  * Structure representing the whole of the SPU
0219  * context save area (CSA).  This struct contains
0220  * all of the state necessary to suspend and then
0221  * later optionally resume execution of an SPU
0222  * context.
0223  *
0224  * The @lscsa region is by far the largest, and is
0225  * allocated separately so that it may either be
0226  * pinned or mapped to/from application memory, as
0227  * appropriate for the OS environment.
0228  */
0229 struct spu_state {
0230     struct spu_lscsa *lscsa;
0231     struct spu_problem_collapsed prob;
0232     struct spu_priv1_collapsed priv1;
0233     struct spu_priv2_collapsed priv2;
0234     u64 spu_chnlcnt_RW[32];
0235     u64 spu_chnldata_RW[32];
0236     u32 spu_mailbox_data[4];
0237     u32 pu_mailbox_data[1];
0238     u64 class_0_dar, class_0_pending;
0239     u64 class_1_dar, class_1_dsisr;
0240     unsigned long suspend_time;
0241     spinlock_t register_lock;
0242 };
0243
0244 #endif /* !__SPU__ */
0245 #endif /* __KERNEL__ */
0246 #endif /* !__ASSEMBLY__ */
0247 #endif /* _SPU_CSA_H_ */