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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * SPU core / file system interface and HW structures
0004  *
0005  * (C) Copyright IBM Deutschland Entwicklung GmbH 2005
0006  *
0007  * Author: Arnd Bergmann <arndb@de.ibm.com>
0008  */
0009 
0010 #ifndef _SPU_H
0011 #define _SPU_H
0012 #ifdef __KERNEL__
0013 
0014 #include <linux/workqueue.h>
0015 #include <linux/device.h>
0016 #include <linux/mutex.h>
0017 #include <asm/reg.h>
0018 #include <asm/copro.h>
0019 
0020 #define LS_SIZE (256 * 1024)
0021 #define LS_ADDR_MASK (LS_SIZE - 1)
0022 
0023 #define MFC_PUT_CMD             0x20
0024 #define MFC_PUTS_CMD            0x28
0025 #define MFC_PUTR_CMD            0x30
0026 #define MFC_PUTF_CMD            0x22
0027 #define MFC_PUTB_CMD            0x21
0028 #define MFC_PUTFS_CMD           0x2A
0029 #define MFC_PUTBS_CMD           0x29
0030 #define MFC_PUTRF_CMD           0x32
0031 #define MFC_PUTRB_CMD           0x31
0032 #define MFC_PUTL_CMD            0x24
0033 #define MFC_PUTRL_CMD           0x34
0034 #define MFC_PUTLF_CMD           0x26
0035 #define MFC_PUTLB_CMD           0x25
0036 #define MFC_PUTRLF_CMD          0x36
0037 #define MFC_PUTRLB_CMD          0x35
0038 
0039 #define MFC_GET_CMD             0x40
0040 #define MFC_GETS_CMD            0x48
0041 #define MFC_GETF_CMD            0x42
0042 #define MFC_GETB_CMD            0x41
0043 #define MFC_GETFS_CMD           0x4A
0044 #define MFC_GETBS_CMD           0x49
0045 #define MFC_GETL_CMD            0x44
0046 #define MFC_GETLF_CMD           0x46
0047 #define MFC_GETLB_CMD           0x45
0048 
0049 #define MFC_SDCRT_CMD           0x80
0050 #define MFC_SDCRTST_CMD         0x81
0051 #define MFC_SDCRZ_CMD           0x89
0052 #define MFC_SDCRS_CMD           0x8D
0053 #define MFC_SDCRF_CMD           0x8F
0054 
0055 #define MFC_GETLLAR_CMD         0xD0
0056 #define MFC_PUTLLC_CMD          0xB4
0057 #define MFC_PUTLLUC_CMD         0xB0
0058 #define MFC_PUTQLLUC_CMD        0xB8
0059 #define MFC_SNDSIG_CMD          0xA0
0060 #define MFC_SNDSIGB_CMD         0xA1
0061 #define MFC_SNDSIGF_CMD         0xA2
0062 #define MFC_BARRIER_CMD         0xC0
0063 #define MFC_EIEIO_CMD           0xC8
0064 #define MFC_SYNC_CMD            0xCC
0065 
0066 #define MFC_MIN_DMA_SIZE_SHIFT  4       /* 16 bytes */
0067 #define MFC_MAX_DMA_SIZE_SHIFT  14      /* 16384 bytes */
0068 #define MFC_MIN_DMA_SIZE        (1 << MFC_MIN_DMA_SIZE_SHIFT)
0069 #define MFC_MAX_DMA_SIZE        (1 << MFC_MAX_DMA_SIZE_SHIFT)
0070 #define MFC_MIN_DMA_SIZE_MASK   (MFC_MIN_DMA_SIZE - 1)
0071 #define MFC_MAX_DMA_SIZE_MASK   (MFC_MAX_DMA_SIZE - 1)
0072 #define MFC_MIN_DMA_LIST_SIZE   0x0008  /*   8 bytes */
0073 #define MFC_MAX_DMA_LIST_SIZE   0x4000  /* 16K bytes */
0074 
0075 #define MFC_TAGID_TO_TAGMASK(tag_id)  (1 << (tag_id & 0x1F))
0076 
0077 /* Events for Channels 0-2 */
0078 #define MFC_DMA_TAG_STATUS_UPDATE_EVENT     0x00000001
0079 #define MFC_DMA_TAG_CMD_STALL_NOTIFY_EVENT  0x00000002
0080 #define MFC_DMA_QUEUE_AVAILABLE_EVENT       0x00000008
0081 #define MFC_SPU_MAILBOX_WRITTEN_EVENT       0x00000010
0082 #define MFC_DECREMENTER_EVENT               0x00000020
0083 #define MFC_PU_INT_MAILBOX_AVAILABLE_EVENT  0x00000040
0084 #define MFC_PU_MAILBOX_AVAILABLE_EVENT      0x00000080
0085 #define MFC_SIGNAL_2_EVENT                  0x00000100
0086 #define MFC_SIGNAL_1_EVENT                  0x00000200
0087 #define MFC_LLR_LOST_EVENT                  0x00000400
0088 #define MFC_PRIV_ATTN_EVENT                 0x00000800
0089 #define MFC_MULTI_SRC_EVENT                 0x00001000
0090 
0091 /* Flag indicating progress during context switch. */
0092 #define SPU_CONTEXT_SWITCH_PENDING  0UL
0093 #define SPU_CONTEXT_FAULT_PENDING   1UL
0094 
0095 struct spu_context;
0096 struct spu_runqueue;
0097 struct spu_lscsa;
0098 struct device_node;
0099 
0100 enum spu_utilization_state {
0101     SPU_UTIL_USER,
0102     SPU_UTIL_SYSTEM,
0103     SPU_UTIL_IOWAIT,
0104     SPU_UTIL_IDLE_LOADED,
0105     SPU_UTIL_MAX
0106 };
0107 
0108 struct spu {
0109     const char *name;
0110     unsigned long local_store_phys;
0111     u8 *local_store;
0112     unsigned long problem_phys;
0113     struct spu_problem __iomem *problem;
0114     struct spu_priv2 __iomem *priv2;
0115     struct list_head cbe_list;
0116     struct list_head full_list;
0117     enum { SPU_FREE, SPU_USED } alloc_state;
0118     int number;
0119     unsigned int irqs[3];
0120     u32 node;
0121     unsigned long flags;
0122     u64 class_0_pending;
0123     u64 class_0_dar;
0124     u64 class_1_dar;
0125     u64 class_1_dsisr;
0126     size_t ls_size;
0127     unsigned int slb_replace;
0128     struct mm_struct *mm;
0129     struct spu_context *ctx;
0130     struct spu_runqueue *rq;
0131     unsigned long long timestamp;
0132     pid_t pid;
0133     pid_t tgid;
0134     spinlock_t register_lock;
0135 
0136     void (* wbox_callback)(struct spu *spu);
0137     void (* ibox_callback)(struct spu *spu);
0138     void (* stop_callback)(struct spu *spu, int irq);
0139     void (* mfc_callback)(struct spu *spu);
0140 
0141     char irq_c0[8];
0142     char irq_c1[8];
0143     char irq_c2[8];
0144 
0145     u64 spe_id;
0146 
0147     void* pdata; /* platform private data */
0148 
0149     /* of based platforms only */
0150     struct device_node *devnode;
0151 
0152     /* native only */
0153     struct spu_priv1 __iomem *priv1;
0154 
0155     /* beat only */
0156     u64 shadow_int_mask_RW[3];
0157 
0158     struct device dev;
0159 
0160     int has_mem_affinity;
0161     struct list_head aff_list;
0162 
0163     struct {
0164         /* protected by interrupt reentrancy */
0165         enum spu_utilization_state util_state;
0166         unsigned long long tstamp;
0167         unsigned long long times[SPU_UTIL_MAX];
0168         unsigned long long vol_ctx_switch;
0169         unsigned long long invol_ctx_switch;
0170         unsigned long long min_flt;
0171         unsigned long long maj_flt;
0172         unsigned long long hash_flt;
0173         unsigned long long slb_flt;
0174         unsigned long long class2_intr;
0175         unsigned long long libassist;
0176     } stats;
0177 };
0178 
0179 struct cbe_spu_info {
0180     struct mutex list_mutex;
0181     struct list_head spus;
0182     int n_spus;
0183     int nr_active;
0184     atomic_t busy_spus;
0185     atomic_t reserved_spus;
0186 };
0187 
0188 extern struct cbe_spu_info cbe_spu_info[];
0189 
0190 void spu_init_channels(struct spu *spu);
0191 void spu_irq_setaffinity(struct spu *spu, int cpu);
0192 
0193 void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
0194         void *code, int code_size);
0195 
0196 extern void spu_invalidate_slbs(struct spu *spu);
0197 extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
0198 int spu_64k_pages_available(void);
0199 
0200 /* Calls from the memory management to the SPU */
0201 struct mm_struct;
0202 extern void spu_flush_all_slbs(struct mm_struct *mm);
0203 
0204 /* system callbacks from the SPU */
0205 struct spu_syscall_block {
0206     u64 nr_ret;
0207     u64 parm[6];
0208 };
0209 extern long spu_sys_callback(struct spu_syscall_block *s);
0210 
0211 /* syscalls implemented in spufs */
0212 struct file;
0213 struct coredump_params;
0214 struct spufs_calls {
0215     long (*create_thread)(const char __user *name,
0216                     unsigned int flags, umode_t mode,
0217                     struct file *neighbor);
0218     long (*spu_run)(struct file *filp, __u32 __user *unpc,
0219                         __u32 __user *ustatus);
0220     int (*coredump_extra_notes_size)(void);
0221     int (*coredump_extra_notes_write)(struct coredump_params *cprm);
0222     void (*notify_spus_active)(void);
0223     struct module *owner;
0224 };
0225 
0226 /* return status from spu_run, same as in libspe */
0227 #define SPE_EVENT_DMA_ALIGNMENT     0x0008  /*A DMA alignment error */
0228 #define SPE_EVENT_SPE_ERROR     0x0010  /*An illegal instruction error*/
0229 #define SPE_EVENT_SPE_DATA_SEGMENT  0x0020  /*A DMA segmentation error    */
0230 #define SPE_EVENT_SPE_DATA_STORAGE  0x0040  /*A DMA storage error */
0231 #define SPE_EVENT_INVALID_DMA       0x0800  /* Invalid MFC DMA */
0232 
0233 /*
0234  * Flags for sys_spu_create.
0235  */
0236 #define SPU_CREATE_EVENTS_ENABLED   0x0001
0237 #define SPU_CREATE_GANG         0x0002
0238 #define SPU_CREATE_NOSCHED      0x0004
0239 #define SPU_CREATE_ISOLATE      0x0008
0240 #define SPU_CREATE_AFFINITY_SPU     0x0010
0241 #define SPU_CREATE_AFFINITY_MEM     0x0020
0242 
0243 #define SPU_CREATE_FLAG_ALL     0x003f /* mask of all valid flags */
0244 
0245 
0246 int register_spu_syscalls(struct spufs_calls *calls);
0247 void unregister_spu_syscalls(struct spufs_calls *calls);
0248 
0249 int spu_add_dev_attr(struct device_attribute *attr);
0250 void spu_remove_dev_attr(struct device_attribute *attr);
0251 
0252 int spu_add_dev_attr_group(const struct attribute_group *attrs);
0253 void spu_remove_dev_attr_group(const struct attribute_group *attrs);
0254 
0255 extern void notify_spus_active(void);
0256 extern void do_notify_spus_active(void);
0257 
0258 /*
0259  * This defines the Local Store, Problem Area and Privilege Area of an SPU.
0260  */
0261 
0262 union mfc_tag_size_class_cmd {
0263     struct {
0264         u16 mfc_size;
0265         u16 mfc_tag;
0266         u8  pad;
0267         u8  mfc_rclassid;
0268         u16 mfc_cmd;
0269     } u;
0270     struct {
0271         u32 mfc_size_tag32;
0272         u32 mfc_class_cmd32;
0273     } by32;
0274     u64 all64;
0275 };
0276 
0277 struct mfc_cq_sr {
0278     u64 mfc_cq_data0_RW;
0279     u64 mfc_cq_data1_RW;
0280     u64 mfc_cq_data2_RW;
0281     u64 mfc_cq_data3_RW;
0282 };
0283 
0284 struct spu_problem {
0285 #define MS_SYNC_PENDING         1L
0286     u64 spc_mssync_RW;                  /* 0x0000 */
0287     u8  pad_0x0008_0x3000[0x3000 - 0x0008];
0288 
0289     /* DMA Area */
0290     u8  pad_0x3000_0x3004[0x4];             /* 0x3000 */
0291     u32 mfc_lsa_W;                      /* 0x3004 */
0292     u64 mfc_ea_W;                       /* 0x3008 */
0293     union mfc_tag_size_class_cmd mfc_union_W;           /* 0x3010 */
0294     u8  pad_0x3018_0x3104[0xec];                /* 0x3018 */
0295     u32 dma_qstatus_R;                  /* 0x3104 */
0296     u8  pad_0x3108_0x3204[0xfc];                /* 0x3108 */
0297     u32 dma_querytype_RW;                   /* 0x3204 */
0298     u8  pad_0x3208_0x321c[0x14];                /* 0x3208 */
0299     u32 dma_querymask_RW;                   /* 0x321c */
0300     u8  pad_0x3220_0x322c[0xc];             /* 0x3220 */
0301     u32 dma_tagstatus_R;                    /* 0x322c */
0302 #define DMA_TAGSTATUS_INTR_ANY  1u
0303 #define DMA_TAGSTATUS_INTR_ALL  2u
0304     u8  pad_0x3230_0x4000[0x4000 - 0x3230];         /* 0x3230 */
0305 
0306     /* SPU Control Area */
0307     u8  pad_0x4000_0x4004[0x4];             /* 0x4000 */
0308     u32 pu_mb_R;                        /* 0x4004 */
0309     u8  pad_0x4008_0x400c[0x4];             /* 0x4008 */
0310     u32 spu_mb_W;                       /* 0x400c */
0311     u8  pad_0x4010_0x4014[0x4];             /* 0x4010 */
0312     u32 mb_stat_R;                      /* 0x4014 */
0313     u8  pad_0x4018_0x401c[0x4];             /* 0x4018 */
0314     u32 spu_runcntl_RW;                 /* 0x401c */
0315 #define SPU_RUNCNTL_STOP    0L
0316 #define SPU_RUNCNTL_RUNNABLE    1L
0317 #define SPU_RUNCNTL_ISOLATE 2L
0318     u8  pad_0x4020_0x4024[0x4];             /* 0x4020 */
0319     u32 spu_status_R;                   /* 0x4024 */
0320 #define SPU_STOP_STATUS_SHIFT           16
0321 #define SPU_STATUS_STOPPED      0x0
0322 #define SPU_STATUS_RUNNING      0x1
0323 #define SPU_STATUS_STOPPED_BY_STOP  0x2
0324 #define SPU_STATUS_STOPPED_BY_HALT  0x4
0325 #define SPU_STATUS_WAITING_FOR_CHANNEL  0x8
0326 #define SPU_STATUS_SINGLE_STEP      0x10
0327 #define SPU_STATUS_INVALID_INSTR        0x20
0328 #define SPU_STATUS_INVALID_CH           0x40
0329 #define SPU_STATUS_ISOLATED_STATE       0x80
0330 #define SPU_STATUS_ISOLATED_LOAD_STATUS 0x200
0331 #define SPU_STATUS_ISOLATED_EXIT_STATUS 0x400
0332     u8  pad_0x4028_0x402c[0x4];             /* 0x4028 */
0333     u32 spu_spe_R;                      /* 0x402c */
0334     u8  pad_0x4030_0x4034[0x4];             /* 0x4030 */
0335     u32 spu_npc_RW;                     /* 0x4034 */
0336     u8  pad_0x4038_0x14000[0x14000 - 0x4038];       /* 0x4038 */
0337 
0338     /* Signal Notification Area */
0339     u8  pad_0x14000_0x1400c[0xc];               /* 0x14000 */
0340     u32 signal_notify1;                 /* 0x1400c */
0341     u8  pad_0x14010_0x1c00c[0x7ffc];            /* 0x14010 */
0342     u32 signal_notify2;                 /* 0x1c00c */
0343 } __attribute__ ((aligned(0x20000)));
0344 
0345 /* SPU Privilege 2 State Area */
0346 struct spu_priv2 {
0347     /* MFC Registers */
0348     u8  pad_0x0000_0x1100[0x1100 - 0x0000];         /* 0x0000 */
0349 
0350     /* SLB Management Registers */
0351     u8  pad_0x1100_0x1108[0x8];             /* 0x1100 */
0352     u64 slb_index_W;                    /* 0x1108 */
0353 #define SLB_INDEX_MASK              0x7L
0354     u64 slb_esid_RW;                    /* 0x1110 */
0355     u64 slb_vsid_RW;                    /* 0x1118 */
0356 #define SLB_VSID_SUPERVISOR_STATE   (0x1ull << 11)
0357 #define SLB_VSID_SUPERVISOR_STATE_MASK  (0x1ull << 11)
0358 #define SLB_VSID_PROBLEM_STATE      (0x1ull << 10)
0359 #define SLB_VSID_PROBLEM_STATE_MASK (0x1ull << 10)
0360 #define SLB_VSID_EXECUTE_SEGMENT    (0x1ull << 9)
0361 #define SLB_VSID_NO_EXECUTE_SEGMENT (0x1ull << 9)
0362 #define SLB_VSID_EXECUTE_SEGMENT_MASK   (0x1ull << 9)
0363 #define SLB_VSID_4K_PAGE        (0x0 << 8)
0364 #define SLB_VSID_LARGE_PAGE     (0x1ull << 8)
0365 #define SLB_VSID_PAGE_SIZE_MASK     (0x1ull << 8)
0366 #define SLB_VSID_CLASS_MASK     (0x1ull << 7)
0367 #define SLB_VSID_VIRTUAL_PAGE_SIZE_MASK (0x1ull << 6)
0368     u64 slb_invalidate_entry_W;             /* 0x1120 */
0369     u64 slb_invalidate_all_W;               /* 0x1128 */
0370     u8  pad_0x1130_0x2000[0x2000 - 0x1130];         /* 0x1130 */
0371 
0372     /* Context Save / Restore Area */
0373     struct mfc_cq_sr spuq[16];              /* 0x2000 */
0374     struct mfc_cq_sr puq[8];                /* 0x2200 */
0375     u8  pad_0x2300_0x3000[0x3000 - 0x2300];         /* 0x2300 */
0376 
0377     /* MFC Control */
0378     u64 mfc_control_RW;                 /* 0x3000 */
0379 #define MFC_CNTL_RESUME_DMA_QUEUE       (0ull << 0)
0380 #define MFC_CNTL_SUSPEND_DMA_QUEUE      (1ull << 0)
0381 #define MFC_CNTL_SUSPEND_DMA_QUEUE_MASK     (1ull << 0)
0382 #define MFC_CNTL_SUSPEND_MASK           (1ull << 4)
0383 #define MFC_CNTL_NORMAL_DMA_QUEUE_OPERATION (0ull << 8)
0384 #define MFC_CNTL_SUSPEND_IN_PROGRESS        (1ull << 8)
0385 #define MFC_CNTL_SUSPEND_COMPLETE       (3ull << 8)
0386 #define MFC_CNTL_SUSPEND_DMA_STATUS_MASK    (3ull << 8)
0387 #define MFC_CNTL_DMA_QUEUES_EMPTY       (1ull << 14)
0388 #define MFC_CNTL_DMA_QUEUES_EMPTY_MASK      (1ull << 14)
0389 #define MFC_CNTL_PURGE_DMA_REQUEST      (1ull << 15)
0390 #define MFC_CNTL_PURGE_DMA_IN_PROGRESS      (1ull << 24)
0391 #define MFC_CNTL_PURGE_DMA_COMPLETE     (3ull << 24)
0392 #define MFC_CNTL_PURGE_DMA_STATUS_MASK      (3ull << 24)
0393 #define MFC_CNTL_RESTART_DMA_COMMAND        (1ull << 32)
0394 #define MFC_CNTL_DMA_COMMAND_REISSUE_PENDING    (1ull << 32)
0395 #define MFC_CNTL_DMA_COMMAND_REISSUE_STATUS_MASK (1ull << 32)
0396 #define MFC_CNTL_MFC_PRIVILEGE_STATE        (2ull << 33)
0397 #define MFC_CNTL_MFC_PROBLEM_STATE      (3ull << 33)
0398 #define MFC_CNTL_MFC_KEY_PROTECTION_STATE_MASK  (3ull << 33)
0399 #define MFC_CNTL_DECREMENTER_HALTED     (1ull << 35)
0400 #define MFC_CNTL_DECREMENTER_RUNNING        (1ull << 40)
0401 #define MFC_CNTL_DECREMENTER_STATUS_MASK    (1ull << 40)
0402     u8  pad_0x3008_0x4000[0x4000 - 0x3008];         /* 0x3008 */
0403 
0404     /* Interrupt Mailbox */
0405     u64 puint_mb_R;                     /* 0x4000 */
0406     u8  pad_0x4008_0x4040[0x4040 - 0x4008];         /* 0x4008 */
0407 
0408     /* SPU Control */
0409     u64 spu_privcntl_RW;                    /* 0x4040 */
0410 #define SPU_PRIVCNTL_MODE_NORMAL        (0x0ull << 0)
0411 #define SPU_PRIVCNTL_MODE_SINGLE_STEP       (0x1ull << 0)
0412 #define SPU_PRIVCNTL_MODE_MASK          (0x1ull << 0)
0413 #define SPU_PRIVCNTL_NO_ATTENTION_EVENT     (0x0ull << 1)
0414 #define SPU_PRIVCNTL_ATTENTION_EVENT        (0x1ull << 1)
0415 #define SPU_PRIVCNTL_ATTENTION_EVENT_MASK   (0x1ull << 1)
0416 #define SPU_PRIVCNT_LOAD_REQUEST_NORMAL     (0x0ull << 2)
0417 #define SPU_PRIVCNT_LOAD_REQUEST_ENABLE_MASK    (0x1ull << 2)
0418     u8  pad_0x4048_0x4058[0x10];                /* 0x4048 */
0419     u64 spu_lslr_RW;                    /* 0x4058 */
0420     u64 spu_chnlcntptr_RW;                  /* 0x4060 */
0421     u64 spu_chnlcnt_RW;                 /* 0x4068 */
0422     u64 spu_chnldata_RW;                    /* 0x4070 */
0423     u64 spu_cfg_RW;                     /* 0x4078 */
0424     u8  pad_0x4080_0x5000[0x5000 - 0x4080];         /* 0x4080 */
0425 
0426     /* PV2_ImplRegs: Implementation-specific privileged-state 2 regs */
0427     u64 spu_pm_trace_tag_status_RW;             /* 0x5000 */
0428     u64 spu_tag_status_query_RW;                /* 0x5008 */
0429 #define TAG_STATUS_QUERY_CONDITION_BITS (0x3ull << 32)
0430 #define TAG_STATUS_QUERY_MASK_BITS (0xffffffffull)
0431     u64 spu_cmd_buf1_RW;                    /* 0x5010 */
0432 #define SPU_COMMAND_BUFFER_1_LSA_BITS (0x7ffffull << 32)
0433 #define SPU_COMMAND_BUFFER_1_EAH_BITS (0xffffffffull)
0434     u64 spu_cmd_buf2_RW;                    /* 0x5018 */
0435 #define SPU_COMMAND_BUFFER_2_EAL_BITS ((0xffffffffull) << 32)
0436 #define SPU_COMMAND_BUFFER_2_TS_BITS (0xffffull << 16)
0437 #define SPU_COMMAND_BUFFER_2_TAG_BITS (0x3full)
0438     u64 spu_atomic_status_RW;               /* 0x5020 */
0439 } __attribute__ ((aligned(0x20000)));
0440 
0441 /* SPU Privilege 1 State Area */
0442 struct spu_priv1 {
0443     /* Control and Configuration Area */
0444     u64 mfc_sr1_RW;                     /* 0x000 */
0445 #define MFC_STATE1_LOCAL_STORAGE_DECODE_MASK    0x01ull
0446 #define MFC_STATE1_BUS_TLBIE_MASK       0x02ull
0447 #define MFC_STATE1_REAL_MODE_OFFSET_ENABLE_MASK 0x04ull
0448 #define MFC_STATE1_PROBLEM_STATE_MASK       0x08ull
0449 #define MFC_STATE1_RELOCATE_MASK        0x10ull
0450 #define MFC_STATE1_MASTER_RUN_CONTROL_MASK  0x20ull
0451 #define MFC_STATE1_TABLE_SEARCH_MASK        0x40ull
0452     u64 mfc_lpid_RW;                    /* 0x008 */
0453     u64 spu_idr_RW;                     /* 0x010 */
0454     u64 mfc_vr_RO;                      /* 0x018 */
0455 #define MFC_VERSION_BITS        (0xffff << 16)
0456 #define MFC_REVISION_BITS       (0xffff)
0457 #define MFC_GET_VERSION_BITS(vr)    (((vr) & MFC_VERSION_BITS) >> 16)
0458 #define MFC_GET_REVISION_BITS(vr)   ((vr) & MFC_REVISION_BITS)
0459     u64 spu_vr_RO;                      /* 0x020 */
0460 #define SPU_VERSION_BITS        (0xffff << 16)
0461 #define SPU_REVISION_BITS       (0xffff)
0462 #define SPU_GET_VERSION_BITS(vr)    (vr & SPU_VERSION_BITS) >> 16
0463 #define SPU_GET_REVISION_BITS(vr)   (vr & SPU_REVISION_BITS)
0464     u8  pad_0x28_0x100[0x100 - 0x28];           /* 0x28 */
0465 
0466     /* Interrupt Area */
0467     u64 int_mask_RW[3];                 /* 0x100 */
0468 #define CLASS0_ENABLE_DMA_ALIGNMENT_INTR        0x1L
0469 #define CLASS0_ENABLE_INVALID_DMA_COMMAND_INTR      0x2L
0470 #define CLASS0_ENABLE_SPU_ERROR_INTR            0x4L
0471 #define CLASS0_ENABLE_MFC_FIR_INTR          0x8L
0472 #define CLASS1_ENABLE_SEGMENT_FAULT_INTR        0x1L
0473 #define CLASS1_ENABLE_STORAGE_FAULT_INTR        0x2L
0474 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_GET_INTR    0x4L
0475 #define CLASS1_ENABLE_LS_COMPARE_SUSPEND_ON_PUT_INTR    0x8L
0476 #define CLASS2_ENABLE_MAILBOX_INTR          0x1L
0477 #define CLASS2_ENABLE_SPU_STOP_INTR         0x2L
0478 #define CLASS2_ENABLE_SPU_HALT_INTR         0x4L
0479 #define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR   0x8L
0480 #define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR        0x10L
0481     u8  pad_0x118_0x140[0x28];              /* 0x118 */
0482     u64 int_stat_RW[3];                 /* 0x140 */
0483 #define CLASS0_DMA_ALIGNMENT_INTR           0x1L
0484 #define CLASS0_INVALID_DMA_COMMAND_INTR         0x2L
0485 #define CLASS0_SPU_ERROR_INTR               0x4L
0486 #define CLASS0_INTR_MASK                0x7L
0487 #define CLASS1_SEGMENT_FAULT_INTR           0x1L
0488 #define CLASS1_STORAGE_FAULT_INTR           0x2L
0489 #define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR       0x4L
0490 #define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR       0x8L
0491 #define CLASS1_INTR_MASK                0xfL
0492 #define CLASS2_MAILBOX_INTR             0x1L
0493 #define CLASS2_SPU_STOP_INTR                0x2L
0494 #define CLASS2_SPU_HALT_INTR                0x4L
0495 #define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR      0x8L
0496 #define CLASS2_MAILBOX_THRESHOLD_INTR           0x10L
0497 #define CLASS2_INTR_MASK                0x1fL
0498     u8  pad_0x158_0x180[0x28];              /* 0x158 */
0499     u64 int_route_RW;                   /* 0x180 */
0500 
0501     /* Interrupt Routing */
0502     u8  pad_0x188_0x200[0x200 - 0x188];         /* 0x188 */
0503 
0504     /* Atomic Unit Control Area */
0505     u64 mfc_atomic_flush_RW;                /* 0x200 */
0506 #define mfc_atomic_flush_enable         0x1L
0507     u8  pad_0x208_0x280[0x78];              /* 0x208 */
0508     u64 resource_allocation_groupID_RW;         /* 0x280 */
0509     u64 resource_allocation_enable_RW;          /* 0x288 */
0510     u8  pad_0x290_0x3c8[0x3c8 - 0x290];         /* 0x290 */
0511 
0512     /* SPU_Cache_ImplRegs: Implementation-dependent cache registers */
0513 
0514     u64 smf_sbi_signal_sel;                 /* 0x3c8 */
0515 #define smf_sbi_mask_lsb    56
0516 #define smf_sbi_shift       (63 - smf_sbi_mask_lsb)
0517 #define smf_sbi_mask        (0x301LL << smf_sbi_shift)
0518 #define smf_sbi_bus0_bits   (0x001LL << smf_sbi_shift)
0519 #define smf_sbi_bus2_bits   (0x100LL << smf_sbi_shift)
0520 #define smf_sbi2_bus0_bits  (0x201LL << smf_sbi_shift)
0521 #define smf_sbi2_bus2_bits  (0x300LL << smf_sbi_shift)
0522     u64 smf_ato_signal_sel;                 /* 0x3d0 */
0523 #define smf_ato_mask_lsb    35
0524 #define smf_ato_shift       (63 - smf_ato_mask_lsb)
0525 #define smf_ato_mask        (0x3LL << smf_ato_shift)
0526 #define smf_ato_bus0_bits   (0x2LL << smf_ato_shift)
0527 #define smf_ato_bus2_bits   (0x1LL << smf_ato_shift)
0528     u8  pad_0x3d8_0x400[0x400 - 0x3d8];         /* 0x3d8 */
0529 
0530     /* TLB Management Registers */
0531     u64 mfc_sdr_RW;                     /* 0x400 */
0532     u8  pad_0x408_0x500[0xf8];              /* 0x408 */
0533     u64 tlb_index_hint_RO;                  /* 0x500 */
0534     u64 tlb_index_W;                    /* 0x508 */
0535     u64 tlb_vpn_RW;                     /* 0x510 */
0536     u64 tlb_rpn_RW;                     /* 0x518 */
0537     u8  pad_0x520_0x540[0x20];              /* 0x520 */
0538     u64 tlb_invalidate_entry_W;             /* 0x540 */
0539     u64 tlb_invalidate_all_W;               /* 0x548 */
0540     u8  pad_0x550_0x580[0x580 - 0x550];         /* 0x550 */
0541 
0542     /* SPU_MMU_ImplRegs: Implementation-dependent MMU registers */
0543     u64 smm_hid;                        /* 0x580 */
0544 #define PAGE_SIZE_MASK      0xf000000000000000ull
0545 #define PAGE_SIZE_16MB_64KB 0x2000000000000000ull
0546     u8  pad_0x588_0x600[0x600 - 0x588];         /* 0x588 */
0547 
0548     /* MFC Status/Control Area */
0549     u64 mfc_accr_RW;                    /* 0x600 */
0550 #define MFC_ACCR_EA_ACCESS_GET      (1 << 0)
0551 #define MFC_ACCR_EA_ACCESS_PUT      (1 << 1)
0552 #define MFC_ACCR_LS_ACCESS_GET      (1 << 3)
0553 #define MFC_ACCR_LS_ACCESS_PUT      (1 << 4)
0554     u8  pad_0x608_0x610[0x8];               /* 0x608 */
0555     u64 mfc_dsisr_RW;                   /* 0x610 */
0556 #define MFC_DSISR_PTE_NOT_FOUND     (1 << 30)
0557 #define MFC_DSISR_ACCESS_DENIED     (1 << 27)
0558 #define MFC_DSISR_ATOMIC        (1 << 26)
0559 #define MFC_DSISR_ACCESS_PUT        (1 << 25)
0560 #define MFC_DSISR_ADDR_MATCH        (1 << 22)
0561 #define MFC_DSISR_LS            (1 << 17)
0562 #define MFC_DSISR_L         (1 << 16)
0563 #define MFC_DSISR_ADDRESS_OVERFLOW  (1 << 0)
0564     u8  pad_0x618_0x620[0x8];               /* 0x618 */
0565     u64 mfc_dar_RW;                     /* 0x620 */
0566     u8  pad_0x628_0x700[0x700 - 0x628];         /* 0x628 */
0567 
0568     /* Replacement Management Table (RMT) Area */
0569     u64 rmt_index_RW;                   /* 0x700 */
0570     u8  pad_0x708_0x710[0x8];               /* 0x708 */
0571     u64 rmt_data1_RW;                   /* 0x710 */
0572     u8  pad_0x718_0x800[0x800 - 0x718];         /* 0x718 */
0573 
0574     /* Control/Configuration Registers */
0575     u64 mfc_dsir_R;                     /* 0x800 */
0576 #define MFC_DSIR_Q          (1 << 31)
0577 #define MFC_DSIR_SPU_QUEUE      MFC_DSIR_Q
0578     u64 mfc_lsacr_RW;                   /* 0x808 */
0579 #define MFC_LSACR_COMPARE_MASK      ((~0ull) << 32)
0580 #define MFC_LSACR_COMPARE_ADDR      ((~0ull) >> 32)
0581     u64 mfc_lscrr_R;                    /* 0x810 */
0582 #define MFC_LSCRR_Q         (1 << 31)
0583 #define MFC_LSCRR_SPU_QUEUE     MFC_LSCRR_Q
0584 #define MFC_LSCRR_QI_SHIFT      32
0585 #define MFC_LSCRR_QI_MASK       ((~0ull) << MFC_LSCRR_QI_SHIFT)
0586     u8  pad_0x818_0x820[0x8];               /* 0x818 */
0587     u64 mfc_tclass_id_RW;                   /* 0x820 */
0588 #define MFC_TCLASS_ID_ENABLE        (1L << 0L)
0589 #define MFC_TCLASS_SLOT2_ENABLE     (1L << 5L)
0590 #define MFC_TCLASS_SLOT1_ENABLE     (1L << 6L)
0591 #define MFC_TCLASS_SLOT0_ENABLE     (1L << 7L)
0592 #define MFC_TCLASS_QUOTA_2_SHIFT    8L
0593 #define MFC_TCLASS_QUOTA_1_SHIFT    16L
0594 #define MFC_TCLASS_QUOTA_0_SHIFT    24L
0595 #define MFC_TCLASS_QUOTA_2_MASK     (0x1FL << MFC_TCLASS_QUOTA_2_SHIFT)
0596 #define MFC_TCLASS_QUOTA_1_MASK     (0x1FL << MFC_TCLASS_QUOTA_1_SHIFT)
0597 #define MFC_TCLASS_QUOTA_0_MASK     (0x1FL << MFC_TCLASS_QUOTA_0_SHIFT)
0598     u8  pad_0x828_0x900[0x900 - 0x828];         /* 0x828 */
0599 
0600     /* Real Mode Support Registers */
0601     u64 mfc_rm_boundary;                    /* 0x900 */
0602     u8  pad_0x908_0x938[0x30];              /* 0x908 */
0603     u64 smf_dma_signal_sel;                 /* 0x938 */
0604 #define mfc_dma1_mask_lsb   41
0605 #define mfc_dma1_shift      (63 - mfc_dma1_mask_lsb)
0606 #define mfc_dma1_mask       (0x3LL << mfc_dma1_shift)
0607 #define mfc_dma1_bits       (0x1LL << mfc_dma1_shift)
0608 #define mfc_dma2_mask_lsb   43
0609 #define mfc_dma2_shift      (63 - mfc_dma2_mask_lsb)
0610 #define mfc_dma2_mask       (0x3LL << mfc_dma2_shift)
0611 #define mfc_dma2_bits       (0x1LL << mfc_dma2_shift)
0612     u8  pad_0x940_0xa38[0xf8];              /* 0x940 */
0613     u64 smm_signal_sel;                 /* 0xa38 */
0614 #define smm_sig_mask_lsb    12
0615 #define smm_sig_shift       (63 - smm_sig_mask_lsb)
0616 #define smm_sig_mask        (0x3LL << smm_sig_shift)
0617 #define smm_sig_bus0_bits   (0x2LL << smm_sig_shift)
0618 #define smm_sig_bus2_bits   (0x1LL << smm_sig_shift)
0619     u8  pad_0xa40_0xc00[0xc00 - 0xa40];         /* 0xa40 */
0620 
0621     /* DMA Command Error Area */
0622     u64 mfc_cer_R;                      /* 0xc00 */
0623 #define MFC_CER_Q       (1 << 31)
0624 #define MFC_CER_SPU_QUEUE   MFC_CER_Q
0625     u8  pad_0xc08_0x1000[0x1000 - 0xc08];           /* 0xc08 */
0626 
0627     /* PV1_ImplRegs: Implementation-dependent privileged-state 1 regs */
0628     /* DMA Command Error Area */
0629     u64 spu_ecc_cntl_RW;                    /* 0x1000 */
0630 #define SPU_ECC_CNTL_E          (1ull << 0ull)
0631 #define SPU_ECC_CNTL_ENABLE     SPU_ECC_CNTL_E
0632 #define SPU_ECC_CNTL_DISABLE        (~SPU_ECC_CNTL_E & 1L)
0633 #define SPU_ECC_CNTL_S          (1ull << 1ull)
0634 #define SPU_ECC_STOP_AFTER_ERROR    SPU_ECC_CNTL_S
0635 #define SPU_ECC_CONTINUE_AFTER_ERROR    (~SPU_ECC_CNTL_S & 2L)
0636 #define SPU_ECC_CNTL_B          (1ull << 2ull)
0637 #define SPU_ECC_BACKGROUND_ENABLE   SPU_ECC_CNTL_B
0638 #define SPU_ECC_BACKGROUND_DISABLE  (~SPU_ECC_CNTL_B & 4L)
0639 #define SPU_ECC_CNTL_I_SHIFT        3ull
0640 #define SPU_ECC_CNTL_I_MASK     (3ull << SPU_ECC_CNTL_I_SHIFT)
0641 #define SPU_ECC_WRITE_ALWAYS        (~SPU_ECC_CNTL_I & 12L)
0642 #define SPU_ECC_WRITE_CORRECTABLE   (1ull << SPU_ECC_CNTL_I_SHIFT)
0643 #define SPU_ECC_WRITE_UNCORRECTABLE (3ull << SPU_ECC_CNTL_I_SHIFT)
0644 #define SPU_ECC_CNTL_D          (1ull << 5ull)
0645 #define SPU_ECC_DETECTION_ENABLE    SPU_ECC_CNTL_D
0646 #define SPU_ECC_DETECTION_DISABLE   (~SPU_ECC_CNTL_D & 32L)
0647     u64 spu_ecc_stat_RW;                    /* 0x1008 */
0648 #define SPU_ECC_CORRECTED_ERROR     (1ull << 0ul)
0649 #define SPU_ECC_UNCORRECTED_ERROR   (1ull << 1ul)
0650 #define SPU_ECC_SCRUB_COMPLETE      (1ull << 2ul)
0651 #define SPU_ECC_SCRUB_IN_PROGRESS   (1ull << 3ul)
0652 #define SPU_ECC_INSTRUCTION_ERROR   (1ull << 4ul)
0653 #define SPU_ECC_DATA_ERROR      (1ull << 5ul)
0654 #define SPU_ECC_DMA_ERROR       (1ull << 6ul)
0655 #define SPU_ECC_STATUS_CNT_MASK     (256ull << 8)
0656     u64 spu_ecc_addr_RW;                    /* 0x1010 */
0657     u64 spu_err_mask_RW;                    /* 0x1018 */
0658 #define SPU_ERR_ILLEGAL_INSTR       (1ull << 0ul)
0659 #define SPU_ERR_ILLEGAL_CHANNEL     (1ull << 1ul)
0660     u8  pad_0x1020_0x1028[0x1028 - 0x1020];         /* 0x1020 */
0661 
0662     /* SPU Debug-Trace Bus (DTB) Selection Registers */
0663     u64 spu_trig0_sel;                  /* 0x1028 */
0664     u64 spu_trig1_sel;                  /* 0x1030 */
0665     u64 spu_trig2_sel;                  /* 0x1038 */
0666     u64 spu_trig3_sel;                  /* 0x1040 */
0667     u64 spu_trace_sel;                  /* 0x1048 */
0668 #define spu_trace_sel_mask      0x1f1fLL
0669 #define spu_trace_sel_bus0_bits     0x1000LL
0670 #define spu_trace_sel_bus2_bits     0x0010LL
0671     u64 spu_event0_sel;                 /* 0x1050 */
0672     u64 spu_event1_sel;                 /* 0x1058 */
0673     u64 spu_event2_sel;                 /* 0x1060 */
0674     u64 spu_event3_sel;                 /* 0x1068 */
0675     u64 spu_trace_cntl;                 /* 0x1070 */
0676 } __attribute__ ((aligned(0x2000)));
0677 
0678 #endif /* __KERNEL__ */
0679 #endif
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