include/asm/security_features.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Security related feature bit definitions.
0004  *
0005  * Copyright 2018, Michael Ellerman, IBM Corporation.
0006  */
0007
0008 #ifndef _ASM_POWERPC_SECURITY_FEATURES_H
0009 #define _ASM_POWERPC_SECURITY_FEATURES_H
0010
0011
0012 extern u64 powerpc_security_features;
0013 extern bool rfi_flush;
0014
0015 /* These are bit flags */
0016 enum stf_barrier_type {
0017     STF_BARRIER_NONE    = 0x1,
0018     STF_BARRIER_FALLBACK    = 0x2,
0019     STF_BARRIER_EIEIO   = 0x4,
0020     STF_BARRIER_SYNC_ORI    = 0x8,
0021 };
0022
0023 void setup_stf_barrier(void);
0024 void do_stf_barrier_fixups(enum stf_barrier_type types);
0025 void setup_count_cache_flush(void);
0026
0027 static inline void security_ftr_set(u64 feature)
0028 {
0029     powerpc_security_features |= feature;
0030 }
0031
0032 static inline void security_ftr_clear(u64 feature)
0033 {
0034     powerpc_security_features &= ~feature;
0035 }
0036
0037 static inline bool security_ftr_enabled(u64 feature)
0038 {
0039     return !!(powerpc_security_features & feature);
0040 }
0041
0042 #ifdef CONFIG_PPC_BOOK3S_64
0043 enum stf_barrier_type stf_barrier_type_get(void);
0044 #else
0045 static inline enum stf_barrier_type stf_barrier_type_get(void) { return STF_BARRIER_NONE; }
0046 #endif
0047
0048 // Features indicating support for Spectre/Meltdown mitigations
0049
0050 // The L1-D cache can be flushed with ori r30,r30,0
0051 #define SEC_FTR_L1D_FLUSH_ORI30     0x0000000000000001ull
0052
0053 // The L1-D cache can be flushed with mtspr 882,r0 (aka SPRN_TRIG2)
0054 #define SEC_FTR_L1D_FLUSH_TRIG2     0x0000000000000002ull
0055
0056 // ori r31,r31,0 acts as a speculation barrier
0057 #define SEC_FTR_SPEC_BAR_ORI31      0x0000000000000004ull
0058
0059 // Speculation past bctr is disabled
0060 #define SEC_FTR_BCCTRL_SERIALISED   0x0000000000000008ull
0061
0062 // Entries in L1-D are private to a SMT thread
0063 #define SEC_FTR_L1D_THREAD_PRIV     0x0000000000000010ull
0064
0065 // Indirect branch prediction cache disabled
0066 #define SEC_FTR_COUNT_CACHE_DISABLED    0x0000000000000020ull
0067
0068 // bcctr 2,0,0 triggers a hardware assisted count cache flush
0069 #define SEC_FTR_BCCTR_FLUSH_ASSIST  0x0000000000000800ull
0070
0071 // bcctr 2,0,0 triggers a hardware assisted link stack flush
0072 #define SEC_FTR_BCCTR_LINK_FLUSH_ASSIST 0x0000000000002000ull
0073
0074 // Features indicating need for Spectre/Meltdown mitigations
0075
0076 // The L1-D cache should be flushed on MSR[HV] 1->0 transition (hypervisor to guest)
0077 #define SEC_FTR_L1D_FLUSH_HV        0x0000000000000040ull
0078
0079 // The L1-D cache should be flushed on MSR[PR] 0->1 transition (kernel to userspace)
0080 #define SEC_FTR_L1D_FLUSH_PR        0x0000000000000080ull
0081
0082 // A speculation barrier should be used for bounds checks (Spectre variant 1)
0083 #define SEC_FTR_BNDS_CHK_SPEC_BAR   0x0000000000000100ull
0084
0085 // Firmware configuration indicates user favours security over performance
0086 #define SEC_FTR_FAVOUR_SECURITY     0x0000000000000200ull
0087
0088 // Software required to flush count cache on context switch
0089 #define SEC_FTR_FLUSH_COUNT_CACHE   0x0000000000000400ull
0090
0091 // Software required to flush link stack on context switch
0092 #define SEC_FTR_FLUSH_LINK_STACK    0x0000000000001000ull
0093
0094 // The L1-D cache should be flushed when entering the kernel
0095 #define SEC_FTR_L1D_FLUSH_ENTRY     0x0000000000004000ull
0096
0097 // The L1-D cache should be flushed after user accesses from the kernel
0098 #define SEC_FTR_L1D_FLUSH_UACCESS   0x0000000000008000ull
0099
0100 // The STF flush should be executed on privilege state switch
0101 #define SEC_FTR_STF_BARRIER     0x0000000000010000ull
0102
0103 // Features enabled by default
0104 #define SEC_FTR_DEFAULT \
0105     (SEC_FTR_L1D_FLUSH_HV | \
0106      SEC_FTR_L1D_FLUSH_PR | \
0107      SEC_FTR_BNDS_CHK_SPEC_BAR | \
0108      SEC_FTR_L1D_FLUSH_ENTRY | \
0109      SEC_FTR_L1D_FLUSH_UACCESS | \
0110      SEC_FTR_STF_BARRIER | \
0111      SEC_FTR_FAVOUR_SECURITY)
0112
0113 #endif /* _ASM_POWERPC_SECURITY_FEATURES_H */